llvm.org GIT mirror llvm / 181eb73
Some platforms use the same name for 32-bit and 64-bit registers (like %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 12 years ago
5 changed file(s) with 58 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
4848 ///
4949 struct TargetRegisterDesc {
5050 const char *Name; // Assembly language name for the register
51 const char *PrintableName;// Printable name for the reg (for debugging)
5152 const unsigned *AliasSet; // Register Alias Set, described above
5253 const unsigned *SubRegs; // Sub-register set, described above
5354 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
380381 return get(RegNo).Name;
381382 }
382383
384 /// getPrintableName - Return the human-readable symbolic target specific name
385 /// for the specified physical register.
386 const char *getPrintableName(unsigned RegNo) const {
387 return get(RegNo).PrintableName;
388 }
389
383390 /// getNumRegs - Return the number of registers this target has (useful for
384391 /// sizing arrays holding per register information)
385392 unsigned getNumRegs() const {
173173 TM = &MF->getTarget();
174174
175175 if (TM)
176 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
176 OS << "%" << TM->getRegisterInfo()->get(getReg()).PrintableName;
177177 else
178178 OS << "%mreg" << getReg();
179179 }
189189 NeedComma = true;
190190 }
191191 if (isKill() || isDead()) {
192 if (NeedComma) OS << ",";
193 if (isKill()) OS << "kill";
194 if (isDead()) OS << "dead";
192 if (NeedComma) OS << ",";
193 if (isKill()) OS << "kill";
194 if (isDead()) OS << "dead";
195195 }
196196 OS << ">";
197197 }
None //===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
0 //===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
2121 }
2222
2323 // GP8 - One of the 32 64-bit general-purpose registers
24 class GP8> : PPCReg {
24 class GP8, string n> : PPCReg {
2525 field bits<5> Num = SubReg.Num;
2626 let SubRegs = [SubReg];
27 let PrintableName = n;
2728 }
2829
2930 // SPR - One of the 32-bit special-purpose registers
8788 def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
8889
8990 // 64-bit General-purpose registers
90 def X0 : GP8< R0>, DwarfRegNum<[0]>;
91 def X1 : GP8< R1>, DwarfRegNum<[1]>;
92 def X2 : GP8< R2>, DwarfRegNum<[2]>;
93 def X3 : GP8< R3>, DwarfRegNum<[3]>;
94 def X4 : GP8< R4>, DwarfRegNum<[4]>;
95 def X5 : GP8< R5>, DwarfRegNum<[5]>;
96 def X6 : GP8< R6>, DwarfRegNum<[6]>;
97 def X7 : GP8< R7>, DwarfRegNum<[7]>;
98 def X8 : GP8< R8>, DwarfRegNum<[8]>;
99 def X9 : GP8< R9>, DwarfRegNum<[9]>;
100 def X10 : GP8, DwarfRegNum<[10]>;
101 def X11 : GP8, DwarfRegNum<[11]>;
102 def X12 : GP8, DwarfRegNum<[12]>;
103 def X13 : GP8, DwarfRegNum<[13]>;
104 def X14 : GP8, DwarfRegNum<[14]>;
105 def X15 : GP8, DwarfRegNum<[15]>;
106 def X16 : GP8, DwarfRegNum<[16]>;
107 def X17 : GP8, DwarfRegNum<[17]>;
108 def X18 : GP8, DwarfRegNum<[18]>;
109 def X19 : GP8, DwarfRegNum<[19]>;
110 def X20 : GP8, DwarfRegNum<[20]>;
111 def X21 : GP8, DwarfRegNum<[21]>;
112 def X22 : GP8, DwarfRegNum<[22]>;
113 def X23 : GP8, DwarfRegNum<[23]>;
114 def X24 : GP8, DwarfRegNum<[24]>;
115 def X25 : GP8, DwarfRegNum<[25]>;
116 def X26 : GP8, DwarfRegNum<[26]>;
117 def X27 : GP8, DwarfRegNum<[27]>;
118 def X28 : GP8, DwarfRegNum<[28]>;
119 def X29 : GP8, DwarfRegNum<[29]>;
120 def X30 : GP8, DwarfRegNum<[30]>;
121 def X31 : GP8, DwarfRegNum<[31]>;
91 def X0 : GP8< R0, "x0">, DwarfRegNum<[0]>;
92 def X1 : GP8< R1, "x1">, DwarfRegNum<[1]>;
93 def X2 : GP8< R2, "x2">, DwarfRegNum<[2]>;
94 def X3 : GP8< R3, "x3">, DwarfRegNum<[3]>;
95 def X4 : GP8< R4, "x4">, DwarfRegNum<[4]>;
96 def X5 : GP8< R5, "x5">, DwarfRegNum<[5]>;
97 def X6 : GP8< R6, "x6">, DwarfRegNum<[6]>;
98 def X7 : GP8< R7, "x7">, DwarfRegNum<[7]>;
99 def X8 : GP8< R8, "x8">, DwarfRegNum<[8]>;
100 def X9 : GP8< R9, "x9">, DwarfRegNum<[9]>;
101 def X10 : GP8, DwarfRegNum<[10]>;
102 def X11 : GP8, DwarfRegNum<[11]>;
103 def X12 : GP8, DwarfRegNum<[12]>;
104 def X13 : GP8, DwarfRegNum<[13]>;
105 def X14 : GP8, DwarfRegNum<[14]>;
106 def X15 : GP8, DwarfRegNum<[15]>;
107 def X16 : GP8, DwarfRegNum<[16]>;
108 def X17 : GP8, DwarfRegNum<[17]>;
109 def X18 : GP8, DwarfRegNum<[18]>;
110 def X19 : GP8, DwarfRegNum<[19]>;
111 def X20 : GP8, DwarfRegNum<[20]>;
112 def X21 : GP8, DwarfRegNum<[21]>;
113 def X22 : GP8, DwarfRegNum<[22]>;
114 def X23 : GP8, DwarfRegNum<[23]>;
115 def X24 : GP8, DwarfRegNum<[24]>;
116 def X25 : GP8, DwarfRegNum<[25]>;
117 def X26 : GP8, DwarfRegNum<[26]>;
118 def X27 : GP8, DwarfRegNum<[27]>;
119 def X28 : GP8, DwarfRegNum<[28]>;
120 def X29 : GP8, DwarfRegNum<[29]>;
121 def X30 : GP8, DwarfRegNum<[30]>;
122 def X31 : GP8, DwarfRegNum<[31]>;
122123
123124 // Floating-point registers
124125 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
2525 class Register {
2626 string Namespace = "";
2727 string Name = n;
28 string PrintableName = n;
2829
2930 // SpillSize - If this value is set to a non-zero value, it is the size in
3031 // bits of the spill slot required to hold this register. If this value is
511511 }
512512
513513 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
514 OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
514 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n";
515515
516516 // Now that register alias and sub-registers sets have been emitted, emit the
517517 // register descriptors now.
523523 OS << Reg.TheDef->getValueAsString("Name");
524524 else
525525 OS << Reg.getName();
526 OS << "\",\t\"";
527 if (!Reg.TheDef->getValueAsString("PrintableName").empty()) {
528 OS << Reg.TheDef->getValueAsString("PrintableName");
529 } else {
530 // Default to "name".
531 if (!Reg.TheDef->getValueAsString("Name").empty())
532 OS << Reg.TheDef->getValueAsString("Name");
533 else
534 OS << Reg.getName();
535 }
526536 OS << "\",\t";
527537 if (RegisterAliases.count(Reg.TheDef))
528538 OS << Reg.getName() << "_AliasSet,\t";