llvm.org GIT mirror llvm / 17d47e4
Fix these test cases to not use .bc files. Otherwise, we run into issues with bitcode reader/writer backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142896 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 9 years ago
4 changed file(s) with 97 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
22 ;
33 ; Rdar: 9472944
44 ;
5 ; RUN: llvm-dis < %s.bc | FileCheck %s
5 ; RUN: opt < %s | llvm-dis | FileCheck %s
66
77 ; crc32.8 should upgrade to crc32.32.8
88 ; CHECK: i32 @llvm.x86.sse42.crc32.32.8(
2525 ; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64(
2626
2727
28 define void @foo() nounwind readnone ssp {
29 entry:
30 %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0)
31 %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0)
32 %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0)
33 %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0)
34 %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0)
35 ret void
36 }
37
38 declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone
39 declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone
40 declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone
41 declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone
42 declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone
test/Bitcode/sse42_crc32.ll.bc less more
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None ; RUN: llvm-dis < %s.bc | FileCheck %s
0 ; RUN: opt < %s | llvm-dis | FileCheck %s
11 ; CHECK-NOT: {@llvm\\.palign}
2
3 define <4 x i32> @align1(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
4 entry:
5 %0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
6 %1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
7 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
8 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
9 ret <4 x i32> %3
10 }
11
12 define double @align8(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
13 entry:
14 %0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
15 %1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
16 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
17 %3 = extractelement <1 x i64> %2, i32 0 ; [#uses=1]
18 %retval12 = bitcast i64 %3 to double ; [#uses=1]
19 ret double %retval12
20 }
21
22 declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
23
24 define double @align7(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
25 entry:
26 %0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
27 %1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
28 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
29 %3 = extractelement <1 x i64> %2, i32 0 ; [#uses=1]
30 %retval12 = bitcast i64 %3 to double ; [#uses=1]
31 ret double %retval12
32 }
33
34 define double @align6(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
35 entry:
36 %0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
37 %1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
38 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
39 %3 = extractelement <1 x i64> %2, i32 0 ; [#uses=1]
40 %retval12 = bitcast i64 %3 to double ; [#uses=1]
41 ret double %retval12
42 }
43
44 define double @align5(<2 x i32> %a, <2 x i32> %b) nounwind readnone ssp {
45 entry:
46 %0 = bitcast <2 x i32> %b to <1 x i64> ; <<1 x i64>> [#uses=1]
47 %1 = bitcast <2 x i32> %a to <1 x i64> ; <<1 x i64>> [#uses=1]
48 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
49 %3 = extractelement <1 x i64> %2, i32 0 ; [#uses=1]
50 %retval12 = bitcast i64 %3 to double ; [#uses=1]
51 ret double %retval12
52 }
53
54 define <4 x i32> @align4(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
55 entry:
56 %0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
57 %1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
58 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
59 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
60 ret <4 x i32> %3
61 }
62
63 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
64
65 define <4 x i32> @align3(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
66 entry:
67 %0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
68 %1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
69 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
70 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
71 ret <4 x i32> %3
72 }
73
74 define <4 x i32> @align2(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
75 entry:
76 %0 = bitcast <4 x i32> %b to <2 x i64> ; <<2 x i64>> [#uses=1]
77 %1 = bitcast <4 x i32> %a to <2 x i64> ; <<2 x i64>> [#uses=1]
78 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1]
79 %3 = bitcast <2 x i64> %2 to <4 x i32> ; <<4 x i32>> [#uses=1]
80 ret <4 x i32> %3
81 }
test/Bitcode/ssse3_palignr.ll.bc less more
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