llvm.org GIT mirror llvm / 17b2b19
Merging r142350: ------------------------------------------------------------------------ r142350 | baldrick | 2011-10-18 05:44:00 -0700 (Tue, 18 Oct 2011) | 3 lines Fix a bunch of unused variable warnings when doing a release build with gcc-4.6. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_30@142609 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
6 changed file(s) with 11 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
265265 // Implement VSELECT in terms of XOR, AND, OR
266266 // on platforms which do not support blend natively.
267267 EVT VT = Op.getOperand(0).getValueType();
268 EVT OVT = Op.getOperand(1).getValueType();
269268 DebugLoc DL = Op.getDebugLoc();
270269
271270 SDValue Mask = Op.getOperand(0);
279278 !TLI.isOperationLegalOrCustom(ISD::OR, VT))
280279 return DAG.UnrollVectorOp(Op.getNode());
281280
282 assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
281 assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
282 && "Invalid mask size");
283283 // Bitcast the operands to be the same type as the mask.
284284 // This is needed when we select between FP types because
285285 // the mask is a vector of integers.
27992799 EVT.getVectorNumElements() == VT.getVectorNumElements()) &&
28002800 "Vector element counts must match in FP_ROUND_INREG");
28012801 assert(EVT.bitsLE(VT) && "Not rounding down!");
2802 (void)EVT;
28022803 if (cast(N2)->getVT() == VT) return N1; // Not actually rounding.
28032804 break;
28042805 }
24732473 size_t numCmps = Clusterify(Cases, SI);
24742474 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
24752475 << ". Total compares: " << numCmps << '\n');
2476 numCmps = 0;
2476 (void)numCmps;
24772477
24782478 // Get the Value to be switched on and default basic blocks, which will be
24792479 // inserted into CaseBlock records, representing basic blocks in the binary
48994899 static void
49004900 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl& Results,
49014901 SelectionDAG &DAG, unsigned NewOp) {
4902 EVT T = Node->getValueType(0);
49034902 DebugLoc dl = Node->getDebugLoc();
4904 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
4903 assert (Node->getValueType(0) == MVT::i64 &&
4904 "Only know how to expand i64 atomics");
49054905
49064906 SmallVector Ops;
49074907 Ops.push_back(Node->getOperand(0)); // Chain
11121112 // Skip the saved EBP.
11131113 Offset += RI->getSlotSize();
11141114 } else {
1115 unsigned Align = MFI->getObjectAlignment(FI);
1116 assert((-(Offset + StackSize)) % Align == 0);
1117 Align = 0;
1115 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
11181116 return Offset + StackSize;
11191117 }
11201118 // FIXME: Support tail calls
12661264 true);
12671265 assert(FrameIdx == MFI->getObjectIndexBegin() &&
12681266 "Slot for EBP register must be last in order to be found!");
1269 FrameIdx = 0;
1267 (void)FrameIdx;
12701268 }
12711269 }
12721270
17521752 // places.
17531753 assert(VA.getValNo() != LastVal &&
17541754 "Don't support value assigned to multiple locs yet");
1755 (void)LastVal;
17551756 LastVal = VA.getValNo();
17561757
17571758 if (VA.isRegLoc()) {
1047610477 void X86TargetLowering::
1047710478 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl&Results,
1047810479 SelectionDAG &DAG, unsigned NewOp) const {
10479 EVT T = Node->getValueType(0);
1048010480 DebugLoc dl = Node->getDebugLoc();
10481 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10481 assert (Node->getValueType(0) == MVT::i64 &&
10482 "Only know how to expand i64 atomics");
1048210483
1048310484 SDValue Chain = Node->getOperand(0);
1048410485 SDValue In1 = Node->getOperand(1);