llvm.org GIT mirror llvm / 17ab24c
[TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328031 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
6 changed file(s) with 99 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
None =============================
0 ============================
11 User Guide for AMDGPU Backend
22 =============================
33
26552655 The AMDGPU code generator lives in the ``lib/Target/AMDGPU``
26562656 directory. This code generator is capable of targeting a variety of
26572657 AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information.
2658
2659 The X86 backend
2660 ------------------
2661
2662 The X86 code generator lives in the ``lib/Target/X86``
2663 directory. Refer to :doc:`X86Usage` for more information.
9898 * `X86 and X86-64 SysV psABI `_
9999 * `Calling conventions for different C++ compilers and operating systems `_
100100
101 Refer to :doc:`X86Usage` for additional documentation.
102
101103 XCore
102104 -----
103105
0 =============================
1 User Guide for X86 Backend
2 =============================
3
4 .. contents::
5 :local:
6
7 Introduction
8 ============
9
10 The X86 backend provides ISA code generation for X86 CPUs. It lives in the
11 ``lib/Target/X86`` directory.
12
13 LLVM
14 ====
15
16 .. _x86-processors
17
18 Processors
19 ----------
20
21 Use the ``clang -march=`` option to specify the X86 processor.
22
23 .. table:: X86 processors
24 :name: x86-processor-table
25
26 ================== ===================
27 Processor Alternative
28 Name
29 ``i386``
30 ``i486``
31 ``i586``
32 ``pentium``
33 ``pentium-mmx``
34 ``i686``
35 ``pentiumpro``
36 ``pentium2``
37 ``pentium3`` - ``pentium3m``
38 ``pentium-m``
39 ``pentium4`` - ``pentium4m``
40 ``lakemont``
41 ``yonah``
42 ``prescott``
43 ``nocona``
44 ``core2``
45 ``penryn``
46 ``bonnell`` - ``atom``
47 ``silvermont`` - ``slm``
48 ``goldmont``
49 ``nehalem`` - ``corei7``
50 ``westmere``
51 ``sandybridge`` - ``corei7-avx``
52 ``ivybridge`` - ``core-avx-i``
53 ``haswell`` - ``core-avx2``
54 ``broadwell`` - ``skylake``
55 ``knl``
56 ``knm``
57 ``skylake-avx512`` - ``skx``
58 ``cannonlake``
59 ``icelake``
60 ``k6``
61 ``k6-2``
62 ``k6-3``
63 ``athlon`` - ``athlon-tbird``
64 ``athlon-4`` - ``athlon-xp``
65 - ``athlon-mp``
66 ``k8`` - ``opteron``
67 - ``athlon64``
68 - ``athlon-fx``
69 ``k8-sse3`` - ``opteron-sse3``
70 - ``athlon64-sse3``
71 ``amdfam10h`` - ``barcelona``
72 ``btver1``
73 ``btver2``
74 ``bdver1``
75 ``bdver2``
76 ``bdver3``
77 ``bdver4``
78 ``znver1``
79 ``geode``
80 ``winchip-c6``
81 ``winchip2``
82 ``c3``
83 ``c3-2``
84 ================== ===================
275275 HowToUseAttributes
276276 NVPTXUsage
277277 AMDGPUUsage
278 X86Usage
278279 StackMaps
279280 InAlloca
280281 BigEndianNEON
379380 :doc:`AMDGPUUsage`
380381 This document describes using the AMDGPU backend to compile GPU kernels.
381382
383 :doc:`X86Usage`
384 This document describes using the X86 backend.
385
382386 :doc:`StackMaps`
383387 LLVM support for mapping instruction addresses to the location of
384388 values and allowing code to be patched.
13971397 PI = I->PredTerm.begin(), PE = I->PredTerm.end(); PI != PE; ++PI) {
13981398 Preds.push_back(PI->Predicate);
13991399 }
1400 RecIter PredsEnd = std::unique(Preds.begin(), Preds.end());
1401 Preds.resize(PredsEnd - Preds.begin());
1400 Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());
14021401 SCTrans.PredTerm = Preds;
14031402 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans);
14041403 }