llvm.org GIT mirror llvm / 17a663f
[ARM] Select vmla This patch adds vmla selection. Differential revision: https://reviews.llvm.org/D66297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370704 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Tebbs 1 year, 21 days ago
2 changed file(s) with 95 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
37803780 def MVE_VMLAS_qr_u8 : MVE_VFMAMLA_qr<"vmlas", "u8", 0b1, 0b00, 0b1>;
37813781 def MVE_VMLAS_qr_u16 : MVE_VFMAMLA_qr<"vmlas", "u16", 0b1, 0b01, 0b1>;
37823782 def MVE_VMLAS_qr_u32 : MVE_VFMAMLA_qr<"vmlas", "u32", 0b1, 0b10, 0b1>;
3783
3784 let Predicates = [HasMVEInt] in {
3785 def : Pat<(v4i32 (add (v4i32 MQPR:$src1),
3786 (v4i32 (mul (v4i32 MQPR:$src2),
3787 (v4i32 (ARMvdup (i32 rGPR:$x))))))),
3788 (v4i32 (MVE_VMLA_qr_u32 $src1, $src2, $x))>;
3789 def : Pat<(v8i16 (add (v8i16 MQPR:$src1),
3790 (v8i16 (mul (v8i16 MQPR:$src2),
3791 (v8i16 (ARMvdup (i32 rGPR:$x))))))),
3792 (v8i16 (MVE_VMLA_qr_u16 $src1, $src2, $x))>;
3793 def : Pat<(v16i8 (add (v16i8 MQPR:$src1),
3794 (v16i8 (mul (v16i8 MQPR:$src2),
3795 (v16i8 (ARMvdup (i32 rGPR:$x))))))),
3796 (v16i8 (MVE_VMLA_qr_u8 $src1, $src2, $x))>;
3797 }
37833798
37843799 let Predicates = [HasMVEFloat] in {
37853800 def MVE_VFMA_qr_f16 : MVE_VFMAMLA_qr<"vfma", "f16", 0b1, 0b11, 0b0>;
0 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
1
2 define arm_aapcs_vfpcc <4 x i32> @vmlau32(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
3 ; CHECK-LABEL: vmlau32:
4 ; CHECK: @ %bb.0: @ %entry
5 ; CHECK-NEXT: vmla.u32 q0, q1, r0
6 ; CHECK-NEXT: bx lr
7 entry:
8 %0 = insertelement <4 x i32> undef, i32 %X, i32 0
9 %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
10 %2 = mul nsw <4 x i32> %B, %1
11 %3 = add nsw <4 x i32> %A, %2
12 ret <4 x i32> %3
13 }
14
15 define arm_aapcs_vfpcc <4 x i32> @vmlau32b(<4 x i32> %A, <4 x i32> %B, i32 %X) nounwind {
16 ; CHECK-LABEL: vmlau32b:
17 ; CHECK: @ %bb.0: @ %entry
18 ; CHECK-NEXT: vmla.u32 q0, q1, r0
19 ; CHECK-NEXT: bx lr
20 entry:
21 %0 = insertelement <4 x i32> undef, i32 %X, i32 0
22 %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
23 %2 = mul nsw <4 x i32> %1, %B
24 %3 = add nsw <4 x i32> %2, %A
25 ret <4 x i32> %3
26 }
27
28 define arm_aapcs_vfpcc <8 x i16> @vmlau16(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
29 ; CHECK-LABEL: vmlau16:
30 ; CHECK: @ %bb.0: @ %entry
31 ; CHECK-NEXT: vmla.u16 q0, q1, r0
32 ; CHECK-NEXT: bx lr
33 entry:
34 %0 = insertelement <8 x i16> undef, i16 %X, i32 0
35 %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
36 %2 = mul nsw <8 x i16> %B, %1
37 %3 = add nsw <8 x i16> %A, %2
38 ret <8 x i16> %3
39 }
40
41 define arm_aapcs_vfpcc <8 x i16> @vmlau16b(<8 x i16> %A, <8 x i16> %B, i16 %X) nounwind {
42 ; CHECK-LABEL: vmlau16b:
43 ; CHECK: @ %bb.0: @ %entry
44 ; CHECK-NEXT: vmla.u16 q0, q1, r0
45 ; CHECK-NEXT: bx lr
46 entry:
47 %0 = insertelement <8 x i16> undef, i16 %X, i32 0
48 %1 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
49 %2 = mul nsw <8 x i16> %1, %B
50 %3 = add nsw <8 x i16> %2, %A
51 ret <8 x i16> %3
52 }
53
54 define arm_aapcs_vfpcc <16 x i8> @vmlau8(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
55 ; CHECK-LABEL: vmlau8:
56 ; CHECK: @ %bb.0: @ %entry
57 ; CHECK-NEXT: vmla.u8 q0, q1, r0
58 ; CHECK-NEXT: bx lr
59 entry:
60 %0 = insertelement <16 x i8> undef, i8 %X, i32 0
61 %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
62 %2 = mul nsw <16 x i8> %B, %1
63 %3 = add nsw <16 x i8> %A, %2
64 ret <16 x i8> %3
65 }
66
67 define arm_aapcs_vfpcc <16 x i8> @vmlau8b(<16 x i8> %A, <16 x i8> %B, i8 %X) nounwind {
68 ; CHECK-LABEL: vmlau8b:
69 ; CHECK: @ %bb.0: @ %entry
70 ; CHECK-NEXT: vmla.u8 q0, q1, r0
71 ; CHECK-NEXT: bx lr
72 entry:
73 %0 = insertelement <16 x i8> undef, i8 %X, i32 0
74 %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
75 %2 = mul nsw <16 x i8> %1, %B
76 %3 = add nsw <16 x i8> %2, %A
77 ret <16 x i8> %3
78 }
79