llvm.org GIT mirror llvm / 1763be4
[NFC] fix trivial typos in comments "a a" -> "a" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325752 91177308-0d34-0410-b5e6-96231b3b80d8 Hiroshi Inoue 2 years ago
7 changed file(s) with 7 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
217217 /// - InsnID - Instruction ID to modify
218218 /// - RegNum - The register to add
219219 GIR_AddRegister,
220 /// Add a a temporary register to the specified instruction
220 /// Add a temporary register to the specified instruction
221221 /// - InsnID - Instruction ID to modify
222222 /// - TempRegID - The temporary register ID to add
223223 GIR_AddTempRegister,
217217 unsigned Size = TRI->getRegSizeInBits(*RC);
218218 Result.Named.LGKM = Size > 32 ? 2 : 1;
219219 } else {
220 // s_dcache_inv etc. do not have a a destination register. Assume we
220 // s_dcache_inv etc. do not have a destination register. Assume we
221221 // want a wait on these.
222222 // XXX - What is the right value?
223223 Result.Named.LGKM = 1;
357357 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
358358 const Instruction *I) {
359359 int ISD = TLI->InstructionOpcodeToISD(Opcode);
360 // On NEON a a vector select gets lowered to vbsl.
360 // On NEON a vector select gets lowered to vbsl.
361361 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
362362 // Lowering of some vector selects is currently far from perfect.
363363 static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
19131913 if (OptimizeSpillSlots && !isOptNone(MF))
19141914 optimizeSpillSlots(MF, NewRegs);
19151915
1916 // We need to reserve a a spill slot if scavenging could potentially require
1916 // We need to reserve a spill slot if scavenging could potentially require
19171917 // spilling a scavenged register.
19181918 if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
19191919 MachineFrameInfo &MFI = MF.getFrameInfo();
38843884 // This is accomplished by using a BNEZ with the result of the SLT.
38853885 //
38863886 // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
3887 // and BLE with BGT), so we change the BNEZ into a a BEQZ.
3887 // and BLE with BGT), so we change the BNEZ into a BEQZ.
38883888 // Because only BGE and BLE branch on equality, we can use the
38893889 // AcceptsEquality variable to decide when to emit the BEQZ.
38903890 // Note that the order of the SLT arguments doesn't change between
0 # Test that we can extract all the sled types we know about. This is built with
1 # a a file with functions always instrumented, and using the built-ins and
1 # a file with functions always instrumented, and using the built-ins and
22 # intrinsics supported by clang. Those are built with:
33 #
44 # clang++ -c all-sleds.cc -o all-sleds.o -fpic -std=c++11 -fxray-instrument
243243
244244 } // namespace llvm
245245
246 // Given a a section and an offset into this section the function returns the
246 // Given a section and an offset into this section the function returns the
247247 // symbol used for the relocation at the offset.
248248 std::error_code COFFDumper::resolveSymbol(const coff_section *Section,
249249 uint64_t Offset, SymbolRef &Sym) {