llvm.org GIT mirror llvm / 17427fa
Use llvm_unreachable instead of assert(0) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 6 years ago
9 changed file(s) with 18 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
256256 isSGPR = false;
257257 width = 16;
258258 } else {
259 assert(!"Unknown register class");
259 llvm_unreachable("Unknown register class");
260260 }
261261 hwReg = RI->getEncodingValue(reg) & 0xff;
262262 maxUsed = hwReg + width - 1;
253253 switch (Op.getOpcode()) {
254254 default:
255255 Op.getNode()->dump();
256 assert(0 && "Custom lowering code for this"
257 "instruction is not implemented yet!");
256 llvm_unreachable("Custom lowering code for this"
257 "instruction is not implemented yet!");
258258 break;
259259 // AMDIL DAG lowering
260260 case ISD::SDIV: return LowerSDIV(Op, DAG);
454454 case ISD::SETTRUE2:
455455 case ISD::SETUO:
456456 case ISD::SETO:
457 assert(0 && "Operation should already be optimised !");
457 llvm_unreachable("Operation should already be optimised!");
458458 case ISD::SETULE:
459459 case ISD::SETULT:
460460 case ISD::SETOLE:
478478 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
479479 }
480480 case ISD::SETCC_INVALID:
481 assert(0 && "Invalid setcc condcode !");
481 llvm_unreachable("Invalid setcc condcode!");
482482 }
483483 return Op;
484484 }
109109 int FrameIndex,
110110 const TargetRegisterClass *RC,
111111 const TargetRegisterInfo *TRI) const {
112 assert(!"Not Implemented");
112 llvm_unreachable("Not Implemented");
113113 }
114114
115115 void
118118 unsigned DestReg, int FrameIndex,
119119 const TargetRegisterClass *RC,
120120 const TargetRegisterInfo *TRI) const {
121 assert(!"Not Implemented");
121 llvm_unreachable("Not Implemented");
122122 }
123123
124124 bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
3737 int SPAdj,
3838 unsigned FIOperandNum,
3939 RegScavenger *RS) const {
40 assert(!"Subroutines not supported yet");
40 llvm_unreachable("Subroutines not supported yet");
4141 }
4242
4343 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
976976 HWFalse = DAG.getConstant(0, CompareVT);
977977 }
978978 else {
979 assert(!"Unhandled value type in LowerSELECT_CC");
979 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
980980 }
981981
982982 // Lower this unsupported SELECT_CC into a combination of two supported
10981098 Ptr, DAG.getConstant(2, MVT::i32)));
10991099
11001100 if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
1101 assert(!"Truncated and indexed stores not supported yet");
1101 llvm_unreachable("Truncated and indexed stores not supported yet");
11021102 } else {
11031103 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
11041104 }
6262 DenseMap RegToChan;
6363 std::vector UndefReg;
6464 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
65 assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
65 assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
6666 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
6767 MachineOperand &MO = Instr->getOperand(i);
6868 unsigned Chan = Instr->getOperand(i + 1).getImm();
252252 PhiInserter.AddAvailableValue(Parent, Ret);
253253
254254 } else {
255 assert(0 && "Unhandled loop condition!");
255 llvm_unreachable("Unhandled loop condition!");
256256 }
257257 }
258258
5959 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
6060 bool NewMI=false) const;
6161
62 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
62 virtual unsigned getIEQOpcode() const {
63 llvm_unreachable("Unimplemented");
64 }
65
6366 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
6467 MachineBasicBlock::iterator I,
6568 unsigned DstReg, unsigned SrcReg) const;
282282 }
283283
284284 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
285 MachineBasicBlock *Next = MI.getParent()->getNextNode();
286 MachineBasicBlock *Target = MI.getOperand(0).getMBB();
287 if (Target == Next)
288 MI.eraseFromParent();
289 else
290 assert(0);
285 assert(MI.getOperand(0).getMBB() == MI.getParent()->getNextNode());
286 MI.eraseFromParent();
291287 }
292288
293289 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
294
295290 MachineBasicBlock &MBB = *MI.getParent();
296291 DebugLoc DL = MI.getDebugLoc();
297292