llvm.org GIT mirror llvm / 173e195
[Nios2] Remove Nios2 backend As mentioned here http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html This backend is incomplete and has not been maintained in several months. Differential Revision: https://reviews.llvm.org/D56691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351231 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 10 months ago
61 changed file(s) with 0 addition(s) and 3060 deletion(s). Raw diff Collapse all Expand all
5959 mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
6060 mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
6161 msp430, // MSP430: msp430
62 nios2, // NIOSII: nios2
6362 ppc, // PPC: powerpc
6463 ppc64, // PPC64: powerpc64, ppu
6564 ppc64le, // PPC64LE: powerpc64le
3434 case mips64: return "mips64";
3535 case mips64el: return "mips64el";
3636 case msp430: return "msp430";
37 case nios2: return "nios2";
3837 case ppc64: return "powerpc64";
3938 case ppc64le: return "powerpc64le";
4039 case ppc: return "powerpc";
101100 case mips64:
102101 case mips64el: return "mips";
103102
104 case nios2: return "nios2";
105
106103 case hexagon: return "hexagon";
107104
108105 case amdgcn: return "amdgcn";
273270 .Case("mips64", mips64)
274271 .Case("mips64el", mips64el)
275272 .Case("msp430", msp430)
276 .Case("nios2", nios2)
277273 .Case("ppc64", ppc64)
278274 .Case("ppc32", ppc)
279275 .Case("ppc", ppc)
408404 "mips64r6", "mipsn32r6", Triple::mips64)
409405 .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el",
410406 "mipsn32r6el", Triple::mips64el)
411 .Case("nios2", Triple::nios2)
412407 .Case("r600", Triple::r600)
413408 .Case("amdgcn", Triple::amdgcn)
414409 .Case("riscv32", Triple::riscv32)
666661 case Triple::mips64el:
667662 case Triple::mipsel:
668663 case Triple::msp430:
669 case Triple::nios2:
670664 case Triple::nvptx:
671665 case Triple::nvptx64:
672666 case Triple::ppc64le:
12241218 case llvm::Triple::le32:
12251219 case llvm::Triple::mips:
12261220 case llvm::Triple::mipsel:
1227 case llvm::Triple::nios2:
12281221 case llvm::Triple::nvptx:
12291222 case llvm::Triple::ppc:
12301223 case llvm::Triple::r600:
13091302 case Triple::le32:
13101303 case Triple::mips:
13111304 case Triple::mipsel:
1312 case Triple::nios2:
13131305 case Triple::nvptx:
13141306 case Triple::ppc:
13151307 case Triple::r600:
13581350 case Triple::kalimba:
13591351 case Triple::lanai:
13601352 case Triple::msp430:
1361 case Triple::nios2:
13621353 case Triple::r600:
13631354 case Triple::tce:
13641355 case Triple::tcele:
14301421 case Triple::le32:
14311422 case Triple::le64:
14321423 case Triple::msp430:
1433 case Triple::nios2:
14341424 case Triple::nvptx64:
14351425 case Triple::nvptx:
14361426 case Triple::r600:
15171507 case Triple::mips64el:
15181508 case Triple::mipsel:
15191509 case Triple::msp430:
1520 case Triple::nios2:
15211510 case Triple::nvptx64:
15221511 case Triple::nvptx:
15231512 case Triple::ppc64le:
2929 MSP430
3030 NVPTX
3131 Mips
32 Nios2
3332 PowerPC
3433 RISCV
3534 Sparc
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lib/Target/Nios2/CMakeLists.txt less more
None set(LLVM_TARGET_DEFINITIONS Nios2.td)
1
2 tablegen(LLVM Nios2GenAsmWriter.inc -gen-asm-writer)
3 tablegen(LLVM Nios2GenCallingConv.inc -gen-callingconv)
4 tablegen(LLVM Nios2GenDAGISel.inc -gen-dag-isel)
5 tablegen(LLVM Nios2GenInstrInfo.inc -gen-instr-info)
6 tablegen(LLVM Nios2GenRegisterInfo.inc -gen-register-info)
7 tablegen(LLVM Nios2GenSubtargetInfo.inc -gen-subtarget)
8
9 add_public_tablegen_target(Nios2CommonTableGen)
10
11 #Nios2CodeGen should match with LLVMBuild.txt Nios2CodeGen
12 add_llvm_target(Nios2CodeGen
13 Nios2AsmPrinter.cpp
14 Nios2FrameLowering.cpp
15 Nios2InstrInfo.cpp
16 Nios2ISelDAGToDAG.cpp
17 Nios2ISelLowering.cpp
18 Nios2MachineFunction.cpp
19 Nios2MCInstLower.cpp
20 Nios2RegisterInfo.cpp
21 Nios2Subtarget.cpp
22 Nios2TargetMachine.cpp
23 Nios2TargetObjectFile.cpp
24 )
25
26 #Should match with "subdirectories = InstPrinter MCTargetDesc TargetInfo" in LLVMBuild.txt
27 add_subdirectory(InstPrinter)
28 add_subdirectory(MCTargetDesc)
29 add_subdirectory(TargetInfo)
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lib/Target/Nios2/InstPrinter/CMakeLists.txt less more
None add_llvm_library(LLVMNios2AsmPrinter Nios2InstPrinter.cpp)
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-23
lib/Target/Nios2/InstPrinter/LLVMBuild.txt less more
None ;===- ./lib/Target/Nios2/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = Nios2AsmPrinter
20 parent = Nios2
21 required_libraries = MC Support
22 add_to_library_groups = Nios2
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lib/Target/Nios2/InstPrinter/Nios2InstPrinter.cpp less more
None //===-- Nios2InstPrinter.cpp - Convert Nios2 MCInst to assembly syntax-----===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an Nios2 MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2InstPrinter.h"
14
15 #include "Nios2InstrInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/Support/raw_ostream.h"
20 using namespace llvm;
21
22 #define DEBUG_TYPE "asm-printer"
23
24 #define PRINT_ALIAS_INSTR
25 #include "Nios2GenAsmWriter.inc"
26
27 void Nios2InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
28 OS << getRegisterName(RegNo);
29 }
30
31 void Nios2InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
32 StringRef Annot, const MCSubtargetInfo &STI) {
33 // Try to print any aliases first.
34 if (!printAliasInstr(MI, STI, O))
35 printInstruction(MI, STI, O);
36 printAnnotation(O, Annot);
37 }
38
39 void Nios2InstPrinter::printOperand(const MCInst *MI, int OpNo,
40 const MCSubtargetInfo &STI,
41 raw_ostream &O) {
42 const MCOperand &Op = MI->getOperand(OpNo);
43 if (Op.isReg()) {
44 printRegName(O, Op.getReg());
45 return;
46 }
47
48 if (Op.isImm()) {
49 O << Op.getImm();
50 return;
51 }
52
53 assert(Op.isExpr() && "unknown operand kind in printOperand");
54 Op.getExpr()->print(O, &MAI, true);
55 }
56
57 void Nios2InstPrinter::printMemOperand(const MCInst *MI, int opNum,
58 const MCSubtargetInfo &STI,
59 raw_ostream &O, const char *Modifier) {
60 // Load/Store memory operands -- imm($reg)
61 printOperand(MI, opNum + 1, STI, O);
62 O << "(";
63 printOperand(MI, opNum, STI, O);
64 O << ")";
65 }
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lib/Target/Nios2/InstPrinter/Nios2InstPrinter.h less more
None //= Nios2InstPrinter.h - Convert Nios2 MCInst to assembly syntax -*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints a Nios2 MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_INSTPRINTER_NIOS2INSTPRINTER_H
14 #define LLVM_LIB_TARGET_NIOS2_INSTPRINTER_NIOS2INSTPRINTER_H
15
16 #include "llvm/MC/MCInstPrinter.h"
17
18 namespace llvm {
19
20 class Nios2InstPrinter : public MCInstPrinter {
21 public:
22 Nios2InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
23 const MCRegisterInfo &MRI)
24 : MCInstPrinter(MAI, MII, MRI) {}
25
26 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
27 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
28 const MCSubtargetInfo &STI) override;
29
30 // Autogenerated by tblgen.
31 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
32 raw_ostream &O);
33 static const char *getRegisterName(unsigned RegNo);
34
35 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
36 raw_ostream &O);
37
38 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
39 unsigned PrintMethodIdx,
40 const MCSubtargetInfo &STI, raw_ostream &O);
41 void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
42 raw_ostream &OS);
43 void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
44 raw_ostream &OS, const char *Modifier = nullptr);
45 };
46 } // end namespace llvm
47
48 #endif
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lib/Target/Nios2/LLVMBuild.txt less more
None ;===- ./lib/Target/Nios2/LLVMBuild.txt -------------------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 #Following comments extracted from http: // llvm.org/docs/LLVMBuild.html
18
19 [common]
20 subdirectories =
21 InstPrinter
22 MCTargetDesc
23 TargetInfo
24
25 [component_0]
26 #TargetGroup components are an extension of LibraryGroups, specifically for
27 #defining LLVM targets(which are handled specially in a few places).
28 type = TargetGroup
29 #The name of the component should always be the name of the target.(should
30 #match "def Nios2 : Target" in Nios2.td)
31 name = Nios2
32 #Nios2 component is located in directory Target /
33 parent = Target
34 #Whether this target defines an assembly parser, assembly printer, disassembler
35 #, and supports JIT compilation.They are optional.
36 has_asmprinter = 1
37
38 [component_1]
39 #component_1 is a Library type and name is Nios2CodeGen.After build it will
40 #in lib / libLLVMNios2CodeGen.a of your build command directory.
41 type = Library
42 name = Nios2CodeGen
43 #Nios2CodeGen component(Library) is located in directory Nios2 /
44 parent = Nios2
45 #If given, a list of the names of Library or LibraryGroup components which
46 #must also be linked in whenever this library is used.That is, the link time
47 #dependencies for this component.When tools are built, the build system will
48 #include the transitive closure of all required_libraries for the components
49 #the tool needs.
50 required_libraries = AsmPrinter
51 CodeGen
52 Core
53 GlobalISel
54 MC
55 Nios2AsmPrinter
56 Nios2Desc
57 Nios2Info
58 SelectionDAG
59 Support
60 Target
61 #end of required_libraries
62
63 #All LLVMBuild.txt in Target / Nios2 and subdirectory use 'add_to_library_groups
64 #= Nios2'
65 add_to_library_groups = Nios2
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lib/Target/Nios2/MCTargetDesc/CMakeLists.txt less more
None #MCTargetDesc / CMakeLists.txt
1 add_llvm_library(LLVMNios2Desc
2 Nios2AsmBackend.cpp
3 Nios2ELFObjectWriter.cpp
4 Nios2MCAsmInfo.cpp
5 Nios2MCExpr.cpp
6 Nios2MCTargetDesc.cpp
7 Nios2TargetStreamer.cpp)
8
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lib/Target/Nios2/MCTargetDesc/LLVMBuild.txt less more
None ;===- ./lib/Target/Nios2/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = Nios2Desc
20 parent = Nios2
21 required_libraries = MC
22 Nios2AsmPrinter
23 Nios2Info
24 Support
25 add_to_library_groups = Nios2
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lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.cpp less more
None //===-- Nios2AsmBackend.cpp - Nios2 Asm Backend --------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Nios2AsmBackend class.
10 //
11 //===----------------------------------------------------------------------===//
12 //
13
14 #include "MCTargetDesc/Nios2AsmBackend.h"
15 #include "MCTargetDesc/Nios2FixupKinds.h"
16 #include "MCTargetDesc/Nios2MCTargetDesc.h"
17 #include "llvm/MC/MCAssembler.h"
18 #include "llvm/MC/MCELFObjectWriter.h"
19 #include "llvm/MC/MCFixupKindInfo.h"
20 #include "llvm/MC/MCObjectWriter.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22
23 using namespace llvm;
24
25 // Prepare value for the target space for it
26 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value) {
27
28 unsigned Kind = Fixup.getKind();
29
30 // Add/subtract and shift
31 switch (Kind) {
32 default:
33 return 0;
34 case Nios2::fixup_Nios2_LO16:
35 break;
36 case Nios2::fixup_Nios2_HI16:
37 // Get the higher 16-bits. Also add 1 if bit 15 is 1.
38 Value = ((Value + 0x8000) >> 16) & 0xffff;
39 break;
40 }
41
42 return Value;
43 }
44
45 // Calculate index for Nios2 specific little endian byte order
46 static unsigned calculateLEIndex(unsigned i) {
47 assert(i <= 3 && "Index out of range!");
48
49 return (1 - i / 2) * 2 + i % 2;
50 }
51
52 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
53 /// data fragment, at the offset specified by the fixup and following the
54 /// fixup kind as appropriate.
55 void Nios2AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
56 const MCValue &Target,
57 MutableArrayRef Data, uint64_t Value,
58 bool IsResolved) const {
59 MCFixupKind Kind = Fixup.getKind();
60 Value = adjustFixupValue(Fixup, Value);
61
62 if (!Value)
63 return; // Doesn't change encoding.
64
65 // Where do we start in the object
66 unsigned Offset = Fixup.getOffset();
67 // Number of bytes we need to fixup
68 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
69 // Grab current value, if any, from bits.
70 uint64_t CurVal = 0;
71
72 for (unsigned i = 0; i != NumBytes; ++i) {
73 unsigned Idx = calculateLEIndex(i);
74 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i * 8);
75 }
76
77 uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
78 CurVal |= Value & Mask;
79
80 // Write out the fixed up bytes back to the code/data bits.
81 for (unsigned i = 0; i != NumBytes; ++i) {
82 unsigned Idx = calculateLEIndex(i);
83 Data[Offset + Idx] = (uint8_t)((CurVal >> (i * 8)) & 0xff);
84 }
85 }
86
87 Optional Nios2AsmBackend::getFixupKind(StringRef Name) const {
88 return StringSwitch>(Name)
89 .Case("R_NIOS2_NONE", (MCFixupKind)Nios2::fixup_Nios2_32)
90 .Case("R_NIOS2_32", FK_Data_4)
91 .Default(MCAsmBackend::getFixupKind(Name));
92 }
93
94 //@getFixupKindInfo {
95 const MCFixupKindInfo &
96 Nios2AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
97 const static MCFixupKindInfo Infos[Nios2::NumTargetFixupKinds] = {
98 // This table *must* be in same the order of fixup_* kinds in
99 // Nios2FixupKinds.h.
100 //
101 // name offset bits flags
102 {"fixup_Nios2_32", 0, 32, 0},
103 {"fixup_Nios2_HI16", 0, 16, 0},
104 {"fixup_Nios2_LO16", 0, 16, 0}};
105
106 if (Kind < FirstTargetFixupKind)
107 return MCAsmBackend::getFixupKindInfo(Kind);
108
109 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
110 "Invalid kind!");
111 return Infos[Kind - FirstTargetFixupKind];
112 }
113
114 std::unique_ptr
115 Nios2AsmBackend::createObjectTargetWriter() const {
116 return createNios2ELFObjectWriter(MCELFObjectTargetWriter::getOSABI(OSType));
117 }
118
119 bool Nios2AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
120 return true;
121 }
122
123 // MCAsmBackend
124 MCAsmBackend *llvm::createNios2AsmBackend(const Target &T,
125 const MCSubtargetInfo &STI,
126 const MCRegisterInfo &MRI,
127 const MCTargetOptions &Options) {
128 return new Nios2AsmBackend(T, STI.getTargetTriple().getOS());
129 }
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lib/Target/Nios2/MCTargetDesc/Nios2AsmBackend.h less more
None //===-- Nios2AsmBackend.h - Nios2 Asm Backend ----------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the Nios2AsmBackend class.
10 //
11 //===----------------------------------------------------------------------===//
12 //
13
14 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2ASMBACKEND_H
15 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2ASMBACKEND_H
16
17 #include "MCTargetDesc/Nios2FixupKinds.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCAsmBackend.h"
20
21 namespace llvm {
22
23 class MCAssembler;
24 struct MCFixupKindInfo;
25 class Target;
26 class MCObjectWriter;
27
28 class Nios2AsmBackend : public MCAsmBackend {
29 Triple::OSType OSType;
30
31 public:
32 Nios2AsmBackend(const Target &T, Triple::OSType OSType)
33 : MCAsmBackend(support::little), OSType(OSType) {}
34
35 std::unique_ptr
36 createObjectTargetWriter() const override;
37
38 bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
39
40 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
41 const MCValue &Target, MutableArrayRef Data,
42 uint64_t Value, bool IsResolved) const override;
43
44 Optional getFixupKind(StringRef Name) const override;
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
46
47 unsigned getNumFixupKinds() const override {
48 return Nios2::NumTargetFixupKinds;
49 }
50
51 /// MayNeedRelaxation - Check whether the given instruction may need
52 /// relaxation.
53 ///
54 /// \param Inst - The instruction to test.
55 bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
56
57 /// fixupNeedsRelaxation - Target specific predicate for whether a given
58 /// fixup requires the associated instruction to be relaxed.
59 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
60 const MCRelaxableFragment *DF,
61 const MCAsmLayout &Layout) const override {
62 // FIXME.
63 llvm_unreachable("RelaxInstruction() unimplemented");
64 return false;
65 }
66
67 /// RelaxInstruction - Relax the instruction in the given fragment
68 /// to the next wider instruction.
69 ///
70 /// \param Inst - The instruction to relax, which may be the same
71 /// as the output.
72 /// \param [out] Res On return, the relaxed instruction.
73 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
74 MCInst &Res) const override {}
75
76 }; // class Nios2AsmBackend
77
78 } // namespace llvm
79
80 #endif
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lib/Target/Nios2/MCTargetDesc/Nios2BaseInfo.h less more
None //===-- Nios2BaseInfo.h - Top level definitions for NIOS2 MC ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the Nios2 target useful for the compiler back-end and the MC libraries.
11 //
12 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2BASEINFO_H
14 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2BASEINFO_H
15
16 namespace llvm {
17
18 /// Nios2FG - This namespace holds all of the target specific flags that
19 /// instruction info tracks.
20 namespace Nios2FG {
21 /// Target Operand Flag enum.
22 enum TOF {
23 //===------------------------------------------------------------------===//
24 // Nios2 Specific MachineOperand flags.
25
26 MO_NO_FLAG,
27
28 /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
29 /// address.
30 MO_ABS_HI,
31 MO_ABS_LO,
32
33 };
34 } // namespace Nios2FG
35 } // namespace llvm
36
37 #endif
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lib/Target/Nios2/MCTargetDesc/Nios2ELFObjectWriter.cpp less more
None //===-- Nios2ELFObjectWriter.cpp - Nios2 ELF Writer -----------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/Nios2FixupKinds.h"
10 #include "MCTargetDesc/Nios2MCExpr.h"
11 #include "MCTargetDesc/Nios2MCTargetDesc.h"
12 #include "llvm/MC/MCELFObjectWriter.h"
13 #include "llvm/MC/MCObjectWriter.h"
14
15 using namespace llvm;
16
17 namespace {
18 class Nios2ELFObjectWriter : public MCELFObjectTargetWriter {
19 public:
20 Nios2ELFObjectWriter(uint8_t OSABI)
21 : MCELFObjectTargetWriter(false, OSABI, ELF::EM_ALTERA_NIOS2, false) {}
22
23 ~Nios2ELFObjectWriter() override;
24
25 unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
26 const MCFixup &Fixup, bool IsPCRel) const override;
27 };
28 } // namespace
29
30 Nios2ELFObjectWriter::~Nios2ELFObjectWriter() {}
31
32 unsigned Nios2ELFObjectWriter::getRelocType(MCContext &Ctx,
33 const MCValue &Target,
34 const MCFixup &Fixup,
35 bool IsPCRel) const {
36 return 0;
37 }
38
39 std::unique_ptr
40 llvm::createNios2ELFObjectWriter(uint8_t OSABI) {
41 return llvm::make_unique(OSABI);
42 }
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lib/Target/Nios2/MCTargetDesc/Nios2FixupKinds.h less more
None //===-- Nios2FixupKinds.h - Nios2 Specific Fixup Entries --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2FIXUPKINDS_H
10 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2FIXUPKINDS_H
11
12 #include "llvm/MC/MCFixup.h"
13
14 namespace llvm {
15 namespace Nios2 {
16 // Although most of the current fixup types reflect a unique relocation
17 // one can have multiple fixup types for a given relocation and thus need
18 // to be uniquely named.
19 //
20 // This table *must* be in the save order of
21 // MCFixupKindInfo Infos[Nios2::NumTargetFixupKinds]
22 // in Nios2AsmBackend.cpp.
23 enum Fixups {
24 // Pure upper 32 bit fixup resulting in - R_NIOS2_32.
25 fixup_Nios2_32 = FirstTargetFixupKind,
26
27 // Pure upper 16 bit fixup resulting in - R_NIOS2_HI16.
28 fixup_Nios2_HI16,
29
30 // Pure lower 16 bit fixup resulting in - R_NIOS2_LO16.
31 fixup_Nios2_LO16,
32
33 // Marker
34 LastTargetFixupKind,
35 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
36 };
37 } // namespace Nios2
38 } // namespace llvm
39
40 #endif // LLVM_NIOS2_NIOS2FIXUPKINDS_H
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lib/Target/Nios2/MCTargetDesc/Nios2MCAsmInfo.cpp less more
None //===-- Nios2MCAsmInfo.cpp - Nios2 Asm Properties -------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declarations of the Nios2MCAsmInfo properties.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2MCAsmInfo.h"
14
15 #include "llvm/ADT/Triple.h"
16
17 using namespace llvm;
18
19 void Nios2MCAsmInfo::anchor() {}
20
21 Nios2MCAsmInfo::Nios2MCAsmInfo(const Triple &TheTriple) {
22 if ((TheTriple.getArch() == Triple::nios2))
23 IsLittleEndian = true; // the default of IsLittleEndian is true
24
25 AlignmentIsInBytes = false;
26 Data16bitsDirective = "\t.2byte\t";
27 Data32bitsDirective = "\t.4byte\t";
28 Data64bitsDirective = "\t.8byte\t";
29 PrivateLabelPrefix = ".LC";
30 CommentString = "#";
31 ZeroDirective = "\t.space\t";
32 GPRel32Directive = "\t.gpword\t";
33 GPRel64Directive = "\t.gpdword\t";
34 WeakRefDirective = "\t.weak\t";
35 GlobalDirective = "\t.global\t";
36 AscizDirective = "\t.string\t";
37 UseAssignmentForEHBegin = true;
38
39 SupportsDebugInformation = true;
40 ExceptionsType = ExceptionHandling::DwarfCFI;
41 DwarfRegNumForCFI = true;
42 UsesELFSectionDirectiveForBSS = true;
43 }
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lib/Target/Nios2/MCTargetDesc/Nios2MCAsmInfo.h less more
None //===-- Nios2MCAsmInfo.h - Nios2 Asm Info ----------------------*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the Nios2MCAsmInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCASMINFO_H
14 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCASMINFO_H
15
16 #include "llvm/MC/MCAsmInfoELF.h"
17
18 namespace llvm {
19 class Triple;
20
21 class Nios2MCAsmInfo : public MCAsmInfoELF {
22 void anchor() override;
23
24 public:
25 explicit Nios2MCAsmInfo(const Triple &TheTriple);
26 };
27
28 } // namespace llvm
29
30 #endif
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lib/Target/Nios2/MCTargetDesc/Nios2MCExpr.cpp less more
None //===-- Nios2MCExpr.cpp - Nios2 specific MC expression classes ------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Nios2.h"
10
11 #include "Nios2MCExpr.h"
12 #include "llvm/MC/MCAsmInfo.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCObjectStreamer.h"
16 #include "llvm/MC/MCSymbolELF.h"
17
18 using namespace llvm;
19
20 #define DEBUG_TYPE "nios2mcexpr"
21
22 const Nios2MCExpr *Nios2MCExpr::create(Nios2MCExpr::Nios2ExprKind Kind,
23 const MCExpr *Expr, MCContext &Ctx) {
24 return new (Ctx) Nios2MCExpr(Kind, Expr);
25 }
26
27 const Nios2MCExpr *Nios2MCExpr::create(const MCSymbol *Symbol,
28 Nios2MCExpr::Nios2ExprKind Kind,
29 MCContext &Ctx) {
30 const MCSymbolRefExpr *MCSym =
31 MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
32 return new (Ctx) Nios2MCExpr(Kind, MCSym);
33 }
34
35 void Nios2MCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
36
37 switch (Kind) {
38 case CEK_None:
39 case CEK_Special:
40 llvm_unreachable("CEK_None and CEK_Special are invalid");
41 break;
42 case CEK_ABS_HI:
43 OS << "%hiadj";
44 break;
45 case CEK_ABS_LO:
46 OS << "%lo";
47 break;
48 }
49
50 OS << '(';
51 Expr->print(OS, MAI, true);
52 OS << ')';
53 }
54
55 bool Nios2MCExpr::evaluateAsRelocatableImpl(MCValue &Res,
56 const MCAsmLayout *Layout,
57 const MCFixup *Fixup) const {
58 return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);
59 }
60
61 void Nios2MCExpr::visitUsedExpr(MCStreamer &Streamer) const {
62 Streamer.visitUsedExpr(*getSubExpr());
63 }
64
65 void Nios2MCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
66 switch (getKind()) {
67 case CEK_None:
68 case CEK_Special:
69 llvm_unreachable("CEK_None and CEK_Special are invalid");
70 break;
71 case CEK_ABS_HI:
72 case CEK_ABS_LO:
73 break;
74 }
75 }
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lib/Target/Nios2/MCTargetDesc/Nios2MCExpr.h less more
None //===-- Nios2MCExpr.h - Nios2 specific MC expression classes ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCEXPR_H
10 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCEXPR_H
11
12 #include "llvm/MC/MCAsmLayout.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCValue.h"
15
16 namespace llvm {
17
18 class Nios2MCExpr : public MCTargetExpr {
19 public:
20 enum Nios2ExprKind {
21 CEK_None,
22 CEK_ABS_HI,
23 CEK_ABS_LO,
24 CEK_Special,
25 };
26
27 private:
28 const Nios2ExprKind Kind;
29 const MCExpr *Expr;
30
31 explicit Nios2MCExpr(Nios2ExprKind Kind, const MCExpr *Expr)
32 : Kind(Kind), Expr(Expr) {}
33
34 public:
35 static const Nios2MCExpr *create(Nios2ExprKind Kind, const MCExpr *Expr,
36 MCContext &Ctx);
37 static const Nios2MCExpr *create(const MCSymbol *Symbol,
38 Nios2MCExpr::Nios2ExprKind Kind,
39 MCContext &Ctx);
40
41 /// Get the kind of this expression.
42 Nios2ExprKind getKind() const { return Kind; }
43
44 /// Get the child of this expression.
45 const MCExpr *getSubExpr() const { return Expr; }
46
47 void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
48 bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
49 const MCFixup *Fixup) const override;
50 void visitUsedExpr(MCStreamer &Streamer) const override;
51 MCFragment *findAssociatedFragment() const override {
52 return getSubExpr()->findAssociatedFragment();
53 }
54
55 void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
56 };
57 } // end namespace llvm
58
59 #endif
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lib/Target/Nios2/MCTargetDesc/Nios2MCTargetDesc.cpp less more
None //===-- Nios2MCTargetDesc.cpp - Nios2 Target Descriptions -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Nios2 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2MCTargetDesc.h"
14 #include "InstPrinter/Nios2InstPrinter.h"
15 #include "Nios2MCAsmInfo.h"
16 #include "Nios2TargetStreamer.h"
17 #include "llvm/MC/MCInstrInfo.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/TargetRegistry.h"
21
22 using namespace llvm;
23
24 #define GET_INSTRINFO_MC_DESC
25 #include "Nios2GenInstrInfo.inc"
26
27 #define GET_SUBTARGETINFO_MC_DESC
28 #include "Nios2GenSubtargetInfo.inc"
29
30 #define GET_REGINFO_MC_DESC
31 #include "Nios2GenRegisterInfo.inc"
32
33 static MCInstrInfo *createNios2MCInstrInfo() {
34 MCInstrInfo *X = new MCInstrInfo();
35 InitNios2MCInstrInfo(X); // defined in Nios2GenInstrInfo.inc
36 return X;
37 }
38
39 static MCRegisterInfo *createNios2MCRegisterInfo(const Triple &TT) {
40 MCRegisterInfo *X = new MCRegisterInfo();
41 InitNios2MCRegisterInfo(X, Nios2::R15); // defined in Nios2GenRegisterInfo.inc
42 return X;
43 }
44
45 static MCSubtargetInfo *
46 createNios2MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
47 if (CPU.empty() || CPU == "generic")
48 CPU = "nios2r1";
49 return createNios2MCSubtargetInfoImpl(TT, CPU, FS);
50 // createNios2MCSubtargetInfoImpl defined in Nios2GenSubtargetInfo.inc
51 }
52
53 static MCAsmInfo *createNios2MCAsmInfo(const MCRegisterInfo &MRI,
54 const Triple &TT) {
55 MCAsmInfo *MAI = new Nios2MCAsmInfo(TT);
56
57 unsigned SP = MRI.getDwarfRegNum(Nios2::SP, true);
58 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
59 MAI->addInitialFrameState(Inst);
60
61 return MAI;
62 }
63
64 static MCInstPrinter *createNios2MCInstPrinter(const Triple &T,
65 unsigned SyntaxVariant,
66 const MCAsmInfo &MAI,
67 const MCInstrInfo &MII,
68 const MCRegisterInfo &MRI) {
69 return new Nios2InstPrinter(MAI, MII, MRI);
70 }
71
72 static MCTargetStreamer *createNios2AsmTargetStreamer(MCStreamer &S,
73 formatted_raw_ostream &OS,
74 MCInstPrinter *InstPrint,
75 bool isVerboseAsm) {
76 return new Nios2TargetAsmStreamer(S, OS);
77 }
78
79 extern "C" void LLVMInitializeNios2TargetMC() {
80 Target *T = &getTheNios2Target();
81
82 // Register the MC asm info.
83 RegisterMCAsmInfoFn X(*T, createNios2MCAsmInfo);
84
85 // Register the MC instruction info.
86 TargetRegistry::RegisterMCInstrInfo(*T, createNios2MCInstrInfo);
87
88 // Register the MC register info.
89 TargetRegistry::RegisterMCRegInfo(*T, createNios2MCRegisterInfo);
90
91 // Register the asm target streamer.
92 TargetRegistry::RegisterAsmTargetStreamer(*T, createNios2AsmTargetStreamer);
93
94 // Register the MC subtarget info.
95 TargetRegistry::RegisterMCSubtargetInfo(*T, createNios2MCSubtargetInfo);
96 // Register the MCInstPrinter.
97 TargetRegistry::RegisterMCInstPrinter(*T, createNios2MCInstPrinter);
98
99 // Register the asm backend.
100 TargetRegistry::RegisterMCAsmBackend(*T, createNios2AsmBackend);
101 }
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lib/Target/Nios2/MCTargetDesc/Nios2MCTargetDesc.h less more
None //===-- Nios2MCTargetDesc.h - Nios2 Target Descriptions ---------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Nios2 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_NIOS2_MCTARGETDESC_NIOS2MCTARGETDESC_H
15
16 #include
17
18 namespace llvm {
19 class MCAsmBackend;
20 class MCObjectTargetWriter;
21 class MCRegisterInfo;
22 class MCSubtargetInfo;
23 class MCTargetOptions;
24 class Target;
25 class Triple;
26 class StringRef;
27 class raw_pwrite_stream;
28
29 Target &getTheNios2Target();
30
31 MCAsmBackend *createNios2AsmBackend(const Target &T, const MCSubtargetInfo &STI,
32 const MCRegisterInfo &MRI,
33 const MCTargetOptions &Options);
34
35 std::unique_ptr createNios2ELFObjectWriter(uint8_t OSABI);
36
37 } // namespace llvm
38
39 // Defines symbolic names for Nios2 registers. This defines a mapping from
40 // register name to register number.
41 #define GET_REGINFO_ENUM
42 #include "Nios2GenRegisterInfo.inc"
43
44 // Defines symbolic names for the Nios2 instructions.
45 #define GET_INSTRINFO_ENUM
46 #include "Nios2GenInstrInfo.inc"
47
48 #define GET_SUBTARGETINFO_ENUM
49 #include "Nios2GenSubtargetInfo.inc"
50
51 #endif
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lib/Target/Nios2/MCTargetDesc/Nios2TargetStreamer.cpp less more
None //===-- Nios2TargetStreamer.cpp - Nios2 Target Streamer Methods -----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Nios2 specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2TargetStreamer.h"
14
15 using namespace llvm;
16
17 Nios2TargetStreamer::Nios2TargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
18
19 Nios2TargetAsmStreamer::Nios2TargetAsmStreamer(MCStreamer &S,
20 formatted_raw_ostream &OS)
21 : Nios2TargetStreamer(S) {}
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lib/Target/Nios2/Nios2.h less more
None //===-- Nios2.h - Top-level interface for Nios2 representation --*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in
10 // the LLVM Nios2 back-end.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2_H
15 #define LLVM_LIB_TARGET_NIOS2_NIOS2_H
16
17 #include "MCTargetDesc/Nios2MCTargetDesc.h"
18 #include "llvm/Target/TargetMachine.h"
19
20 namespace llvm {
21 class FunctionPass;
22 class formatted_raw_ostream;
23 class Nios2TargetMachine;
24 class AsmPrinter;
25 class MachineInstr;
26 class MCInst;
27
28 FunctionPass *createNios2ISelDag(Nios2TargetMachine &TM,
29 CodeGenOpt::Level OptLevel);
30 void LowerNios2MachineInstToMCInst(const MachineInstr *MI, MCInst &OutMI,
31 AsmPrinter &AP);
32 } // namespace llvm
33
34 #endif
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lib/Target/Nios2/Nios2.td less more
None //===-- Nios2.td - Describe the Nios2 Target Machine -------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
10 // Calling Conv, Instruction Descriptions
11 //===----------------------------------------------------------------------===//
12
13 include "llvm/Target/Target.td"
14 include "Nios2RegisterInfo.td"
15 include "Nios2Schedule.td"
16 include "Nios2InstrInfo.td"
17 include "Nios2CallingConv.td"
18
19 //===----------------------------------------------------------------------===//
20 // Nios2 Subtarget features
21 //===----------------------------------------------------------------------===//
22 def FeatureNios2r1 : SubtargetFeature<"nios2r1", "Nios2ArchVersion",
23 "Nios2r1", "Nios2 R1 ISA Support">;
24 def FeatureNios2r2 : SubtargetFeature<"nios2r2", "Nios2ArchVersion",
25 "Nios2r2", "Nios2 R2 ISA Support">;
26
27 //===----------------------------------------------------------------------===//
28 // Nios2 processors supported.
29 //===----------------------------------------------------------------------===//
30
31 class Proc Features>
32 : Processor;
33
34 def : Proc<"nios2r1", [FeatureNios2r1]>;
35 def : Proc<"nios2r2", [FeatureNios2r2]>;
36
37 def Nios2InstrInfo : InstrInfo;
38
39 def Nios2AsmParser : AsmParser {
40 let ShouldEmitMatchRegisterName = 0;
41 }
42
43 //===----------------------------------------------------------------------===//
44 // Declare the target which we are implementing
45 //===----------------------------------------------------------------------===//
46
47 def Nios2AsmWriter : AsmWriter {
48 string AsmWriterClassName = "InstPrinter";
49 int PassSubtarget = 1;
50 int Variant = 0;
51 }
52
53 def Nios2 : Target {
54 // def Nios2InstrInfo : InstrInfo as before.
55 let InstructionSet = Nios2InstrInfo;
56 let AssemblyParsers = [Nios2AsmParser];
57 let AssemblyWriters = [Nios2AsmWriter];
58 }
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lib/Target/Nios2/Nios2AsmPrinter.cpp less more
None //===-- Nios2AsmPrinter.cpp - Nios2 LLVM Assembly Printer -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format NIOS2 assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "InstPrinter/Nios2InstPrinter.h"
15 #include "MCTargetDesc/Nios2BaseInfo.h"
16 #include "Nios2.h"
17 #include "Nios2TargetMachine.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/Support/TargetRegistry.h"
21
22 using namespace llvm;
23
24 #define DEBUG_TYPE "nios2-asm-printer"
25
26 namespace {
27
28 class Nios2AsmPrinter : public AsmPrinter {
29
30 public:
31 explicit Nios2AsmPrinter(TargetMachine &TM,
32 std::unique_ptr Streamer)
33 : AsmPrinter(TM, std::move(Streamer)) {}
34
35 StringRef getPassName() const override { return "Nios2 Assembly Printer"; }
36
37 //- EmitInstruction() must exists or will have run time error.
38 void EmitInstruction(const MachineInstr *MI) override;
39 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
40 unsigned AsmVariant, const char *ExtraCode,
41 raw_ostream &O) override;
42 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
43 unsigned AsmVariant, const char *ExtraCode,
44 raw_ostream &O) override;
45 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
46 void EmitFunctionEntryLabel() override;
47 };
48 } // namespace
49
50 //- EmitInstruction() must exists or will have run time error.
51 void Nios2AsmPrinter::EmitInstruction(const MachineInstr *MI) {
52
53 // Print out both ordinary instruction and boudle instruction
54 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
55 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
56
57 do {
58
59 if (I->isPseudo()) {
60 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
61 }
62
63 MCInst TmpInst0;
64 LowerNios2MachineInstToMCInst(&*I, TmpInst0, *this);
65 EmitToStreamer(*OutStreamer, TmpInst0);
66 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
67 }
68
69 // .type main,@function
70 //-> .ent main # @main
71 // main:
72 void Nios2AsmPrinter::EmitFunctionEntryLabel() {
73 OutStreamer->EmitLabel(CurrentFnSym);
74 }
75
76 // Print out an operand for an inline asm expression.
77 bool Nios2AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
78 unsigned AsmVariant,
79 const char *ExtraCode, raw_ostream &O) {
80 printOperand(MI, OpNum, O);
81 return false;
82 }
83
84 bool Nios2AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
85 unsigned OpNum, unsigned AsmVariant,
86 const char *ExtraCode,
87 raw_ostream &O) {
88 if (ExtraCode && ExtraCode[0])
89 return true; // Unknown modifier
90
91 const MachineOperand &MO = MI->getOperand(OpNum);
92 assert(MO.isReg() && "unexpected inline asm memory operand");
93 O << "($" << Nios2InstPrinter::getRegisterName(MO.getReg()) << ")";
94
95 return false;
96 }
97
98 void Nios2AsmPrinter::printOperand(const MachineInstr *MI, int opNum,
99 raw_ostream &O) {
100 const MachineOperand &MO = MI->getOperand(opNum);
101 bool closeP = false;
102
103 if (MO.getTargetFlags())
104 closeP = true;
105
106 switch (MO.getTargetFlags()) {
107 case Nios2FG::MO_ABS_HI:
108 O << "%hiadj(";
109 break;
110 case Nios2FG::MO_ABS_LO:
111 O << "%lo(";
112 break;
113 }
114
115 switch (MO.getType()) {
116 case MachineOperand::MO_Register:
117 O << '$'
118 << StringRef(Nios2InstPrinter::getRegisterName(MO.getReg())).lower();
119 break;
120
121 case MachineOperand::MO_Immediate:
122 O << MO.getImm();
123 break;
124
125 case MachineOperand::MO_MachineBasicBlock:
126 MO.getMBB()->getSymbol()->print(O, MAI);
127 return;
128
129 case MachineOperand::MO_GlobalAddress:
130 getSymbol(MO.getGlobal())->print(O, MAI);
131 break;
132
133 case MachineOperand::MO_BlockAddress:
134 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
135 break;
136
137 case MachineOperand::MO_ExternalSymbol:
138 O << MO.getSymbolName();
139 break;
140
141 default:
142 llvm_unreachable("");
143 }
144
145 if (closeP)
146 O << ")";
147 }
148
149 // Force static initialization.
150 extern "C" void LLVMInitializeNios2AsmPrinter() {
151 RegisterAsmPrinter X(getTheNios2Target());
152 }
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lib/Target/Nios2/Nios2CallingConv.td less more
None //===- Nios2CallingConv.td - Calling Conventions for Nios2 -*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 // This describes the calling conventions for Nios2 architecture.
9 //===----------------------------------------------------------------------===//
10
11 /// CCIfSubtarget - Match if the current subtarget has a feature F.
12 class CCIfSubtarget:
13 CCIf().", F), A>;
14
15 def CC_Nios2 : CallingConv<[
16 // i32 f32 arguments get passed in integer registers if there is space.
17 CCIfType<[i32, f32], CCAssignToReg<[R4, R5, R6, R7]>>,
18
19 // Alternatively, they are assigned to the stack in 4-byte aligned units.
20 CCAssignToStack<4, 4>
21 ]>;
22
23 def RetCC_Nios2EABI : CallingConv<[
24 // i32 are returned in registers R2, R3
25 CCIfType<[i32], CCAssignToReg<[R2, R3]>>,
26 // In case of floating point (FPH2 instr.) also use the same register set
27 CCIfType<[f32], CCAssignToReg<[R2, R3]>>,
28 CCIfByVal>,
29 // Stack parameter slots for i32 is 32-bit words and 4-byte aligned.
30 CCIfType<[i32], CCAssignToStack<4, 4>>
31 ]>;
32
33 def CSR : CalleeSavedRegs<(add RA, FP, (sequence "R%u", 16, 23))>;
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lib/Target/Nios2/Nios2FrameLowering.cpp less more
None //===-- Nios2FrameLowering.cpp - Nios2 Frame Information ------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2FrameLowering.h"
14
15 #include "Nios2Subtarget.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17
18 using namespace llvm;
19
20 bool Nios2FrameLowering::hasFP(const MachineFunction &MF) const { return true; }
21
22 void Nios2FrameLowering::emitPrologue(MachineFunction &MF,
23 MachineBasicBlock &MBB) const {}
24
25 void Nios2FrameLowering::emitEpilogue(MachineFunction &MF,
26 MachineBasicBlock &MBB) const {}
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lib/Target/Nios2/Nios2FrameLowering.h less more
None //===-- Nios2FrameLowering.h - Define frame lowering for Nios2 --*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2FRAMELOWERING_H
13 #define LLVM_LIB_TARGET_NIOS2_NIOS2FRAMELOWERING_H
14
15 #include "Nios2.h"
16 #include "llvm/CodeGen/TargetFrameLowering.h"
17
18 namespace llvm {
19 class Nios2Subtarget;
20
21 class Nios2FrameLowering : public TargetFrameLowering {
22 protected:
23 const Nios2Subtarget &STI;
24
25 public:
26 explicit Nios2FrameLowering(const Nios2Subtarget &sti)
27 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0, 4),
28 STI(sti) {}
29
30 bool hasFP(const MachineFunction &MF) const override;
31 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
32 /// the function.
33 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
34 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
35 };
36 } // namespace llvm
37
38 #endif
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lib/Target/Nios2/Nios2ISelDAGToDAG.cpp less more
None //===-- Nios2ISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Nios2 ------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the NIOS2 target.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2.h"
14 #include "Nios2TargetMachine.h"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/Support/Debug.h"
17 using namespace llvm;
18
19 #define DEBUG_TYPE "nios2-isel"
20
21 //===----------------------------------------------------------------------===//
22 // Instruction Selector Implementation
23 //===----------------------------------------------------------------------===//
24
25 //===----------------------------------------------------------------------===//
26 // Nios2DAGToDAGISel - NIOS2 specific code to select NIOS2 machine
27 // instructions for SelectionDAG operations.
28 //===----------------------------------------------------------------------===//
29
30 namespace {
31
32 class Nios2DAGToDAGISel : public SelectionDAGISel {
33 /// Subtarget - Keep a pointer to the Nios2 Subtarget around so that we can
34 /// make the right decision when generating code for different targets.
35 const Nios2Subtarget *Subtarget;
36
37 public:
38 explicit Nios2DAGToDAGISel(Nios2TargetMachine &TM, CodeGenOpt::Level OL)
39 : SelectionDAGISel(TM, OL) {}
40
41 bool runOnMachineFunction(MachineFunction &MF) override {
42 Subtarget = &MF.getSubtarget();
43 return SelectionDAGISel::runOnMachineFunction(MF);
44 }
45
46 void Select(SDNode *N) override;
47
48 // Pass Name
49 StringRef getPassName() const override {
50 return "NIOS2 DAG->DAG Pattern Instruction Selection";
51 }
52
53 #include "Nios2GenDAGISel.inc"
54 };
55 } // namespace
56
57 // Select instructions not customized! Used for
58 // expanded, promoted and normal instructions
59 void Nios2DAGToDAGISel::Select(SDNode *Node) {
60
61 // If we have a custom node, we already have selected!
62 if (Node->isMachineOpcode()) {
63 LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
64 Node->setNodeId(-1);
65 return;
66 }
67
68 // Select the default instruction
69 SelectCode(Node);
70 }
71
72 FunctionPass *llvm::createNios2ISelDag(Nios2TargetMachine &TM,
73 CodeGenOpt::Level OptLevel) {
74 return new Nios2DAGToDAGISel(TM, OptLevel);
75 }
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lib/Target/Nios2/Nios2ISelLowering.cpp less more
None //===-- Nios2ISelLowering.cpp - Nios2 DAG Lowering Implementation ---------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Nios2 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Nios2ISelLowering.h"
15 #include "Nios2MachineFunction.h"
16 #include "Nios2TargetMachine.h"
17 #include "llvm/CodeGen/CallingConvLower.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19
20 using namespace llvm;
21
22 //===----------------------------------------------------------------------===//
23 // Calling Convention Implementation
24 //===----------------------------------------------------------------------===//
25
26 #include "Nios2GenCallingConv.inc"
27
28 SDValue
29 Nios2TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
30 bool IsVarArg,
31 const SmallVectorImpl &Outs,
32 const SmallVectorImpl &OutVals,
33 const SDLoc &DL, SelectionDAG &DAG) const {
34 // CCValAssign - represent the assignment of
35 // the return value to a location
36 SmallVector RVLocs;
37 MachineFunction &MF = DAG.getMachineFunction();
38
39 // CCState - Info about the registers and stack slot.
40 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
41 // Analyze return values.
42 CCInfo.CheckReturn(Outs, RetCC_Nios2EABI);
43
44 SDValue Flag;
45 SmallVector RetOps(1, Chain);
46
47 // Copy the result values into the output registers.
48 for (unsigned i = 0; i != RVLocs.size(); ++i) {
49 SDValue Val = OutVals[i];
50 CCValAssign &VA = RVLocs[i];
51 assert(VA.isRegLoc() && "Can only return in registers!");
52
53 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
54 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
55
56 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
57
58 // Guarantee that all emitted copies are stuck together with flags.
59 Flag = Chain.getValue(1);
60 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
61 }
62
63 if (Flag.getNode())
64 RetOps.push_back(Flag);
65
66 return DAG.getNode(Nios2ISD::Ret, DL, MVT::Other, RetOps);
67 }
68
69 // addLiveIn - This helper function adds the specified physical register to the
70 // MachineFunction as a live in value. It also creates a corresponding
71 // virtual register for it.
72 static unsigned addLiveIn(MachineFunction &MF, unsigned PReg,
73 const TargetRegisterClass *RC) {
74 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
75 MF.getRegInfo().addLiveIn(PReg, VReg);
76 return VReg;
77 }
78
79 //===----------------------------------------------------------------------===//
80 // Formal Arguments Calling Convention Implementation
81 //===----------------------------------------------------------------------===//
82
83 // LowerFormalArguments - transform physical registers into virtual registers
84 // and generate load operations for arguments places on the stack.
85 SDValue Nios2TargetLowering::LowerFormalArguments(
86 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
87 const SmallVectorImpl &Ins, const SDLoc &DL,
88 SelectionDAG &DAG, SmallVectorImpl &InVals) const {
89 MachineFunction &MF = DAG.getMachineFunction();
90 MachineFrameInfo &MFI = MF.getFrameInfo();
91
92 // Assign locations to all of the incoming arguments.
93 SmallVector ArgLocs;
94 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
95 *DAG.getContext());
96
97 CCInfo.AnalyzeFormalArguments(Ins, CC_Nios2);
98
99 // Used with vargs to acumulate store chains.
100 std::vector OutChains;
101
102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
103 CCValAssign &VA = ArgLocs[i];
104
105 EVT ValVT = VA.getValVT();
106
107 // Arguments stored on registers
108 if (VA.isRegLoc()) {
109 MVT RegVT = VA.getLocVT();
110 unsigned ArgReg = VA.getLocReg();
111 const TargetRegisterClass *RC = getRegClassFor(RegVT);
112
113 // Transform the arguments stored on
114 // physical registers into virtual ones
115 unsigned Reg = addLiveIn(MF, ArgReg, RC);
116 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
117
118 // If this is an 8 or 16-bit value, it has been passed promoted
119 // to 32 bits. Insert an assert[sz]ext to capture this, then
120 // truncate to the right size.
121 if (VA.getLocInfo() != CCValAssign::Full) {
122 unsigned Opcode = 0;
123 if (VA.getLocInfo() == CCValAssign::SExt)
124 Opcode = ISD::AssertSext;
125 else if (VA.getLocInfo() == CCValAssign::ZExt)
126 Opcode = ISD::AssertZext;
127 if (Opcode)
128 ArgValue =
129 DAG.getNode(Opcode, DL, RegVT, ArgValue, DAG.getValueType(ValVT));
130 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
131 }
132
133 // Handle floating point arguments passed in integer registers.
134 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
135 (RegVT == MVT::i64 && ValVT == MVT::f64))
136 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
137 InVals.push_back(ArgValue);
138 } else { // VA.isRegLoc()
139 MVT LocVT = VA.getLocVT();
140
141 // sanity check
142 assert(VA.isMemLoc());
143
144 // The stack pointer offset is relative to the caller stack frame.
145 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
146 VA.getLocMemOffset(), true);
147
148 // Create load nodes to retrieve arguments from the stack
149 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
150 SDValue Load = DAG.getLoad(
151 LocVT, DL, Chain, FIN,
152 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
153 InVals.push_back(Load);
154 OutChains.push_back(Load.getValue(1));
155 }
156 }
157 if (!OutChains.empty()) {
158 OutChains.push_back(Chain);
159 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
160 }
161
162 return Chain;
163 }
164
165 //===----------------------------------------------------------------------===//
166 // TargetLowering Implementation
167 //===----------------------------------------------------------------------===//
168
169 Nios2TargetLowering::Nios2TargetLowering(const TargetMachine &TM,
170 const Nios2Subtarget &STI)
171 : TargetLowering(TM), Subtarget(&STI) {
172
173 addRegisterClass(MVT::i32, &Nios2::CPURegsRegClass);
174 computeRegisterProperties(Subtarget->getRegisterInfo());
175 }
176
177 const char *Nios2TargetLowering::getTargetNodeName(unsigned Opcode) const {
178 switch (Opcode) {
179 case Nios2ISD::Hi:
180 return "Nios2ISD::Hi";
181 case Nios2ISD::Lo:
182 return "Nios2ISD::Lo";
183 case Nios2ISD::Ret:
184 return "Nios2ISD::Ret";
185 }
186 return nullptr;
187 }
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lib/Target/Nios2/Nios2ISelLowering.h less more
None //===-- Nios2ISelLowering.h - Nios2 DAG Lowering Interface ------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Nios2 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2ISELLOWERING_H
15 #define LLVM_LIB_TARGET_NIOS2_NIOS2ISELLOWERING_H
16
17 #include "Nios2.h"
18 #include "llvm/CodeGen/TargetLowering.h"
19
20 namespace llvm {
21 class Nios2Subtarget;
22
23 namespace Nios2ISD {
24 enum NodeType {
25 // Start the numbering from where ISD NodeType finishes.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28 // Get the Higher 16 bits from a 32-bit immediate
29 // No relation with Nios2 Hi register
30 Hi,
31 // Get the Lower 16 bits from a 32-bit immediate
32 // No relation with Nios2 Lo register
33 Lo,
34 // Return
35 Ret
36 };
37 }
38
39 class Nios2TargetLowering : public TargetLowering {
40 const Nios2Subtarget *Subtarget;
41
42 public:
43 Nios2TargetLowering(const TargetMachine &TM, const Nios2Subtarget &STI);
44
45 /// getTargetNodeName - This method returns the name of a target specific
46 // DAG node.
47 const char *getTargetNodeName(unsigned Opcode) const override;
48
49 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
50 bool IsVarArg,
51 const SmallVectorImpl &Ins,
52 const SDLoc &dl, SelectionDAG &DAG,
53 SmallVectorImpl &InVals) const override;
54
55 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
56 const SmallVectorImpl &Outs,
57 const SmallVectorImpl &OutVals, const SDLoc &dl,
58 SelectionDAG &DAG) const override;
59 };
60 } // end namespace llvm
61
62 #endif // NIOS2_ISELLOWERING_H
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lib/Target/Nios2/Nios2InstrFormats.td less more
None //===-- Nios2InstrFormats.td - Nios2 Instruction Formats ---*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
10 // Describe NIOS2 instructions format
11 //
12 //
13 //===----------------------------------------------------------------------===//
14
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
17 // code emitter.
18 class Format val> {
19 bits<6> Value = val;
20 }
21
22 def Pseudo : Format<0>;
23 // Nios2 R1 instr formats:
24 def FrmI : Format<1>;
25 def FrmR : Format<2>;
26 def FrmJ : Format<3>;
27 def FrmOther : Format<4>; // Instruction w/ a custom format
28 // Nios2 R2 instr 32-bit formats:
29 def FrmL26 : Format<5>; // corresponds to J format in R1
30 def FrmF2I16 : Format<6>; // corresponds to I format in R1
31 def FrmF2X4I12 : Format<7>;
32 def FrmF1X4I12 : Format<8>;
33 def FrmF1X4L17 : Format<9>;
34 def FrmF3X6L5 : Format<10>; // corresponds to R format in R1
35 def FrmF2X6L10 : Format<11>;
36 def FrmF3X6 : Format<12>; // corresponds to R format in R1
37 def FrmF3X8 : Format<13>; // corresponds to custom format in R1
38 // Nios2 R2 instr 16-bit formats:
39 def FrmI10 : Format<14>;
40 def FrmT1I7 : Format<15>;
41 def FrmT2I4 : Format<16>;
42 def FrmT1X1I6 : Format<17>;
43 def FrmX1I7 : Format<18>;
44 def FrmL5I4X1 : Format<19>;
45 def FrmT2X1L3 : Format<20>;
46 def FrmT2X1I3 : Format<21>;
47 def FrmT3X1 : Format<22>;
48 def FrmT2X3 : Format<23>;
49 def FrmF1X1 : Format<24>;
50 def FrmX2L5 : Format<25>;
51 def FrmF1I5 : Format<26>;
52 def FrmF2 : Format<27>;
53
54 //===----------------------------------------------------------------------===//
55 // Instruction Predicates:
56 //===----------------------------------------------------------------------===//
57
58 def isNios2r1 : Predicate<"Subtarget->isNios2r1()">;
59 def isNios2r2 : Predicate<"Subtarget->isNios2r2()">;
60
61 class PredicateControl {
62 // Predicates related to specific target CPU features
63 list FeaturePredicates = [];
64 // Predicates for the instruction group membership in given ISA
65 list InstrPredicates = [];
66
67 list Predicates = !listconcat(FeaturePredicates, InstrPredicates);
68 }
69
70 //===----------------------------------------------------------------------===//
71 // Base classes for 32-bit, 16-bit and pseudo instructions
72 //===----------------------------------------------------------------------===//
73
74 class Nios2Inst32 pattern,
75 InstrItinClass itin, Format f>: Instruction,
76 PredicateControl {
77 field bits<32> Inst;
78 Format Form = f;
79
80 let Namespace = "Nios2";
81 let Size = 4;
82
83 bits<6> Opcode = 0;
84
85 // Bottom 6 bits are the 'opcode' field
86 let Inst{5-0} = Opcode;
87
88 let OutOperandList = outs;
89 let InOperandList = ins;
90
91 let AsmString = asmstr;
92 let Pattern = pattern;
93 let Itinerary = itin;
94
95 // Attributes specific to Nios2 instructions:
96
97 // TSFlags layout should be kept in sync with Nios2InstrInfo.h.
98 let TSFlags{5-0} = Form.Value;
99 let DecoderNamespace = "Nios2";
100 field bits<32> SoftFail = 0;
101 }
102
103 class Nios2Pseudo pattern,
104 InstrItinClass Itin = IIPseudo>:
105 Nios2Inst32 {
106
107 let isCodeGenOnly = 1;
108 let isPseudo = 1;
109 }
110
111 //===----------------------------------------------------------------------===//
112 // Base classes for R1 and R2 instructions
113 //===----------------------------------------------------------------------===//
114
115 class Nios2R1Inst32 pattern,
116 InstrItinClass itin, Format f>:
117 Nios2Inst32 {
118 let DecoderNamespace = "Nios2";
119 let InstrPredicates = [isNios2r1];
120 }
121
122 class Nios2R2Inst32 pattern,
123 InstrItinClass itin, Format f>:
124 Nios2Inst32 {
125 let DecoderNamespace = "Nios2r2";
126 let InstrPredicates = [isNios2r2];
127 }
128
129 //===----------------------------------------------------------------------===//
130 // Format I instruction class in Nios2 : <|A|B|immediate|opcode|>
131 //===----------------------------------------------------------------------===//
132
133 class FI op, dag outs, dag ins, string asmstr, list pattern,
134 InstrItinClass itin>: Nios2R1Inst32
135 pattern, itin, FrmI> {
136
137 bits<5> rA;
138 bits<5> rB;
139 bits<16> imm;
140
141 let Opcode = op;
142
143 let Inst{31-27} = rA;
144 let Inst{26-22} = rB;
145 let Inst{21-6} = imm;
146 }
147
148
149 //===----------------------------------------------------------------------===//
150 // Format R instruction : <|A|B|C|opx|imm|opcode|>
151 //===----------------------------------------------------------------------===//
152
153 class FR opx, dag outs, dag ins, string asmstr, list pattern,
154 InstrItinClass itin>: Nios2R1Inst32
155 pattern, itin, FrmR> {
156 bits<5> rA;
157 bits<5> rB;
158 bits<5> rC;
159 bits<5> imm = 0;
160
161 let Opcode = 0x3a; /* opcode is always 0x3a for R instr. */
162
163 let Inst{31-27} = rA;
164 let Inst{26-22} = rB;
165 let Inst{21-17} = rC;
166 let Inst{16-11} = opx; /* opx stands for opcode extension */
167 let Inst{10-6} = imm; /* optional 5-bit immediate value */
168 }
169
170 //===----------------------------------------------------------------------===//
171 // Format J instruction class in Nios2 : <|address|opcode|>
172 //===----------------------------------------------------------------------===//
173
174 class FJ op, dag outs, dag ins, string asmstr, list pattern,
175 InstrItinClass itin>:
176 Nios2R1Inst32 {
177 bits<26> addr;
178 let Opcode = op;
179 let Inst{31-6} = addr;
180 }
181
182 //===----------------------------------------------------------------------===//
183 // Format F3X6 (R2) instruction : <|opx|RSV|C|B|A|opcode|>
184 //===----------------------------------------------------------------------===//
185
186 class F3X6 opx, dag outs, dag ins, string asmstr, list pattern,
187 InstrItinClass itin>:
188 Nios2R2Inst32 {
189 bits<5> rC;
190 bits<5> rB;
191 bits<5> rA;
192 bits<5> rsv = 0;
193
194 let Opcode = 0x20; /* opcode is always 0x20 (OPX group) for F3X6 instr. */
195
196 let Inst{31-26} = opx; /* opx stands for opcode extension */
197 let Inst{25-21} = rsv;
198 let Inst{20-16} = rC;
199 let Inst{15-11} = rB;
200 let Inst{10-6} = rA;
201 }
202
203 //===----------------------------------------------------------------------===//
204 // Multiclasses for common instructions of both R1 and R2:
205 //===----------------------------------------------------------------------===//
206
207 // Multiclass for instructions that have R format in R1 and F3X6 format in R2
208 // and their opx values differ between R1 and R2
209 multiclass CommonInstr_R_F3X6_opx opxR1, bits<6> opxR2, dag outs,
210 dag ins, string asmstr, list pattern,
211 InstrItinClass itin> {
212 def NAME#_R1 : FR;
213 def NAME#_R2 : F3X6;
214 }
215
216 // Multiclass for instructions that have R format in R1 and F3X6 format in R2
217 // and their opx values are the same in R1 and R2
218 multiclass CommonInstr_R_F3X6 opx, dag outs, dag ins, string asmstr,
219 list pattern, InstrItinClass itin> :
220 CommonInstr_R_F3X6_opx;
221
222 // Multiclass for instructions that have I format in R1 and F2I16 format in R2
223 // and their op code values differ between R1 and R2
224 multiclass CommonInstr_I_F2I16_op opR1, bits<6> opR2, dag outs, dag ins,
225 string asmstr, list pattern,
226 InstrItinClass itin> {
227 def NAME#_R1 : FI;
228 }
229
230 // Multiclass for instructions that have I format in R1 and F2I16 format in R2
231 // and their op code values are the same in R1 and R2
232 multiclass CommonInstr_I_F2I16 op, dag outs, dag ins, string asmstr,
233 list pattern, InstrItinClass itin> :
234 CommonInstr_I_F2I16_op;
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lib/Target/Nios2/Nios2InstrInfo.cpp less more
None //===-- Nios2InstrInfo.cpp - Nios2 Instruction Information ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2InstrInfo.h"
14 #include "Nios2TargetMachine.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16
17 using namespace llvm;
18
19 #define GET_INSTRINFO_CTOR_DTOR
20 #include "Nios2GenInstrInfo.inc"
21
22 // Pin the vtable to this file.
23 void Nios2InstrInfo::anchor() {}
24
25 Nios2InstrInfo::Nios2InstrInfo(Nios2Subtarget &ST)
26 : Nios2GenInstrInfo(), RI(ST), Subtarget(ST) {}
27
28 /// Expand Pseudo instructions into real backend instructions
29 bool Nios2InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
30 MachineBasicBlock &MBB = *MI.getParent();
31
32 switch (MI.getDesc().getOpcode()) {
33 default:
34 return false;
35 case Nios2::RetRA:
36 BuildMI(MBB, MI, MI.getDebugLoc(), get(Nios2::RET_R1)).addReg(Nios2::RA);
37 break;
38 }
39
40 MBB.erase(MI);
41 return true;
42 }
43
44 void Nios2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator I,
46 const DebugLoc &DL, unsigned DestReg,
47 unsigned SrcReg, bool KillSrc) const {
48 unsigned opc = Subtarget.hasNios2r2() ? Nios2::ADD_R2 : Nios2::ADD_R1;
49 BuildMI(MBB, I, DL, get(opc))
50 .addReg(DestReg, RegState::Define)
51 .addReg(Nios2::ZERO)
52 .addReg(SrcReg, getKillRegState(KillSrc));
53 }
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lib/Target/Nios2/Nios2InstrInfo.h less more
None //===-- Nios2InstrInfo.h - Nios2 Instruction Information --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
14 #define LLVM_LIB_TARGET_NIOS2_NIOS2INSTRINFO_H
15
16 #include "Nios2RegisterInfo.h"
17 #include "llvm/CodeGen/TargetInstrInfo.h"
18
19 #define GET_INSTRINFO_HEADER
20 #include "Nios2GenInstrInfo.inc"
21
22 namespace llvm {
23
24 class Nios2Subtarget;
25
26 class Nios2InstrInfo : public Nios2GenInstrInfo {
27 const Nios2RegisterInfo RI;
28 const Nios2Subtarget &Subtarget;
29 virtual void anchor();
30
31 public:
32 explicit Nios2InstrInfo(Nios2Subtarget &ST);
33
34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
35 /// such, whenever a client has an instance of instruction info, it should
36 /// always be able to get register info as well (through this method).
37 ///
38 const Nios2RegisterInfo &getRegisterInfo() const { return RI; };
39
40 bool expandPostRAPseudo(MachineInstr &MI) const override;
41
42 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
43 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
44 bool KillSrc) const override;
45 };
46 } // namespace llvm
47
48 #endif
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lib/Target/Nios2/Nios2InstrInfo.td less more
None //===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
14 // Instruction format superclass
15 //===----------------------------------------------------------------------===//
16
17 include "Nios2InstrFormats.td"
18
19
20 //===----------------------------------------------------------------------===//
21 // Nios2 Operand, Complex Patterns and Transformations Definitions.
22 //===----------------------------------------------------------------------===//
23
24 def simm16 : Operand {
25 let DecoderMethod= "DecodeSimm16";
26 }
27
28 // Node immediate fits as 16-bit sign extended on target immediate.
29 // e.g. addi, andi
30 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
31
32 // Custom return SDNode
33 def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
34 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
35
36 //===----------------------------------------------------------------------===//
37 // Instructions specific format
38 //===----------------------------------------------------------------------===//
39
40 // Arithmetic and logical instructions with 2 registers and 16-bit immediate
41 // value.
42 multiclass ArithLogicRegImm16 op, string mnemonic, SDNode opNode,
43 Operand immOp, PatLeaf immType>:
44 CommonInstr_I_F2I16
45 (ins CPURegs:$rA, immOp:$imm),
46 !strconcat(mnemonic, "\t$rB, $rA, $imm"),
47 [(set CPURegs:$rB,
48 (opNode CPURegs:$rA, immType:$imm))],
49 IIAlu>;
50
51 // Arithmetic and logical instructions with 3 register operands.
52 // Defines R1 and R2 instruction at the same time.
53 multiclass ArithLogicReg opx, string mnemonic,
54 SDNode opNode>:
55 CommonInstr_R_F3X6
56 (ins CPURegs:$rA, CPURegs:$rB),
57 !strconcat(mnemonic, "\t$rC, $rA, $rB"),
58 [(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
59 IIAlu>;
60
61 multiclass Return opx, dag outs, dag ins, string mnemonic> {
62 let rB = 0, rC = 0,
63 isReturn = 1,
64 isCodeGenOnly = 1,
65 hasCtrlDep = 1,
66 hasExtraSrcRegAllocReq = 1 in {
67 defm NAME# : CommonInstr_R_F3X6;
68 }
69 }
70
71 //===----------------------------------------------------------------------===//
72 // Nios2 Instructions
73 //===----------------------------------------------------------------------===//
74
75 /// Arithmetic instructions operating on registers.
76 let isCommutable = 1 ,
77 isReMaterializable = 1 in {
78 defm ADD : ArithLogicReg<0x31, "add", add>;
79 defm AND : ArithLogicReg<0x0e, "and", and>;
80 defm OR : ArithLogicReg<0x16, "or", or>;
81 defm XOR : ArithLogicReg<0x1e, "xor", xor>;
82 defm MUL : ArithLogicReg<0x27, "mul", mul>;
83 }
84
85 let isReMaterializable = 1 in {
86 defm SUB : ArithLogicReg<0x39, "sub", sub>;
87 }
88
89 defm DIVU : ArithLogicReg<0x24, "divu", udiv>;
90 defm DIV : ArithLogicReg<0x25, "div", sdiv>;
91
92 defm SLL : ArithLogicReg<0x13, "sll", shl>;
93 defm SRL : ArithLogicReg<0x1b, "srl", srl>;
94 defm SRA : ArithLogicReg<0x3b, "sra", sra>;
95
96 /// Arithmetic Instructions (ALU Immediate)
97 defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
98
99 // Returns:
100 defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
101
102 //===----------------------------------------------------------------------===//
103 // Pseudo instructions
104 //===----------------------------------------------------------------------===//
105
106 // Return RA.
107 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
108 def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;
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lib/Target/Nios2/Nios2MCInstLower.cpp less more
None //===-- Nios2MCInstLower.cpp - Convert Nios2 MachineInstr to MCInst -------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower Nios2 MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/Nios2BaseInfo.h"
15 #include "MCTargetDesc/Nios2MCExpr.h"
16 #include "Nios2.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineOperand.h"
20
21 using namespace llvm;
22
23 static MCOperand LowerSymbolOperand(const MachineOperand &MO, AsmPrinter &AP) {
24 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
25 Nios2MCExpr::Nios2ExprKind TargetKind = Nios2MCExpr::CEK_None;
26 const MCSymbol *Symbol;
27
28 switch (MO.getTargetFlags()) {
29 default:
30 llvm_unreachable("Invalid target flag!");
31 case Nios2FG::MO_NO_FLAG:
32 break;
33 case Nios2FG::MO_ABS_HI:
34 TargetKind = Nios2MCExpr::CEK_ABS_HI;
35 break;
36 case Nios2FG::MO_ABS_LO:
37 TargetKind = Nios2MCExpr::CEK_ABS_LO;
38 break;
39 }
40
41 switch (MO.getType()) {
42 case MachineOperand::MO_GlobalAddress:
43 Symbol = AP.getSymbol(MO.getGlobal());
44 break;
45
46 case MachineOperand::MO_MachineBasicBlock:
47 Symbol = MO.getMBB()->getSymbol();
48 break;
49
50 case MachineOperand::MO_BlockAddress:
51 Symbol = AP.GetBlockAddressSymbol(MO.getBlockAddress());
52 break;
53
54 case MachineOperand::MO_ExternalSymbol:
55 Symbol = AP.GetExternalSymbolSymbol(MO.getSymbolName());
56 break;
57
58 case MachineOperand::MO_JumpTableIndex:
59 Symbol = AP.GetJTISymbol(MO.getIndex());
60 break;
61
62 case MachineOperand::MO_ConstantPoolIndex:
63 Symbol = AP.GetCPISymbol(MO.getIndex());
64 break;
65
66 default:
67 llvm_unreachable("");
68 }
69
70 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol, Kind, AP.OutContext);
71
72 if (TargetKind != Nios2MCExpr::CEK_None)
73 Expr = Nios2MCExpr::create(TargetKind, Expr, AP.OutContext);
74
75 return MCOperand::createExpr(Expr);
76 }
77
78 static MCOperand LowerOperand(const MachineOperand &MO, AsmPrinter &AP) {
79
80 switch (MO.getType()) {
81 default:
82 llvm_unreachable("unknown operand type");
83 case MachineOperand::MO_Register:
84 // Ignore all implicit register operands.
85 if (MO.isImplicit())
86 break;
87 return MCOperand::createReg(MO.getReg());
88 case MachineOperand::MO_Immediate:
89 return MCOperand::createImm(MO.getImm());
90 case MachineOperand::MO_MachineBasicBlock:
91 case MachineOperand::MO_ExternalSymbol:
92 case MachineOperand::MO_JumpTableIndex:
93 case MachineOperand::MO_BlockAddress:
94 case MachineOperand::MO_GlobalAddress:
95 case MachineOperand::MO_ConstantPoolIndex:
96 return LowerSymbolOperand(MO, AP);
97 case MachineOperand::MO_RegisterMask:
98 break;
99 }
100
101 return MCOperand();
102 }
103
104 void llvm::LowerNios2MachineInstToMCInst(const MachineInstr *MI, MCInst &OutMI,
105 AsmPrinter &AP) {
106
107 OutMI.setOpcode(MI->getOpcode());
108
109 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
110 const MachineOperand &MO = MI->getOperand(i);
111 MCOperand MCOp = LowerOperand(MO, AP);
112
113 if (MCOp.isValid())
114 OutMI.addOperand(MCOp);
115 }
116 }
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lib/Target/Nios2/Nios2MachineFunction.cpp less more
None //===-- Nios2MachineFunctionInfo.cpp - Private data used for Nios2 --------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Nios2MachineFunction.h"
10
11 using namespace llvm;
12
13 void Nios2FunctionInfo::anchor() {}
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lib/Target/Nios2/Nios2MachineFunction.h less more
None //===-- Nios2MachineFunctionInfo.h - Private data used for Nios2 --*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Nios2 specific subclass of MachineFunctionInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2MACHINEFUNCTION_H
14 #define LLVM_LIB_TARGET_NIOS2_NIOS2MACHINEFUNCTION_H
15
16 #include "llvm/CodeGen/MachineFunction.h"
17
18 namespace llvm {
19
20 /// Nios2FunctionInfo - This class is derived from MachineFunction private
21 /// Nios2 target-specific information for each MachineFunction.
22 class Nios2FunctionInfo : public MachineFunctionInfo {
23 virtual void anchor();
24
25 private:
26 unsigned GlobalBaseReg;
27
28 /// VarArgsFrameOffset - Frame offset to start of varargs area.
29 int VarArgsFrameOffset;
30
31 /// SRetReturnReg - Holds the virtual register into which the sret
32 /// argument is passed.
33 unsigned SRetReturnReg;
34
35 /// IsLeafProc - True if the function is a leaf procedure.
36 bool IsLeafProc;
37
38 public:
39 Nios2FunctionInfo()
40 : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
41 IsLeafProc(false) {}
42 explicit Nios2FunctionInfo(MachineFunction &MF)
43 : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
44 IsLeafProc(false) {}
45
46 unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
47 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
48
49 int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
50 void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
51
52 unsigned getSRetReturnReg() const { return SRetReturnReg; }
53 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
54
55 void setLeafProc(bool rhs) { IsLeafProc = rhs; }
56 bool isLeafProc() const { return IsLeafProc; }
57 };
58
59 } // end of namespace llvm
60
61 #endif // NIOS2_MACHINE_FUNCTION_INFO_H
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lib/Target/Nios2/Nios2RegisterInfo.cpp less more
None //===-- Nios2RegisterInfo.cpp - Nios2 Register Information -== ------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #define DEBUG_TYPE "nios2-reg-info"
14
15 #include "Nios2RegisterInfo.h"
16
17 #include "Nios2.h"
18 #include "Nios2Subtarget.h"
19
20 #define GET_REGINFO_TARGET_DESC
21 #include "Nios2GenRegisterInfo.inc"
22
23 using namespace llvm;
24
25 Nios2RegisterInfo::Nios2RegisterInfo(const Nios2Subtarget &ST)
26 : Nios2GenRegisterInfo(Nios2::RA), Subtarget(ST) {}
27
28 const TargetRegisterClass *Nios2RegisterInfo::intRegClass(unsigned Size) const {
29 return &Nios2::CPURegsRegClass;
30 }
31
32 const MCPhysReg *
33 Nios2RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
34 return CSR_SaveList;
35 }
36
37 BitVector Nios2RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
38 static const MCPhysReg ReservedCPURegs[] = {Nios2::ZERO, Nios2::AT, Nios2::SP,
39 Nios2::RA, Nios2::PC, Nios2::GP};
40 BitVector Reserved(getNumRegs());
41
42 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
43 Reserved.set(ReservedCPURegs[I]);
44
45 return Reserved;
46 }
47
48 void Nios2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
49 int SPAdj, unsigned FIOperandNum,
50 RegScavenger *RS) const {}
51
52 unsigned Nios2RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
53 return Nios2::SP;
54 }
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lib/Target/Nios2/Nios2RegisterInfo.h less more
None //===-- Nios2RegisterInfo.h - Nios2 Register Information Impl ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Nios2 implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
14 #define LLVM_LIB_TARGET_NIOS2_NIOS2REGISTERINFO_H
15
16 #include "Nios2.h"
17 #include "llvm/CodeGen/TargetRegisterInfo.h"
18
19 #define GET_REGINFO_HEADER
20 #include "Nios2GenRegisterInfo.inc"
21
22 namespace llvm {
23 class Nios2Subtarget;
24 class TargetInstrInfo;
25 class Type;
26
27 class Nios2RegisterInfo : public Nios2GenRegisterInfo {
28 protected:
29 const Nios2Subtarget &Subtarget;
30
31 public:
32 Nios2RegisterInfo(const Nios2Subtarget &Subtarget);
33
34 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
35
36 BitVector getReservedRegs(const MachineFunction &MF) const override;
37
38 /// Stack Frame Processing Methods
39 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
40 unsigned FIOperandNum,
41 RegScavenger *RS = nullptr) const override;
42
43 /// Debug information queries.
44 unsigned getFrameRegister(const MachineFunction &MF) const override;
45
46 /// Return GPR register class.
47 const TargetRegisterClass *intRegClass(unsigned Size) const;
48 };
49
50 } // end namespace llvm
51 #endif
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lib/Target/Nios2/Nios2RegisterInfo.td less more
None //===-- Nios2RegisterInfo.td - Nios2 Register defs ---------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 // We have bank of 32 registers.
10 class Nios2Reg : Register {
11 field bits<5> Num;
12 let Namespace = "Nios2";
13 }
14
15 // Nios2 CPU Registers
16 class Nios2GPRReg num, string n> : Nios2Reg {
17 let Num = num;
18 }
19
20 //===----------------------------------------------------------------------===//
21 // Registers
22 //===----------------------------------------------------------------------===//
23
24 let Namespace = "Nios2" in {
25 // General Purpose Registers
26 def ZERO : Nios2GPRReg<0, "zero">, DwarfRegNum<[ 0 ]>;
27 def AT : Nios2GPRReg<1, "at">, DwarfRegNum<[ 1 ]>;
28 foreach RegNum = 2 - 23 in {
29 def R #RegNum : Nios2GPRReg, DwarfRegNum<[ RegNum ]>;
30 }
31 def ET : Nios2GPRReg<24, "et">, DwarfRegNum<[ 24 ]>;
32 def BT : Nios2GPRReg<25, "bt">, DwarfRegNum<[ 25 ]>;
33 def GP : Nios2GPRReg<26, "gp">, DwarfRegNum<[ 26 ]>;
34 def SP : Nios2GPRReg<27, "sp">, DwarfRegNum<[ 27 ]>;
35 def FP : Nios2GPRReg<28, "fp">, DwarfRegNum<[ 28 ]>;
36 def EA : Nios2GPRReg<29, "ea">, DwarfRegNum<[ 29 ]>;
37 def BA : Nios2GPRReg<30, "ba">, DwarfRegNum<[ 30 ]>;
38 def RA : Nios2GPRReg<31, "ra">, DwarfRegNum<[ 31 ]>;
39 def PC : Nios2Reg<"pc">, DwarfRegNum<[ 32 ]>;
40 }
41
42 //===----------------------------------------------------------------------===//
43 // Register Classes
44 //===----------------------------------------------------------------------===//
45
46 def CPURegs : RegisterClass<"Nios2", [ i32 ], 32,
47 (add
48 // Reserved
49 ZERO,
50 AT,
51 // Return Values and Arguments
52 (sequence "R%u", 2, 7),
53 // Not preserved across procedure calls
54 // Caller saved
55 (sequence "R%u", 8, 15),
56 // Callee saved
57 (sequence "R%u", 16, 23),
58 // Reserved
59 ET, BT, GP, SP, FP, EA, BA, RA, PC)>;
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lib/Target/Nios2/Nios2Schedule.td less more
None //===-- Nios2Schedule.td - Nios2 Scheduling Definitions ----*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
10 // Functional units across Nios2 chips sets. Based on GCC/Nios2 backend files.
11 //===----------------------------------------------------------------------===//
12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
14
15 //===----------------------------------------------------------------------===//
16 // Instruction Itinerary classes used for Nios2
17 //===----------------------------------------------------------------------===//
18 def IIAlu : InstrItinClass;
19 def IILoad : InstrItinClass;
20 def IIStore : InstrItinClass;
21 def IIFlush : InstrItinClass;
22 def IIIdiv : InstrItinClass;
23 def IIBranch : InstrItinClass;
24
25 def IIPseudo : InstrItinClass;
26
27 //===----------------------------------------------------------------------===//
28 // Nios2 Generic instruction itineraries.
29 //===----------------------------------------------------------------------===//
30 //@ http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html
31 def Nios2GenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
32 InstrItinData]>,
33 InstrItinData]>,
34 InstrItinData]>,
35 InstrItinData]>,
36 InstrItinData]>,
37 InstrItinData]>
38 ]>;
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lib/Target/Nios2/Nios2Subtarget.cpp less more
None //===-- Nios2Subtarget.cpp - Nios2 Subtarget Information ------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Nios2 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2Subtarget.h"
14 #include "Nios2.h"
15
16 using namespace llvm;
17
18 #define DEBUG_TYPE "nios2-subtarget"
19
20 #define GET_SUBTARGETINFO_TARGET_DESC
21 #define GET_SUBTARGETINFO_CTOR
22 #include "Nios2GenSubtargetInfo.inc"
23
24 void Nios2Subtarget::anchor() {}
25
26 Nios2Subtarget::Nios2Subtarget(const Triple &TT, const std::string &CPU,
27 const std::string &FS, const TargetMachine &TM)
28 :
29
30 // Nios2GenSubtargetInfo will display features by llc -march=nios2
31 // -mcpu=help
32 Nios2GenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
33 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
34 FrameLowering(*this) {}
35
36 Nios2Subtarget &Nios2Subtarget::initializeSubtargetDependencies(StringRef CPU,
37 StringRef FS) {
38 if (TargetTriple.getArch() == Triple::nios2) {
39 if (CPU != "nios2r2") {
40 CPU = "nios2r1";
41 Nios2ArchVersion = Nios2r1;
42 } else {
43 Nios2ArchVersion = Nios2r2;
44 }
45 } else {
46 errs() << "!!!Error, TargetTriple.getArch() = " << TargetTriple.getArch()
47 << "CPU = " << CPU << "\n";
48 exit(0);
49 }
50
51 // Parse features string.
52 ParseSubtargetFeatures(CPU, FS);
53
54 return *this;
55 }
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lib/Target/Nios2/Nios2Subtarget.h less more
None //===-- Nios2Subtarget.h - Define Subtarget for the Nios2 -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Nios2 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2SUBTARGET_H
14 #define LLVM_LIB_TARGET_NIOS2_NIOS2SUBTARGET_H
15
16 #include "Nios2FrameLowering.h"
17 #include "Nios2ISelLowering.h"
18 #include "Nios2InstrInfo.h"
19 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22
23 #define GET_SUBTARGETINFO_HEADER
24 #include "Nios2GenSubtargetInfo.inc"
25
26 namespace llvm {
27 class StringRef;
28
29 class Nios2TargetMachine;
30
31 class Nios2Subtarget : public Nios2GenSubtargetInfo {
32 virtual void anchor();
33
34 public:
35 // Nios2 R2 features
36 // Bit manipulation instructions extension
37 bool HasBMX;
38 // Code Density instructions extension
39 bool HasCDX;
40 // Multi-Processor instructions extension
41 bool HasMPX;
42 // New mandatory instructions
43 bool HasR2Mandatory;
44
45 protected:
46 enum Nios2ArchEnum {
47 // Nios2 R1 ISA
48 Nios2r1,
49 // Nios2 R2 ISA
50 Nios2r2
51 };
52
53 // Nios2 architecture version
54 Nios2ArchEnum Nios2ArchVersion;
55
56 Triple TargetTriple;
57
58 Nios2InstrInfo InstrInfo;
59 Nios2TargetLowering TLInfo;
60 SelectionDAGTargetInfo TSInfo;
61 Nios2FrameLowering FrameLowering;
62
63 public:
64 /// This constructor initializes the data members to match that
65 /// of the specified triple.
66 Nios2Subtarget(const Triple &TT, const std::string &CPU,
67 const std::string &FS, const TargetMachine &TM);
68
69 /// ParseSubtargetFeatures - Parses features string setting specified
70 /// subtarget options. Definition of function is auto generated by tblgen.
71 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
72
73 bool hasNios2r1() const { return Nios2ArchVersion >= Nios2r1; }
74 bool isNios2r1() const { return Nios2ArchVersion == Nios2r1; }
75 bool hasNios2r2() const { return Nios2ArchVersion >= Nios2r2; }
76 bool isNios2r2() const { return Nios2ArchVersion == Nios2r2; }
77
78 Nios2Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
79
80 const Nios2InstrInfo *getInstrInfo() const override { return &InstrInfo; }
81 const TargetFrameLowering *getFrameLowering() const override {
82 return &FrameLowering;
83 }
84 const Nios2RegisterInfo *getRegisterInfo() const override {
85 return &InstrInfo.getRegisterInfo();
86 }
87 const Nios2TargetLowering *getTargetLowering() const override {
88 return &TLInfo;
89 }
90 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
91 return &TSInfo;
92 }
93 };
94 } // namespace llvm
95
96 #endif
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lib/Target/Nios2/Nios2TargetMachine.cpp less more
None //===-- Nios2TargetMachine.cpp - Define TargetMachine for Nios2 -----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Nios2 target spec.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Nios2TargetMachine.h"
14 #include "Nios2.h"
15 #include "Nios2TargetObjectFile.h"
16
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/Support/TargetRegistry.h"
19
20 using namespace llvm;
21
22 #define DEBUG_TYPE "nios2"
23
24 extern "C" void LLVMInitializeNios2Target() {
25 // Register the target.
26 RegisterTargetMachine X(getTheNios2Target());
27 }
28
29 static std::string computeDataLayout() {
30 return "e-p:32:32:32-i8:8:32-i16:16:32-n32";
31 }
32
33 static Reloc::Model getEffectiveRelocModel(Optional RM) {
34 if (!RM.hasValue())
35 return Reloc::Static;
36 return *RM;
37 }
38
39 Nios2TargetMachine::Nios2TargetMachine(const Target &T, const Triple &TT,
40 StringRef CPU, StringRef FS,
41 const TargetOptions &Options,
42 Optional RM,
43 Optional CM,
44 CodeGenOpt::Level OL, bool JIT)
45 : LLVMTargetMachine(T, computeDataLayout(), TT, CPU, FS, Options,
46 getEffectiveRelocModel(RM),
47 getEffectiveCodeModel(CM, CodeModel::Small), OL),
48 TLOF(make_unique()),
49 Subtarget(TT, CPU, FS, *this) {
50 initAsmInfo();
51 }
52
53 Nios2TargetMachine::~Nios2TargetMachine() {}
54
55 const Nios2Subtarget *
56 Nios2TargetMachine::getSubtargetImpl(const Function &F) const {
57 Attribute CPUAttr = F.getFnAttribute("target-cpu");
58 Attribute FSAttr = F.getFnAttribute("target-features");
59
60 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
61 ? CPUAttr.getValueAsString().str()
62 : TargetCPU;
63 std::string FS = !FSAttr.hasAttribute(Attribute::None)
64 ? FSAttr.getValueAsString().str()
65 : TargetFS;
66
67 auto &I = SubtargetMap[CPU + FS];
68 if (!I) {
69 // This needs to be done before we create a new subtarget since any
70 // creation will depend on the TM and the code generation flags on the
71 // function that reside in TargetOptions.
72 resetTargetOptions(F);
73 I = llvm::make_unique(TargetTriple, CPU, FS, *this);
74 }
75 return I.get();
76 }
77
78 namespace {
79 /// Nios2 Code Generator Pass Configuration Options.
80 class Nios2PassConfig : public TargetPassConfig {
81 public:
82 Nios2PassConfig(Nios2TargetMachine &TM, PassManagerBase *PM)
83 : TargetPassConfig(TM, *PM) {}
84
85 Nios2TargetMachine &getNios2TargetMachine() const {
86 return getTM();
87 }
88
89 void addCodeGenPrepare() override;
90 bool addInstSelector() override;
91 void addIRPasses() override;
92 };
93 } // namespace
94
95 TargetPassConfig *Nios2TargetMachine::createPassConfig(PassManagerBase &PM) {
96 return new Nios2PassConfig(*this, &PM);
97 }
98
99 void Nios2PassConfig::addCodeGenPrepare() {
100 TargetPassConfig::addCodeGenPrepare();
101 }
102
103 void Nios2PassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); }
104
105 // Install an instruction selector pass using
106 // the ISelDag to gen Nios2 code.
107 bool Nios2PassConfig::addInstSelector() {
108 addPass(createNios2ISelDag(getNios2TargetMachine(), getOptLevel()));
109 return false;
110 }
+0
-45
lib/Target/Nios2/Nios2TargetMachine.h less more
None //===-- Nios2TargetMachine.h - Define TargetMachine for Nios2 ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Nios2 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETMACHINE_H
14 #define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETMACHINE_H
15
16 #include "Nios2Subtarget.h"
17 #include "llvm/Target/TargetMachine.h"
18
19 namespace llvm {
20 class Nios2TargetMachine : public LLVMTargetMachine {
21 mutable StringMap> SubtargetMap;
22 std::unique_ptr TLOF;
23 Nios2Subtarget Subtarget;
24
25 public:
26 Nios2TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
27 StringRef FS, const TargetOptions &Options,
28 Optional RM, Optional CM,
29 CodeGenOpt::Level OL, bool JIT);
30 ~Nios2TargetMachine() override;
31
32 const Nios2Subtarget *getSubtargetImpl() const { return &Subtarget; }
33 const Nios2Subtarget *getSubtargetImpl(const Function &F) const override;
34
35 TargetLoweringObjectFile *getObjFileLowering() const override {
36 return TLOF.get();
37 }
38
39 // Pass Pipeline Configuration
40 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
41 };
42 } // namespace llvm
43
44 #endif
+0
-18
lib/Target/Nios2/Nios2TargetObjectFile.cpp less more
None //===-- Nios2TargetObjectFile.cpp - Nios2 Object Files --------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Nios2TargetObjectFile.h"
10
11 using namespace llvm;
12
13 void Nios2TargetObjectFile::Initialize(MCContext &Ctx,
14 const TargetMachine &TM) {
15 TargetLoweringObjectFileELF::Initialize(Ctx, TM);
16 InitializeELF(TM.Options.UseInitArray);
17 }
+0
-26
lib/Target/Nios2/Nios2TargetObjectFile.h less more
None //===-- llvm/Target/Nios2TargetObjectFile.h - Nios2 Object Info -*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETOBJECTFILE_H
10 #define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETOBJECTFILE_H
11
12 #include "Nios2TargetMachine.h"
13 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
14
15 namespace llvm {
16
17 class Nios2TargetObjectFile : public TargetLoweringObjectFileELF {
18 public:
19 Nios2TargetObjectFile() : TargetLoweringObjectFileELF() {}
20
21 void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
22 };
23 } // end namespace llvm
24
25 #endif
+0
-30
lib/Target/Nios2/Nios2TargetStreamer.h less more
None //===-- Nios2TargetStreamer.h - Nios2 Target Streamer ----------*- C++ -*--===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_LIB_TARGET_NIOS2_NIOS2TARGETSTREAMER_H
10 #define LLVM_LIB_TARGET_NIOS2_NIOS2TARGETSTREAMER_H
11
12 #include "llvm/MC/MCRegisterInfo.h"
13 #include "llvm/MC/MCStreamer.h"
14
15 namespace llvm {
16
17 class Nios2TargetStreamer : public MCTargetStreamer {
18 public:
19 Nios2TargetStreamer(MCStreamer &S);
20 };
21
22 // This part is for ascii assembly output
23 class Nios2TargetAsmStreamer : public Nios2TargetStreamer {
24 public:
25 Nios2TargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
26 };
27
28 } // namespace llvm
29 #endif
+0
-1
lib/Target/Nios2/TargetInfo/CMakeLists.txt less more
None add_llvm_library(LLVMNios2Info Nios2TargetInfo.cpp)
+0
-23
lib/Target/Nios2/TargetInfo/LLVMBuild.txt less more
None ;===- ./lib/Target/Nios2/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===;
1 ;
2 ; The LLVM Compiler Infrastructure
3 ;
4 ; This file is distributed under the University of Illinois Open Source
5 ; License. See LICENSE.TXT for details.
6 ;
7 ;===------------------------------------------------------------------------===;
8 ;
9 ; This is an LLVMBuild description file for the components in this subdirectory.
10 ;
11 ; For more information on the LLVMBuild system, please see:
12 ;
13 ; http://llvm.org/docs/LLVMBuild.html
14 ;
15 ;===------------------------------------------------------------------------===;
16
17 [component_0]
18 type = Library
19 name = Nios2Info
20 parent = Nios2
21 required_libraries = Support
22 add_to_library_groups = Nios2
+0
-24
lib/Target/Nios2/TargetInfo/Nios2TargetInfo.cpp less more
None //===-- Nios2TargetInfo.cpp - Nios2 Target Implementation -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Nios2.h"
10 #include "llvm/Support/TargetRegistry.h"
11
12 using namespace llvm;
13
14 Target &llvm::getTheNios2Target() {
15 static Target TheNios2Target;
16 return TheNios2Target;
17 }
18
19 extern "C" void LLVMInitializeNios2TargetInfo() {
20 RegisterTarget
21 /*HasJIT=*/true>
22 X(getTheNios2Target(), "nios2", "Nios2", "Nios2");
23 }
+0
-19
test/CodeGen/Nios2/add-sub.ll less more
None ; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
1 ; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
2
3 define i32 @add_reg(i32 %a, i32 %b) nounwind {
4 entry:
5 ; CHECK: add_reg:
6 ; CHECK: add r2, r4, r5
7 %c = add i32 %a, %b
8 ret i32 %c
9 }
10
11 define i32 @sub_reg(i32 %a, i32 %b) nounwind {
12 entry:
13 ; CHECK: sub_reg:
14 ; CHECK: sub r2, r4, r5
15 %c = sub i32 %a, %b
16 ret i32 %c
17 }
18
+0
-3
test/CodeGen/Nios2/lit.local.cfg less more
None if not 'Nios2' in config.root.targets:
1 config.unsupported = True
2
+0
-27
test/CodeGen/Nios2/mul-div.ll less more
None ; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
1 ; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
2
3 define i32 @mul_reg(i32 %a, i32 %b) nounwind {
4 entry:
5 ; CHECK: mul_reg:
6 ; CHECK: mul r2, r4, r5
7 %c = mul i32 %a, %b
8 ret i32 %c
9 }
10
11 define i32 @div_signed(i32 %a, i32 %b) nounwind {
12 entry:
13 ; CHECK: div_signed:
14 ; CHECK: div r2, r4, r5
15 %c = sdiv i32 %a, %b
16 ret i32 %c
17 }
18
19 define i32 @div_unsigned(i32 %a, i32 %b) nounwind {
20 entry:
21 ; CHECK: div_unsigned:
22 ; CHECK: divu r2, r4, r5
23 %c = udiv i32 %a, %b
24 ret i32 %c
25 }
26
+0
-10
test/CodeGen/Nios2/proc_support.ll less more
None ; This tests that llc accepts Nios2 processors.
1
2 ; RUN: not not llc < %s -asm-verbose=false -march=nios2 -mcpu=nios2r1 2>&1 | FileCheck %s --check-prefix=ARCH
3 ; RUN: not not llc < %s -asm-verbose=false -march=nios2 -mcpu=nios2r2 2>&1 | FileCheck %s --check-prefix=ARCH
4
5 ; ARCH-NOT: is not a recognized processor
6
7 define i32 @f(i32 %i) {
8 ret i32 %i
9 }
+0
-9
test/CodeGen/Nios2/ret_generated.ll less more
None ; This tests that llc generates 'ret' instruction in assembly output.
1
2 ; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s --check-prefix=ARCH
3
4 ; ARCH: ret
5
6 define i32 @f(i32 %i) {
7 ret i32 %i
8 }
+0
-26
test/CodeGen/Nios2/shift-rotate.ll less more
None ; RUN: llc < %s -march=nios2 2>&1 | FileCheck %s
1 ; RUN: llc < %s -march=nios2 -target-abi=nios2r2 2>&1 | FileCheck %s
2
3 define i32 @sll_reg(i32 %a, i32 %b) nounwind {
4 entry:
5 ; CHECK: sll_reg:
6 ; CHECK: sll r2, r4, r5
7 %c = shl i32 %a, %b
8 ret i32 %c
9 }
10
11 define i32 @srl_reg(i32 %a, i32 %b) nounwind {
12 entry:
13 ; CHECK: srl_reg:
14 ; CHECK: srl r2, r4, r5
15 %c = lshr i32 %a, %b
16 ret i32 %c
17 }
18
19 define i32 @sra_reg(i32 %a, i32 %b) nounwind {
20 entry:
21 ; CHECK: sra_reg:
22 ; CHECK: sra r2, r4, r5
23 %c = ashr i32 %a, %b
24 ret i32 %c
25 }
+0
-11
test/CodeGen/Nios2/target_support.ll less more
None ; This tests that llc accepts Nios2 target.
1
2 ; RUN: not not llc < %s -asm-verbose=false -march=nios2 2>&1 | FileCheck %s --check-prefix=ARCH
3 ; RUN: not not llc < %s -asm-verbose=false -mtriple=nios2 2>&1 | FileCheck %s --check-prefix=TRIPLE
4
5 ; ARCH-NOT: invalid target
6 ; TRIPLE-NOT: unable to get target
7
8 define i32 @f(i32 %i) {
9 ret i32 %i
10 }
5757 "Targets/MSP430.cpp",
5858 "Targets/Mips.cpp",
5959 "Targets/NVPTX.cpp",
60 "Targets/Nios2.cpp",
6160 "Targets/OSTargets.cpp",
6261 "Targets/PNaCl.cpp",
6362 "Targets/PPC.cpp",