llvm.org GIT mirror llvm / 171049d
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24997 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
10 changed file(s) with 77 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
4545 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
4646 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
4747
48 def SDT_PPCRetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
48 def SDT_PPCRetFlag : SDTypeProfile<0, 0, []>;
4949 def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag, [SDNPHasChain]>;
5050
5151 //===----------------------------------------------------------------------===//
222222
223223
224224 let isTerminator = 1 in {
225 // FIXME: temporary workaround for return without an incoming flag.
225226 let isReturn = 1 in
226 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(ret)]>;
227 def BLRVOID : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(ret)]>;
228 let isReturn = 1, hasInFlag = 1 in
229 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, []>;
227230 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
228231 }
229232
10551058 def : Pat<(f64 (extload xaddr:$src, f32)),
10561059 (FMRSD (LFSX xaddr:$src))>;
10571060
1058 def : Pat<(retflag FLAG), (BLR)>;
1061 def : Pat<(retflag), (BLR)>;
10591062
10601063 // Same as above, but using a temporary. FIXME: implement temporaries :)
10611064 /*
372372 const MachineFrameInfo *MFI = MF.getFrameInfo();
373373 MachineBasicBlock::iterator MBBI = prior(MBB.end());
374374 MachineInstr *MI;
375 assert(MBBI->getOpcode() == PPC::BLR &&
375 // FIXME: BLRVOID should be removed. See PPCInstrInfo.td
376 assert((MBBI->getOpcode() == PPC::BLR || MBBI->getOpcode() == PPC::BLRVOID) &&
376377 "Can only insert epilog into returning blocks");
377378
378379 // Get the number of bytes allocated from the FrameInfo...
9292 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
9393 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
9494
95 def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
96 SDTCisVT<2, FlagVT>]>;
95 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
9796 def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
9897
99 def SDT_V8RetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
98 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
10099 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
101100
102101 //===----------------------------------------------------------------------===//
173172 // special cases of JMPL:
174173 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
175174 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
176 def RETL: F3_2<2, 0b111000, (ops),
177 "retl", [(ret)]>;
175 // FIXME: temporary workaround for return without an incoming flag.
176 def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
177 let hasInFlag = 1 in
178 def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
178179 }
179180
180181 // Section B.1 - Load Integer Instructions, p. 90
558559
559560 // Section B.24 - Call and Link Instruction, p. 125
560561 // This is the only Format 1 instruction
561 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
562 let Uses = [O0, O1, O2, O3, O4, O5],
563 hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1,
562564 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
563565 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
564 // pc-relative call:
565566 def CALL : InstV8<(ops calltarget:$dst),
566 "call $dst",
567 [(set FLAG, (call tglobaladdr:$dst, FLAG))]> {
567 "call $dst", []> {
568568 bits<30> disp;
569569 let op = 1;
570570 let Inst{29-0} = disp;
571571 }
572
572
573573 // indirect calls
574574 def JMPLrr : F3_1<2, 0b111000,
575575 (ops MEMrr:$ptr),
576576 "call $ptr",
577 [(set FLAG, (call ADDRrr:$ptr, FLAG))]>;
577 [(call ADDRrr:$ptr)]>;
578578 def JMPLri : F3_2<2, 0b111000,
579579 (ops MEMri:$ptr),
580580 "call $ptr",
581 [(set FLAG, (call ADDRri:$ptr, FLAG))]>;
581 [(call ADDRri:$ptr)]>;
582582 }
583583
584584 // Section B.28 - Read State Register Instructions
723723 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
724724
725725 // Return of a value, which has an input flag.
726 def : Pat<(retflag FLAG), (RETL)>;
726 def : Pat<(retflag), (RETL)>;
727
728
729 // Calls:
730 def : Pat<(call tglobaladdr:$dst),
731 (CALL tglobaladdr:$dst)>;
732 def : Pat<(call externalsym:$dst),
733 (CALL externalsym:$dst)>;
734
727735
728736 // Map integer extload's to zextloads.
729737 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
164164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
165165 MachineBasicBlock &MBB) const {
166166 MachineBasicBlock::iterator MBBI = prior(MBB.end());
167 assert(MBBI->getOpcode() == V8::RETL &&
167 // FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
168 assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
168169 "Can only put epilog before 'retl' instruction!");
169170 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
170171 }
9292 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
9393 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
9494
95 def SDT_V8Call : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisVT<1, i32>,
96 SDTCisVT<2, FlagVT>]>;
95 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
9796 def call : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
9897
99 def SDT_V8RetFlag : SDTypeProfile<0, 1, [ SDTCisVT<0, FlagVT>]>;
98 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
10099 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
101100
102101 //===----------------------------------------------------------------------===//
173172 // special cases of JMPL:
174173 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
175174 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
176 def RETL: F3_2<2, 0b111000, (ops),
177 "retl", [(ret)]>;
175 // FIXME: temporary workaround for return without an incoming flag.
176 def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
177 let hasInFlag = 1 in
178 def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
178179 }
179180
180181 // Section B.1 - Load Integer Instructions, p. 90
558559
559560 // Section B.24 - Call and Link Instruction, p. 125
560561 // This is the only Format 1 instruction
561 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1,
562 let Uses = [O0, O1, O2, O3, O4, O5],
563 hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1,
562564 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
563565 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
564 // pc-relative call:
565566 def CALL : InstV8<(ops calltarget:$dst),
566 "call $dst",
567 [(set FLAG, (call tglobaladdr:$dst, FLAG))]> {
567 "call $dst", []> {
568568 bits<30> disp;
569569 let op = 1;
570570 let Inst{29-0} = disp;
571571 }
572
572
573573 // indirect calls
574574 def JMPLrr : F3_1<2, 0b111000,
575575 (ops MEMrr:$ptr),
576576 "call $ptr",
577 [(set FLAG, (call ADDRrr:$ptr, FLAG))]>;
577 [(call ADDRrr:$ptr)]>;
578578 def JMPLri : F3_2<2, 0b111000,
579579 (ops MEMri:$ptr),
580580 "call $ptr",
581 [(set FLAG, (call ADDRri:$ptr, FLAG))]>;
581 [(call ADDRri:$ptr)]>;
582582 }
583583
584584 // Section B.28 - Read State Register Instructions
723723 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
724724
725725 // Return of a value, which has an input flag.
726 def : Pat<(retflag FLAG), (RETL)>;
726 def : Pat<(retflag), (RETL)>;
727
728
729 // Calls:
730 def : Pat<(call tglobaladdr:$dst),
731 (CALL tglobaladdr:$dst)>;
732 def : Pat<(call externalsym:$dst),
733 (CALL externalsym:$dst)>;
734
727735
728736 // Map integer extload's to zextloads.
729737 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
164164 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
165165 MachineBasicBlock &MBB) const {
166166 MachineBasicBlock::iterator MBBI = prior(MBB.end());
167 assert(MBBI->getOpcode() == V8::RETL &&
167 // FIXME: RETVOID should be removed. See SparcV8InstrInfo.td
168 assert((MBBI->getOpcode() == V8::RETL || MBBI->getOpcode() == V8::RETVOID) &&
168169 "Can only put epilog before 'retl' instruction!");
169170 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
170171 }
168168 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
169169 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
170170 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
171 bit hasInFlag = 0; // Does this instruction read a flag operand?
172 bit hasOutFlag = 0; // Does this instruction write a flag operand?
171173
172174 InstrItinClass Itinerary; // Execution steps used for scheduling.
173175 }
183183 def set;
184184 def node;
185185 def srcvalue;
186 def FLAG;
187186
188187 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
189188 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
3131 [SDTCisVT<0, i8>, SDTCisVT<1, OtherVT>,
3232 SDTCisVT<2, FlagVT>]>;
3333
34 def SDTX86RetFlag : SDTypeProfile<0, 2, [SDTCisVT<0, i16>,
35 SDTCisVT<1, FlagVT>]>;
34 def SDTX86RetFlag : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
3635
3736 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
3837 SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
3938
40 def SDTX86FpSet : SDTypeProfile<1, 1, [SDTCisVT<0, FlagVT>, SDTCisFP<1>]>;
39 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
4140
4241 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
4342 def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
4645 def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
4746 def X86SetCC : SDNode<"X86ISD::SETCC", SDTX86SetCC, []>;
4847
49 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
48 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86RetFlag, [SDNPHasChain]>;
5049
5150 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, [SDNPHasChain]>;
5251
289288 //
290289
291290 // Return instructions.
292 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
293 def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
294 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in
295 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
296
297 def : Pat<(X86retflag 0, FLAG), (RET)>;
298 def : Pat<(X86retflag imm:$amt, FLAG), (RETI imm:$amt)>;
291 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
292 // FIXME: temporary workaround for return without an incoming flag.
293 def RETVOID : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
294 let hasInFlag = 1 in {
295 def RET : I<0xC3, RawFrm, (ops), "ret", []>;
296 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
297 }
298 }
299
300 def : Pat<(X86retflag 0), (RET)>;
301 def : Pat<(X86retflag imm:$amt), (RETI imm:$amt)>;
299302
300303 // All branches are RawFrm, Void, Branch, and Terminators
301304 let isBranch = 1, isTerminator = 1 in
23112314 }
23122315
23132316 // Random Pseudo Instructions.
2314 def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, // FPR = ST(0)
2315 []>;
2316 def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
2317 [(set FLAG, (X86fpset RFP:$src))]>,
2318 Imp<[], [ST0]>; // ST(0) = FPR
2319
2320 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP,
2321 []>; // f1 = fmov f2
2317 def FpGETRESULT : FpPseudoI<(ops RFP:$dst), SpecialFP, []>; // FPR = ST(0)
2318 let hasOutFlag = 1 in
2319 def FpSETRESULT : FpPseudoI<(ops RFP:$src), SpecialFP,
2320 [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
2321
2322 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
23222323
23232324 // Arithmetic
2324
23252325 // Add, Sub, Mul, Div.
23262326 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
23272327 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
567567 switch (MBBI->getOpcode()) {
568568 case X86::RET:
569569 case X86::RETI:
570 case X86::RETVOID: // FIXME: See X86InstrInfo.td
570571 case X86::TAILJMPd:
571572 case X86::TAILJMPr:
572573 case X86::TAILJMPm: break; // These are ok