llvm.org GIT mirror llvm / 1704eb6
[AMDGPU] refactor DS instruction definitions. NFC. Differential revision: https://reviews.llvm.org/D22522 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277344 91177308-0d34-0410-b5e6-96231b3b80d8 Valery Pykhtin 4 years ago
9 changed file(s) with 908 addition(s) and 628 deletion(s). Raw diff Collapse all Expand all
1212 // S_CBRANCH_CDBGSYS
1313 // S_CBRANCH_CDBGSYS_OR_USER
1414 // S_CBRANCH_CDBGSYS_AND_USER
15 // DS_NOP
16 // DS_GWS_SEMA_RELEASE_ALL
17 // DS_WRAP_RTN_B32
18 // DS_CNDXCHG32_RTN_B64
19 // DS_WRITE_B96
20 // DS_WRITE_B128
21 // DS_CONDXCHG32_RTN_B128
22 // DS_READ_B96
23 // DS_READ_B128
2415 // BUFFER_LOAD_DWORDX3
2516 // BUFFER_STORE_DWORDX3
2617
7970 >;
8071 } // End isCommutable = 1
8172
82
83 //===----------------------------------------------------------------------===//
84 // DS Instructions
85 //===----------------------------------------------------------------------===//
86 defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">;
87
88 // DS_CONDXCHG32_RTN_B64
89 // DS_CONDXCHG32_RTN_B128
9073
9174 //===----------------------------------------------------------------------===//
9275 // SMRD Instructions
0 //===-- DSInstructions.td - DS Instruction Defintions ---------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 class DS_Pseudo pattern=[]> :
10 InstSI ,
11 SIMCInstr {
12
13 let SubtargetPredicate = isGCN;
14
15 let LGKM_CNT = 1;
16 let DS = 1;
17 let UseNamedOperandTable = 1;
18 let Uses = [M0, EXEC];
19
20 // Most instruction load and store data, so set this as the default.
21 let mayLoad = 1;
22 let mayStore = 1;
23
24 let hasSideEffects = 0;
25 let SchedRW = [WriteLDS];
26
27 let isPseudo = 1;
28 let isCodeGenOnly = 1;
29
30 let AsmMatchConverter = "cvtDS";
31
32 string Mnemonic = opName;
33 string AsmOperands = asmOps;
34
35 // Well these bits a kind of hack because it would be more natural
36 // to test "outs" and "ins" dags for the presence of particular operands
37 bits<1> has_vdst = 1;
38 bits<1> has_addr = 1;
39 bits<1> has_data0 = 1;
40 bits<1> has_data1 = 1;
41
42 bits<1> has_offset = 1; // has "offset" that should be split to offset0,1
43 bits<1> has_offset0 = 1;
44 bits<1> has_offset1 = 1;
45
46 bits<1> has_gds = 1;
47 bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
48 }
49
50 class DS_Real :
51 InstSI ,
52 Enc64 {
53
54 let isPseudo = 0;
55 let isCodeGenOnly = 0;
56
57 // copy relevant pseudo op flags
58 let SubtargetPredicate = ds.SubtargetPredicate;
59 let AsmMatchConverter = ds.AsmMatchConverter;
60
61 // encoding fields
62 bits<8> vdst;
63 bits<1> gds;
64 bits<8> addr;
65 bits<8> data0;
66 bits<8> data1;
67 bits<8> offset0;
68 bits<8> offset1;
69
70 bits<16> offset;
71 let offset0 = !if(ds.has_offset, offset{7-0}, ?);
72 let offset1 = !if(ds.has_offset, offset{15-8}, ?);
73 }
74
75
76 // DS Pseudo instructions
77
78 class DS_1A1D_NORET
79 : DS_Pseudo
80 (outs),
81 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
82 "$addr, $data0$offset$gds">,
83 AtomicNoRet {
84
85 let has_data1 = 0;
86 let has_vdst = 0;
87 }
88
89 class DS_1A_Off8_NORET : DS_Pseudo
90 (outs),
91 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
92 "$addr $offset0$offset1$gds"> {
93
94 let has_data0 = 0;
95 let has_data1 = 0;
96 let has_vdst = 0;
97 let has_offset = 0;
98 let AsmMatchConverter = "cvtDSOffset01";
99 }
100
101 class DS_1A2D_NORET
102 : DS_Pseudo
103 (outs),
104 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
105 "$addr, $data0, $data1"#"$offset"#"$gds">,
106 AtomicNoRet {
107
108 let has_vdst = 0;
109 }
110
111 class DS_1A2D_Off8_NORET
112 : DS_Pseudo
113 (outs),
114 (ins VGPR_32:$addr, rc:$data0, rc:$data1,
115 offset0:$offset0, offset1:$offset1, gds:$gds),
116 "$addr, $data0, $data1$offset0$offset1$gds"> {
117
118 let has_vdst = 0;
119 let has_offset = 0;
120 let AsmMatchConverter = "cvtDSOffset01";
121 }
122
123 class DS_1A1D_RET
124 : DS_Pseudo
125 (outs rc:$vdst),
126 (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
127 "$vdst, $addr, $data0$offset$gds"> {
128
129 let hasPostISelHook = 1;
130 let has_data1 = 0;
131 }
132
133 class DS_1A2D_RET
134 RegisterClass rc = VGPR_32,
135 RegisterClass src = rc>
136 : DS_Pseudo
137 (outs rc:$vdst),
138 (ins VGPR_32:$addr, src:$data0, src:$data1, offset:$offset, gds:$gds),
139 "$vdst, $addr, $data0, $data1$offset$gds"> {
140
141 let hasPostISelHook = 1;
142 }
143
144 class DS_1A_RET
145 : DS_Pseudo
146 (outs rc:$vdst),
147 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
148 "$vdst, $addr$offset$gds"> {
149
150 let has_data0 = 0;
151 let has_data1 = 0;
152 }
153
154 class DS_1A_Off8_RET
155 : DS_Pseudo
156 (outs rc:$vdst),
157 (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
158 "$vdst, $addr$offset0$offset1$gds"> {
159
160 let has_offset = 0;
161 let has_data0 = 0;
162 let has_data1 = 0;
163 let AsmMatchConverter = "cvtDSOffset01";
164 }
165
166 class DS_1A_RET_GDS : DS_Pseudo
167 (outs VGPR_32:$vdst),
168 (ins VGPR_32:$addr, offset:$offset),
169 "$vdst, $addr$offset gds"> {
170
171 let has_data0 = 0;
172 let has_data1 = 0;
173 let has_gds = 0;
174 let gdsValue = 1;
175 }
176
177 class DS_0A_RET : DS_Pseudo
178 (outs VGPR_32:$vdst),
179 (ins offset:$offset, gds:$gds),
180 "$vdst$offset$gds"> {
181
182 let mayLoad = 1;
183 let mayStore = 1;
184
185 let has_addr = 0;
186 let has_data0 = 0;
187 let has_data1 = 0;
188 }
189
190 class DS_1A : DS_Pseudo
191 (outs),
192 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
193 "$addr$offset$gds"> {
194
195 let mayLoad = 1;
196 let mayStore = 1;
197
198 let has_vdst = 0;
199 let has_data0 = 0;
200 let has_data1 = 0;
201 }
202
203 class DS_1A_GDS : DS_Pseudo
204 (outs),
205 (ins VGPR_32:$addr),
206 "$addr gds"> {
207
208 let has_vdst = 0;
209 let has_data0 = 0;
210 let has_data1 = 0;
211 let has_offset = 0;
212 let has_offset0 = 0;
213 let has_offset1 = 0;
214
215 let has_gds = 0;
216 let gdsValue = 1;
217 }
218
219 class DS_1A1D_PERMUTE
220 : DS_Pseudo
221 (outs VGPR_32:$vdst),
222 (ins VGPR_32:$addr, VGPR_32:$data0, offset:$offset),
223 "$vdst, $addr, $data0$offset",
224 [(set i32:$vdst,
225 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
226
227 let mayLoad = 0;
228 let mayStore = 0;
229 let isConvergent = 1;
230
231 let has_data1 = 0;
232 let has_gds = 0;
233 }
234
235 def DS_ADD_U32 : DS_1A1D_NORET<"ds_add_u32">;
236 def DS_SUB_U32 : DS_1A1D_NORET<"ds_sub_u32">;
237 def DS_RSUB_U32 : DS_1A1D_NORET<"ds_rsub_u32">;
238 def DS_INC_U32 : DS_1A1D_NORET<"ds_inc_u32">;
239 def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
240 def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
241 def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
242 def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
243 def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
244 def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
245 def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
246 def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
247
248 let mayLoad = 0 in {
249 def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
250 def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
251 def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
252 def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
253 def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
254 }
255
256 def DS_MSKOR_B32 : DS_1A2D_NORET<"ds_mskor_b32">;
257 def DS_CMPST_B32 : DS_1A2D_NORET<"ds_cmpst_b32">;
258 def DS_CMPST_F32 : DS_1A2D_NORET<"ds_cmpst_f32">;
259 def DS_MIN_F32 : DS_1A2D_NORET<"ds_min_f32">;
260 def DS_MAX_F32 : DS_1A2D_NORET<"ds_max_f32">;
261
262 def DS_ADD_U64 : DS_1A1D_NORET<"ds_add_u64", VReg_64>;
263 def DS_SUB_U64 : DS_1A1D_NORET<"ds_sub_u64", VReg_64>;
264 def DS_RSUB_U64 : DS_1A1D_NORET<"ds_rsub_u64", VReg_64>;
265 def DS_INC_U64 : DS_1A1D_NORET<"ds_inc_u64", VReg_64>;
266 def DS_DEC_U64 : DS_1A1D_NORET<"ds_dec_u64", VReg_64>;
267 def DS_MIN_I64 : DS_1A1D_NORET<"ds_min_i64", VReg_64>;
268 def DS_MAX_I64 : DS_1A1D_NORET<"ds_max_i64", VReg_64>;
269 def DS_MIN_U64 : DS_1A1D_NORET<"ds_min_u64", VReg_64>;
270 def DS_MAX_U64 : DS_1A1D_NORET<"ds_max_u64", VReg_64>;
271 def DS_AND_B64 : DS_1A1D_NORET<"ds_and_b64", VReg_64>;
272 def DS_OR_B64 : DS_1A1D_NORET<"ds_or_b64", VReg_64>;
273 def DS_XOR_B64 : DS_1A1D_NORET<"ds_xor_b64", VReg_64>;
274 def DS_MSKOR_B64 : DS_1A2D_NORET<"ds_mskor_b64", VReg_64>;
275 let mayLoad = 0 in {
276 def DS_WRITE_B64 : DS_1A1D_NORET<"ds_write_b64", VReg_64>;
277 def DS_WRITE2_B64 : DS_1A2D_Off8_NORET<"ds_write2_b64", VReg_64>;
278 def DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET<"ds_write2st64_b64", VReg_64>;
279 }
280 def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
281 def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
282 def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
283 def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
284
285 def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
286 AtomicNoRet<"ds_add_u32", 1>;
287 def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
288 AtomicNoRet<"ds_sub_u32", 1>;
289 def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
290 AtomicNoRet<"ds_rsub_u32", 1>;
291 def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
292 AtomicNoRet<"ds_inc_u32", 1>;
293 def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
294 AtomicNoRet<"ds_dec_u32", 1>;
295 def DS_MIN_RTN_I32 : DS_1A1D_RET<"ds_min_rtn_i32">,
296 AtomicNoRet<"ds_min_i32", 1>;
297 def DS_MAX_RTN_I32 : DS_1A1D_RET<"ds_max_rtn_i32">,
298 AtomicNoRet<"ds_max_i32", 1>;
299 def DS_MIN_RTN_U32 : DS_1A1D_RET<"ds_min_rtn_u32">,
300 AtomicNoRet<"ds_min_u32", 1>;
301 def DS_MAX_RTN_U32 : DS_1A1D_RET<"ds_max_rtn_u32">,
302 AtomicNoRet<"ds_max_u32", 1>;
303 def DS_AND_RTN_B32 : DS_1A1D_RET<"ds_and_rtn_b32">,
304 AtomicNoRet<"ds_and_b32", 1>;
305 def DS_OR_RTN_B32 : DS_1A1D_RET<"ds_or_rtn_b32">,
306 AtomicNoRet<"ds_or_b32", 1>;
307 def DS_XOR_RTN_B32 : DS_1A1D_RET<"ds_xor_rtn_b32">,
308 AtomicNoRet<"ds_xor_b32", 1>;
309 def DS_MSKOR_RTN_B32 : DS_1A2D_RET<"ds_mskor_rtn_b32">,
310 AtomicNoRet<"ds_mskor_b32", 1>;
311 def DS_CMPST_RTN_B32 : DS_1A2D_RET <"ds_cmpst_rtn_b32">,
312 AtomicNoRet<"ds_cmpst_b32", 1>;
313 def DS_CMPST_RTN_F32 : DS_1A2D_RET <"ds_cmpst_rtn_f32">,
314 AtomicNoRet<"ds_cmpst_f32", 1>;
315 def DS_MIN_RTN_F32 : DS_1A2D_RET <"ds_min_rtn_f32">,
316 AtomicNoRet<"ds_min_f32", 1>;
317 def DS_MAX_RTN_F32 : DS_1A2D_RET <"ds_max_rtn_f32">,
318 AtomicNoRet<"ds_max_f32", 1>;
319
320 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET<"ds_wrxchg_rtn_b32">,
321 AtomicNoRet<"", 1>;
322 def DS_WRXCHG2_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>,
323 AtomicNoRet<"", 1>;
324 def DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>,
325 AtomicNoRet<"", 1>;
326
327 def DS_ADD_RTN_U64 : DS_1A1D_RET<"ds_add_rtn_u64", VReg_64>,
328 AtomicNoRet<"ds_add_u64", 1>;
329 def DS_SUB_RTN_U64 : DS_1A1D_RET<"ds_sub_rtn_u64", VReg_64>,
330 AtomicNoRet<"ds_sub_u64", 1>;
331 def DS_RSUB_RTN_U64 : DS_1A1D_RET<"ds_rsub_rtn_u64", VReg_64>,
332 AtomicNoRet<"ds_rsub_u64", 1>;
333 def DS_INC_RTN_U64 : DS_1A1D_RET<"ds_inc_rtn_u64", VReg_64>,
334 AtomicNoRet<"ds_inc_u64", 1>;
335 def DS_DEC_RTN_U64 : DS_1A1D_RET<"ds_dec_rtn_u64", VReg_64>,
336 AtomicNoRet<"ds_dec_u64", 1>;
337 def DS_MIN_RTN_I64 : DS_1A1D_RET<"ds_min_rtn_i64", VReg_64>,
338 AtomicNoRet<"ds_min_i64", 1>;
339 def DS_MAX_RTN_I64 : DS_1A1D_RET<"ds_max_rtn_i64", VReg_64>,
340 AtomicNoRet<"ds_max_i64", 1>;
341 def DS_MIN_RTN_U64 : DS_1A1D_RET<"ds_min_rtn_u64", VReg_64>,
342 AtomicNoRet<"ds_min_u64", 1>;
343 def DS_MAX_RTN_U64 : DS_1A1D_RET<"ds_max_rtn_u64", VReg_64>,
344 AtomicNoRet<"ds_max_u64", 1>;
345 def DS_AND_RTN_B64 : DS_1A1D_RET<"ds_and_rtn_b64", VReg_64>,
346 AtomicNoRet<"ds_and_b64", 1>;
347 def DS_OR_RTN_B64 : DS_1A1D_RET<"ds_or_rtn_b64", VReg_64>,
348 AtomicNoRet<"ds_or_b64", 1>;
349 def DS_XOR_RTN_B64 : DS_1A1D_RET<"ds_xor_rtn_b64", VReg_64>,
350 AtomicNoRet<"ds_xor_b64", 1>;
351 def DS_MSKOR_RTN_B64 : DS_1A2D_RET<"ds_mskor_rtn_b64", VReg_64>,
352 AtomicNoRet<"ds_mskor_b64", 1>;
353 def DS_CMPST_RTN_B64 : DS_1A2D_RET<"ds_cmpst_rtn_b64", VReg_64>,
354 AtomicNoRet<"ds_cmpst_b64", 1>;
355 def DS_CMPST_RTN_F64 : DS_1A2D_RET<"ds_cmpst_rtn_f64", VReg_64>,
356 AtomicNoRet<"ds_cmpst_f64", 1>;
357 def DS_MIN_RTN_F64 : DS_1A1D_RET<"ds_min_rtn_f64", VReg_64>,
358 AtomicNoRet<"ds_min_f64", 1>;
359 def DS_MAX_RTN_F64 : DS_1A1D_RET<"ds_max_rtn_f64", VReg_64>,
360 AtomicNoRet<"ds_max_f64", 1>;
361
362 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET<"ds_wrxchg_rtn_b64", VReg_64>,
363 AtomicNoRet<"ds_wrxchg_b64", 1>;
364 def DS_WRXCHG2_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>,
365 AtomicNoRet<"ds_wrxchg2_b64", 1>;
366 def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
367 AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
368
369 def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">;
370 def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">;
371 def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">;
372 def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">;
373 def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">;
374
375 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
376 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
377 def DS_RSUB_SRC2_U32 : DS_1A<"ds_rsub_src2_u32">;
378 def DS_INC_SRC2_U32 : DS_1A<"ds_inc_src2_u32">;
379 def DS_DEC_SRC2_U32 : DS_1A<"ds_dec_src2_u32">;
380 def DS_MIN_SRC2_I32 : DS_1A<"ds_min_src2_i32">;
381 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
382 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
383 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
384 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">;
385 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
386 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
387 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
388 def DS_MAX_SRC2_F32 : DS_1A<"ds_max_src2_f32">;
389
390 def DS_ADD_SRC2_U64 : DS_1A<"ds_add_src2_u64">;
391 def DS_SUB_SRC2_U64 : DS_1A<"ds_sub_src2_u64">;
392 def DS_RSUB_SRC2_U64 : DS_1A<"ds_rsub_src2_u64">;
393 def DS_INC_SRC2_U64 : DS_1A<"ds_inc_src2_u64">;
394 def DS_DEC_SRC2_U64 : DS_1A<"ds_dec_src2_u64">;
395 def DS_MIN_SRC2_I64 : DS_1A<"ds_min_src2_i64">;
396 def DS_MAX_SRC2_I64 : DS_1A<"ds_max_src2_i64">;
397 def DS_MIN_SRC2_U64 : DS_1A<"ds_min_src2_u64">;
398 def DS_MAX_SRC2_U64 : DS_1A<"ds_max_src2_u64">;
399 def DS_AND_SRC2_B64 : DS_1A<"ds_and_src2_b64">;
400 def DS_OR_SRC2_B64 : DS_1A<"ds_or_src2_b64">;
401 def DS_XOR_SRC2_B64 : DS_1A<"ds_xor_src2_b64">;
402 def DS_MIN_SRC2_F64 : DS_1A<"ds_min_src2_f64">;
403 def DS_MAX_SRC2_F64 : DS_1A<"ds_max_src2_f64">;
404
405 def DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET<"ds_write_src2_b32">;
406 def DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET<"ds_write_src2_b64">;
407
408 let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
409 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32">;
410 }
411
412 let mayStore = 0 in {
413 def DS_READ_I8 : DS_1A_RET<"ds_read_i8">;
414 def DS_READ_U8 : DS_1A_RET<"ds_read_u8">;
415 def DS_READ_I16 : DS_1A_RET<"ds_read_i16">;
416 def DS_READ_U16 : DS_1A_RET<"ds_read_u16">;
417 def DS_READ_B32 : DS_1A_RET<"ds_read_b32">;
418 def DS_READ_B64 : DS_1A_RET<"ds_read_b64", VReg_64>;
419
420 def DS_READ2_B32 : DS_1A_Off8_RET<"ds_read2_b32", VReg_64>;
421 def DS_READ2ST64_B32 : DS_1A_Off8_RET<"ds_read2st64_b32", VReg_64>;
422
423 def DS_READ2_B64 : DS_1A_Off8_RET<"ds_read2_b64", VReg_128>;
424 def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
425 }
426
427 let SubtargetPredicate = isSICI in {
428 def DS_CONSUME : DS_0A_RET<"ds_consume">;
429 def DS_APPEND : DS_0A_RET<"ds_append">;
430 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
431 }
432
433 //===----------------------------------------------------------------------===//
434 // Instruction definitions for CI and newer.
435 //===----------------------------------------------------------------------===//
436 // Remaining instructions:
437 // DS_NOP
438 // DS_GWS_SEMA_RELEASE_ALL
439 // DS_WRAP_RTN_B32
440 // DS_CNDXCHG32_RTN_B64
441 // DS_WRITE_B96
442 // DS_WRITE_B128
443 // DS_CONDXCHG32_RTN_B128
444 // DS_READ_B96
445 // DS_READ_B128
446
447 let SubtargetPredicate = isCIVI in {
448
449 def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
450 AtomicNoRet<"ds_wrap_f32", 1>;
451
452 } // let SubtargetPredicate = isCIVI
453
454 //===----------------------------------------------------------------------===//
455 // Instruction definitions for VI and newer.
456 //===----------------------------------------------------------------------===//
457
458 let SubtargetPredicate = isVI in {
459
460 let Uses = [EXEC] in {
461 def DS_PERMUTE_B32 : DS_1A1D_PERMUTE <"ds_permute_b32",
462 int_amdgcn_ds_permute>;
463 def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
464 int_amdgcn_ds_bpermute>;
465 }
466
467 } // let SubtargetPredicate = isVI
468
469 //===----------------------------------------------------------------------===//
470 // DS Patterns
471 //===----------------------------------------------------------------------===//
472
473 let Predicates = [isGCN] in {
474
475 def : Pat <
476 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
477 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
478 >;
479
480 class DSReadPat : Pat <
481 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
482 (inst $ptr, (as_i16imm $offset), (i1 0))
483 >;
484
485 def : DSReadPat ;
486 def : DSReadPat ;
487 def : DSReadPat ;
488 def : DSReadPat ;
489 def : DSReadPat ;
490
491 let AddedComplexity = 100 in {
492
493 def : DSReadPat ;
494
495 } // End AddedComplexity = 100
496
497 def : Pat <
498 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
499 i8:$offset1))),
500 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
501 >;
502
503 class DSWritePat : Pat <
504 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
505 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
506 >;
507
508 def : DSWritePat ;
509 def : DSWritePat ;
510 def : DSWritePat ;
511
512 let AddedComplexity = 100 in {
513
514 def : DSWritePat ;
515 } // End AddedComplexity = 100
516
517 def : Pat <
518 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
519 i8:$offset1)),
520 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0),
521 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1,
522 (i1 0))
523 >;
524
525 class DSAtomicRetPat : Pat <
526 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
527 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
528 >;
529
530 class DSAtomicCmpXChg : Pat <
531 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
532 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
533 >;
534
535
536 // 32-bit atomics.
537 def : DSAtomicRetPat;
538 def : DSAtomicRetPat;
539 def : DSAtomicRetPat;
540 def : DSAtomicRetPat;
541 def : DSAtomicRetPat;
542 def : DSAtomicRetPat;
543 def : DSAtomicRetPat;
544 def : DSAtomicRetPat;
545 def : DSAtomicRetPat;
546 def : DSAtomicRetPat;
547 def : DSAtomicRetPat;
548 def : DSAtomicRetPat;
549 def : DSAtomicCmpXChg;
550
551 // 64-bit atomics.
552 def : DSAtomicRetPat;
553 def : DSAtomicRetPat;
554 def : DSAtomicRetPat;
555 def : DSAtomicRetPat;
556 def : DSAtomicRetPat;
557 def : DSAtomicRetPat;
558 def : DSAtomicRetPat;
559 def : DSAtomicRetPat;
560 def : DSAtomicRetPat;
561 def : DSAtomicRetPat;
562 def : DSAtomicRetPat;
563 def : DSAtomicRetPat;
564
565 def : DSAtomicCmpXChg;
566
567 } // let Predicates = [isGCN]
568
569 //===----------------------------------------------------------------------===//
570 // Real instructions
571 //===----------------------------------------------------------------------===//
572
573 //===----------------------------------------------------------------------===//
574 // SIInstructions.td
575 //===----------------------------------------------------------------------===//
576
577 class DS_Real_si op, DS_Pseudo ds> :
578 DS_Real ,
579 SIMCInstr {
580 let AssemblerPredicates=[isSICI];
581 let DecoderNamespace="SICI";
582
583 // encoding
584 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
585 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
586 let Inst{17} = !if(ds.has_gds, gds, ds.gdsValue);
587 let Inst{25-18} = op;
588 let Inst{31-26} = 0x36; // ds prefix
589 let Inst{39-32} = !if(ds.has_addr, addr, 0);
590 let Inst{47-40} = !if(ds.has_data0, data0, 0);
591 let Inst{55-48} = !if(ds.has_data1, data1, 0);
592 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
593 }
594
595 def DS_ADD_U32_si : DS_Real_si<0x0, DS_ADD_U32>;
596 def DS_SUB_U32_si : DS_Real_si<0x1, DS_SUB_U32>;
597 def DS_RSUB_U32_si : DS_Real_si<0x2, DS_RSUB_U32>;
598 def DS_INC_U32_si : DS_Real_si<0x3, DS_INC_U32>;
599 def DS_DEC_U32_si : DS_Real_si<0x4, DS_DEC_U32>;
600 def DS_MIN_I32_si : DS_Real_si<0x5, DS_MIN_I32>;
601 def DS_MAX_I32_si : DS_Real_si<0x6, DS_MAX_I32>;
602 def DS_MIN_U32_si : DS_Real_si<0x7, DS_MIN_U32>;
603 def DS_MAX_U32_si : DS_Real_si<0x8, DS_MAX_U32>;
604 def DS_AND_B32_si : DS_Real_si<0x9, DS_AND_B32>;
605 def DS_OR_B32_si : DS_Real_si<0xa, DS_OR_B32>;
606 def DS_XOR_B32_si : DS_Real_si<0xb, DS_XOR_B32>;
607 def DS_MSKOR_B32_si : DS_Real_si<0xc, DS_MSKOR_B32>;
608 def DS_WRITE_B32_si : DS_Real_si<0xd, DS_WRITE_B32>;
609 def DS_WRITE2_B32_si : DS_Real_si<0xe, DS_WRITE2_B32>;
610 def DS_WRITE2ST64_B32_si : DS_Real_si<0xf, DS_WRITE2ST64_B32>;
611 def DS_CMPST_B32_si : DS_Real_si<0x10, DS_CMPST_B32>;
612 def DS_CMPST_F32_si : DS_Real_si<0x11, DS_CMPST_F32>;
613 def DS_MIN_F32_si : DS_Real_si<0x12, DS_MIN_F32>;
614 def DS_MAX_F32_si : DS_Real_si<0x13, DS_MAX_F32>;
615 def DS_GWS_INIT_si : DS_Real_si<0x19, DS_GWS_INIT>;
616 def DS_GWS_SEMA_V_si : DS_Real_si<0x1a, DS_GWS_SEMA_V>;
617 def DS_GWS_SEMA_BR_si : DS_Real_si<0x1b, DS_GWS_SEMA_BR>;
618 def DS_GWS_SEMA_P_si : DS_Real_si<0x1c, DS_GWS_SEMA_P>;
619 def DS_GWS_BARRIER_si : DS_Real_si<0x1d, DS_GWS_BARRIER>;
620 def DS_WRITE_B8_si : DS_Real_si<0x1e, DS_WRITE_B8>;
621 def DS_WRITE_B16_si : DS_Real_si<0x1f, DS_WRITE_B16>;
622 def DS_ADD_RTN_U32_si : DS_Real_si<0x20, DS_ADD_RTN_U32>;
623 def DS_SUB_RTN_U32_si : DS_Real_si<0x21, DS_SUB_RTN_U32>;
624 def DS_RSUB_RTN_U32_si : DS_Real_si<0x22, DS_RSUB_RTN_U32>;
625 def DS_INC_RTN_U32_si : DS_Real_si<0x23, DS_INC_RTN_U32>;
626 def DS_DEC_RTN_U32_si : DS_Real_si<0x24, DS_DEC_RTN_U32>;
627 def DS_MIN_RTN_I32_si : DS_Real_si<0x25, DS_MIN_RTN_I32>;
628 def DS_MAX_RTN_I32_si : DS_Real_si<0x26, DS_MAX_RTN_I32>;
629 def DS_MIN_RTN_U32_si : DS_Real_si<0x27, DS_MIN_RTN_U32>;
630 def DS_MAX_RTN_U32_si : DS_Real_si<0x28, DS_MAX_RTN_U32>;
631 def DS_AND_RTN_B32_si : DS_Real_si<0x29, DS_AND_RTN_B32>;
632 def DS_OR_RTN_B32_si : DS_Real_si<0x2a, DS_OR_RTN_B32>;
633 def DS_XOR_RTN_B32_si : DS_Real_si<0x2b, DS_XOR_RTN_B32>;
634 def DS_MSKOR_RTN_B32_si : DS_Real_si<0x2c, DS_MSKOR_RTN_B32>;
635 def DS_WRXCHG_RTN_B32_si : DS_Real_si<0x2d, DS_WRXCHG_RTN_B32>;
636 def DS_WRXCHG2_RTN_B32_si : DS_Real_si<0x2e, DS_WRXCHG2_RTN_B32>;
637 def DS_WRXCHG2ST64_RTN_B32_si : DS_Real_si<0x2f, DS_WRXCHG2ST64_RTN_B32>;
638 def DS_CMPST_RTN_B32_si : DS_Real_si<0x30, DS_CMPST_RTN_B32>;
639 def DS_CMPST_RTN_F32_si : DS_Real_si<0x31, DS_CMPST_RTN_F32>;
640 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
641 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
642
643 // FIXME: this instruction is actually CI/VI
644 def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>;
645
646 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
647 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
648 def DS_READ2_B32_si : DS_Real_si<0x37, DS_READ2_B32>;
649 def DS_READ2ST64_B32_si : DS_Real_si<0x38, DS_READ2ST64_B32>;
650 def DS_READ_I8_si : DS_Real_si<0x39, DS_READ_I8>;
651 def DS_READ_U8_si : DS_Real_si<0x3a, DS_READ_U8>;
652 def DS_READ_I16_si : DS_Real_si<0x3b, DS_READ_I16>;
653 def DS_READ_U16_si : DS_Real_si<0x3c, DS_READ_U16>;
654 def DS_CONSUME_si : DS_Real_si<0x3d, DS_CONSUME>;
655 def DS_APPEND_si : DS_Real_si<0x3e, DS_APPEND>;
656 def DS_ORDERED_COUNT_si : DS_Real_si<0x3f, DS_ORDERED_COUNT>;
657 def DS_ADD_U64_si : DS_Real_si<0x40, DS_ADD_U64>;
658 def DS_SUB_U64_si : DS_Real_si<0x41, DS_SUB_U64>;
659 def DS_RSUB_U64_si : DS_Real_si<0x42, DS_RSUB_U64>;
660 def DS_INC_U64_si : DS_Real_si<0x43, DS_INC_U64>;
661 def DS_DEC_U64_si : DS_Real_si<0x44, DS_DEC_U64>;
662 def DS_MIN_I64_si : DS_Real_si<0x45, DS_MIN_I64>;
663 def DS_MAX_I64_si : DS_Real_si<0x46, DS_MAX_I64>;
664 def DS_MIN_U64_si : DS_Real_si<0x47, DS_MIN_U64>;
665 def DS_MAX_U64_si : DS_Real_si<0x48, DS_MAX_U64>;
666 def DS_AND_B64_si : DS_Real_si<0x49, DS_AND_B64>;
667 def DS_OR_B64_si : DS_Real_si<0x4a, DS_OR_B64>;
668 def DS_XOR_B64_si : DS_Real_si<0x4b, DS_XOR_B64>;
669 def DS_MSKOR_B64_si : DS_Real_si<0x4c, DS_MSKOR_B64>;
670 def DS_WRITE_B64_si : DS_Real_si<0x4d, DS_WRITE_B64>;
671 def DS_WRITE2_B64_si : DS_Real_si<0x4E, DS_WRITE2_B64>;
672 def DS_WRITE2ST64_B64_si : DS_Real_si<0x4f, DS_WRITE2ST64_B64>;
673 def DS_CMPST_B64_si : DS_Real_si<0x50, DS_CMPST_B64>;
674 def DS_CMPST_F64_si : DS_Real_si<0x51, DS_CMPST_F64>;
675 def DS_MIN_F64_si : DS_Real_si<0x52, DS_MIN_F64>;
676 def DS_MAX_F64_si : DS_Real_si<0x53, DS_MAX_F64>;
677
678 def DS_ADD_RTN_U64_si : DS_Real_si<0x60, DS_ADD_RTN_U64>;
679 def DS_SUB_RTN_U64_si : DS_Real_si<0x61, DS_SUB_RTN_U64>;
680 def DS_RSUB_RTN_U64_si : DS_Real_si<0x62, DS_RSUB_RTN_U64>;
681 def DS_INC_RTN_U64_si : DS_Real_si<0x63, DS_INC_RTN_U64>;
682 def DS_DEC_RTN_U64_si : DS_Real_si<0x64, DS_DEC_RTN_U64>;
683 def DS_MIN_RTN_I64_si : DS_Real_si<0x65, DS_MIN_RTN_I64>;
684 def DS_MAX_RTN_I64_si : DS_Real_si<0x66, DS_MAX_RTN_I64>;
685 def DS_MIN_RTN_U64_si : DS_Real_si<0x67, DS_MIN_RTN_U64>;
686 def DS_MAX_RTN_U64_si : DS_Real_si<0x68, DS_MAX_RTN_U64>;
687 def DS_AND_RTN_B64_si : DS_Real_si<0x69, DS_AND_RTN_B64>;
688 def DS_OR_RTN_B64_si : DS_Real_si<0x6a, DS_OR_RTN_B64>;
689 def DS_XOR_RTN_B64_si : DS_Real_si<0x6b, DS_XOR_RTN_B64>;
690 def DS_MSKOR_RTN_B64_si : DS_Real_si<0x6c, DS_MSKOR_RTN_B64>;
691 def DS_WRXCHG_RTN_B64_si : DS_Real_si<0x6d, DS_WRXCHG_RTN_B64>;
692 def DS_WRXCHG2_RTN_B64_si : DS_Real_si<0x6e, DS_WRXCHG2_RTN_B64>;
693 def DS_WRXCHG2ST64_RTN_B64_si : DS_Real_si<0x6f, DS_WRXCHG2ST64_RTN_B64>;
694 def DS_CMPST_RTN_B64_si : DS_Real_si<0x70, DS_CMPST_RTN_B64>;
695 def DS_CMPST_RTN_F64_si : DS_Real_si<0x71, DS_CMPST_RTN_F64>;
696 def DS_MIN_RTN_F64_si : DS_Real_si<0x72, DS_MIN_RTN_F64>;
697 def DS_MAX_RTN_F64_si : DS_Real_si<0x73, DS_MAX_RTN_F64>;
698
699 def DS_READ_B64_si : DS_Real_si<0x76, DS_READ_B64>;
700 def DS_READ2_B64_si : DS_Real_si<0x77, DS_READ2_B64>;
701 def DS_READ2ST64_B64_si : DS_Real_si<0x78, DS_READ2ST64_B64>;
702
703 def DS_ADD_SRC2_U32_si : DS_Real_si<0x80, DS_ADD_SRC2_U32>;
704 def DS_SUB_SRC2_U32_si : DS_Real_si<0x81, DS_SUB_SRC2_U32>;
705 def DS_RSUB_SRC2_U32_si : DS_Real_si<0x82, DS_RSUB_SRC2_U32>;
706 def DS_INC_SRC2_U32_si : DS_Real_si<0x83, DS_INC_SRC2_U32>;
707 def DS_DEC_SRC2_U32_si : DS_Real_si<0x84, DS_DEC_SRC2_U32>;
708 def DS_MIN_SRC2_I32_si : DS_Real_si<0x85, DS_MIN_SRC2_I32>;
709 def DS_MAX_SRC2_I32_si : DS_Real_si<0x86, DS_MAX_SRC2_I32>;
710 def DS_MIN_SRC2_U32_si : DS_Real_si<0x87, DS_MIN_SRC2_U32>;
711 def DS_MAX_SRC2_U32_si : DS_Real_si<0x88, DS_MAX_SRC2_U32>;
712 def DS_AND_SRC2_B32_si : DS_Real_si<0x89, DS_AND_SRC2_B32>;
713 def DS_OR_SRC2_B32_si : DS_Real_si<0x8a, DS_OR_SRC2_B32>;
714 def DS_XOR_SRC2_B32_si : DS_Real_si<0x8b, DS_XOR_SRC2_B32>;
715 def DS_WRITE_SRC2_B32_si : DS_Real_si<0x8d, DS_WRITE_SRC2_B32>;
716
717 def DS_MIN_SRC2_F32_si : DS_Real_si<0x92, DS_MIN_SRC2_F32>;
718 def DS_MAX_SRC2_F32_si : DS_Real_si<0x93, DS_MAX_SRC2_F32>;
719
720 def DS_ADD_SRC2_U64_si : DS_Real_si<0xc0, DS_ADD_SRC2_U64>;
721 def DS_SUB_SRC2_U64_si : DS_Real_si<0xc1, DS_SUB_SRC2_U64>;
722 def DS_RSUB_SRC2_U64_si : DS_Real_si<0xc2, DS_RSUB_SRC2_U64>;
723 def DS_INC_SRC2_U64_si : DS_Real_si<0xc3, DS_INC_SRC2_U64>;
724 def DS_DEC_SRC2_U64_si : DS_Real_si<0xc4, DS_DEC_SRC2_U64>;
725 def DS_MIN_SRC2_I64_si : DS_Real_si<0xc5, DS_MIN_SRC2_I64>;
726 def DS_MAX_SRC2_I64_si : DS_Real_si<0xc6, DS_MAX_SRC2_I64>;
727 def DS_MIN_SRC2_U64_si : DS_Real_si<0xc7, DS_MIN_SRC2_U64>;
728 def DS_MAX_SRC2_U64_si : DS_Real_si<0xc8, DS_MAX_SRC2_U64>;
729 def DS_AND_SRC2_B64_si : DS_Real_si<0xc9, DS_AND_SRC2_B64>;
730 def DS_OR_SRC2_B64_si : DS_Real_si<0xca, DS_OR_SRC2_B64>;
731 def DS_XOR_SRC2_B64_si : DS_Real_si<0xcb, DS_XOR_SRC2_B64>;
732 def DS_WRITE_SRC2_B64_si : DS_Real_si<0xcd, DS_WRITE_SRC2_B64>;
733
734 def DS_MIN_SRC2_F64_si : DS_Real_si<0xd2, DS_MIN_SRC2_F64>;
735 def DS_MAX_SRC2_F64_si : DS_Real_si<0xd3, DS_MAX_SRC2_F64>;
736
737 //===----------------------------------------------------------------------===//
738 // VIInstructions.td
739 //===----------------------------------------------------------------------===//
740
741 class DS_Real_vi op, DS_Pseudo ds> :
742 DS_Real ,
743 SIMCInstr {
744 let AssemblerPredicates = [isVI];
745 let DecoderNamespace="VI";
746
747 // encoding
748 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
749 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
750 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
751 let Inst{24-17} = op;
752 let Inst{31-26} = 0x36; // ds prefix
753 let Inst{39-32} = !if(ds.has_addr, addr, 0);
754 let Inst{47-40} = !if(ds.has_data0, data0, 0);
755 let Inst{55-48} = !if(ds.has_data1, data1, 0);
756 let Inst{63-56} = !if(ds.has_vdst, vdst, 0);
757 }
758
759 def DS_ADD_U32_vi : DS_Real_vi<0x0, DS_ADD_U32>;
760 def DS_SUB_U32_vi : DS_Real_vi<0x1, DS_SUB_U32>;
761 def DS_RSUB_U32_vi : DS_Real_vi<0x2, DS_RSUB_U32>;
762 def DS_INC_U32_vi : DS_Real_vi<0x3, DS_INC_U32>;
763 def DS_DEC_U32_vi : DS_Real_vi<0x4, DS_DEC_U32>;
764 def DS_MIN_I32_vi : DS_Real_vi<0x5, DS_MIN_I32>;
765 def DS_MAX_I32_vi : DS_Real_vi<0x6, DS_MAX_I32>;
766 def DS_MIN_U32_vi : DS_Real_vi<0x7, DS_MIN_U32>;
767 def DS_MAX_U32_vi : DS_Real_vi<0x8, DS_MAX_U32>;
768 def DS_AND_B32_vi : DS_Real_vi<0x9, DS_AND_B32>;
769 def DS_OR_B32_vi : DS_Real_vi<0xa, DS_OR_B32>;
770 def DS_XOR_B32_vi : DS_Real_vi<0xb, DS_XOR_B32>;
771 def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
772 def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
773 def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
774 def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
775 def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
776 def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
777 def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
778 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
779 def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
780 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
781 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
782 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
783 def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
784 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
785 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
786 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
787 def DS_SUB_RTN_U32_vi : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
788 def DS_RSUB_RTN_U32_vi : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
789 def DS_INC_RTN_U32_vi : DS_Real_vi<0x23, DS_INC_RTN_U32>;
790 def DS_DEC_RTN_U32_vi : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
791 def DS_MIN_RTN_I32_vi : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
792 def DS_MAX_RTN_I32_vi : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
793 def DS_MIN_RTN_U32_vi : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
794 def DS_MAX_RTN_U32_vi : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
795 def DS_AND_RTN_B32_vi : DS_Real_vi<0x29, DS_AND_RTN_B32>;
796 def DS_OR_RTN_B32_vi : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
797 def DS_XOR_RTN_B32_vi : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
798 def DS_MSKOR_RTN_B32_vi : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
799 def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
800 def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
801 def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
802 def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
803 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
804 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
805 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
806 def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
807 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
808 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
809 def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
810 def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
811 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
812 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
813 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
814 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
815 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
816 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
817
818 def DS_ADD_U64_vi : DS_Real_vi<0x40, DS_ADD_U64>;
819 def DS_SUB_U64_vi : DS_Real_vi<0x41, DS_SUB_U64>;
820 def DS_RSUB_U64_vi : DS_Real_vi<0x42, DS_RSUB_U64>;
821 def DS_INC_U64_vi : DS_Real_vi<0x43, DS_INC_U64>;
822 def DS_DEC_U64_vi : DS_Real_vi<0x44, DS_DEC_U64>;
823 def DS_MIN_I64_vi : DS_Real_vi<0x45, DS_MIN_I64>;
824 def DS_MAX_I64_vi : DS_Real_vi<0x46, DS_MAX_I64>;
825 def DS_MIN_U64_vi : DS_Real_vi<0x47, DS_MIN_U64>;
826 def DS_MAX_U64_vi : DS_Real_vi<0x48, DS_MAX_U64>;
827 def DS_AND_B64_vi : DS_Real_vi<0x49, DS_AND_B64>;
828 def DS_OR_B64_vi : DS_Real_vi<0x4a, DS_OR_B64>;
829 def DS_XOR_B64_vi : DS_Real_vi<0x4b, DS_XOR_B64>;
830 def DS_MSKOR_B64_vi : DS_Real_vi<0x4c, DS_MSKOR_B64>;
831 def DS_WRITE_B64_vi : DS_Real_vi<0x4d, DS_WRITE_B64>;
832 def DS_WRITE2_B64_vi : DS_Real_vi<0x4E, DS_WRITE2_B64>;
833 def DS_WRITE2ST64_B64_vi : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
834 def DS_CMPST_B64_vi : DS_Real_vi<0x50, DS_CMPST_B64>;
835 def DS_CMPST_F64_vi : DS_Real_vi<0x51, DS_CMPST_F64>;
836 def DS_MIN_F64_vi : DS_Real_vi<0x52, DS_MIN_F64>;
837 def DS_MAX_F64_vi : DS_Real_vi<0x53, DS_MAX_F64>;
838
839 def DS_ADD_RTN_U64_vi : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
840 def DS_SUB_RTN_U64_vi : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
841 def DS_RSUB_RTN_U64_vi : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
842 def DS_INC_RTN_U64_vi : DS_Real_vi<0x63, DS_INC_RTN_U64>;
843 def DS_DEC_RTN_U64_vi : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
844 def DS_MIN_RTN_I64_vi : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
845 def DS_MAX_RTN_I64_vi : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
846 def DS_MIN_RTN_U64_vi : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
847 def DS_MAX_RTN_U64_vi : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
848 def DS_AND_RTN_B64_vi : DS_Real_vi<0x69, DS_AND_RTN_B64>;
849 def DS_OR_RTN_B64_vi : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
850 def DS_XOR_RTN_B64_vi : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
851 def DS_MSKOR_RTN_B64_vi : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
852 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
853 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
854 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
855 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
856 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
857 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
858 def DS_MAX_RTN_F64_vi : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
859
860 def DS_READ_B64_vi : DS_Real_vi<0x76, DS_READ_B64>;
861 def DS_READ2_B64_vi : DS_Real_vi<0x77, DS_READ2_B64>;
862 def DS_READ2ST64_B64_vi : DS_Real_vi<0x78, DS_READ2ST64_B64>;
863
864 def DS_ADD_SRC2_U32_vi : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
865 def DS_SUB_SRC2_U32_vi : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
866 def DS_RSUB_SRC2_U32_vi : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
867 def DS_INC_SRC2_U32_vi : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
868 def DS_DEC_SRC2_U32_vi : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
869 def DS_MIN_SRC2_I32_vi : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
870 def DS_MAX_SRC2_I32_vi : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
871 def DS_MIN_SRC2_U32_vi : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
872 def DS_MAX_SRC2_U32_vi : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
873 def DS_AND_SRC2_B32_vi : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
874 def DS_OR_SRC2_B32_vi : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
875 def DS_XOR_SRC2_B32_vi : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
876 def DS_WRITE_SRC2_B32_vi : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
877 def DS_MIN_SRC2_F32_vi : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
878 def DS_MAX_SRC2_F32_vi : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
879 def DS_ADD_SRC2_U64_vi : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
880 def DS_SUB_SRC2_U64_vi : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
881 def DS_RSUB_SRC2_U64_vi : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
882 def DS_INC_SRC2_U64_vi : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
883 def DS_DEC_SRC2_U64_vi : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
884 def DS_MIN_SRC2_I64_vi : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
885 def DS_MAX_SRC2_I64_vi : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
886 def DS_MIN_SRC2_U64_vi : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
887 def DS_MAX_SRC2_U64_vi : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
888 def DS_AND_SRC2_B64_vi : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
889 def DS_OR_SRC2_B64_vi : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
890 def DS_XOR_SRC2_B64_vi : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
891 def DS_WRITE_SRC2_B64_vi : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
892 def DS_MIN_SRC2_F64_vi : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
893 def DS_MAX_SRC2_F64_vi : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
479479 let Inst{17-16} = op;
480480 let Inst{25-18} = vdst;
481481 let Inst{31-26} = 0x32; // encoding
482 }
483
484 class DSe op> : Enc64 {
485 bits<8> vdst;
486 bits<1> gds;
487 bits<8> addr;
488 bits<8> data0;
489 bits<8> data1;
490 bits<8> offset0;
491 bits<8> offset1;
492
493 let Inst{7-0} = offset0;
494 let Inst{15-8} = offset1;
495 let Inst{17} = gds;
496 let Inst{25-18} = op;
497 let Inst{31-26} = 0x36; //encoding
498 let Inst{39-32} = addr;
499 let Inst{47-40} = data0;
500 let Inst{55-48} = data1;
501 let Inst{63-56} = vdst;
502482 }
503483
504484 class MUBUFe op> : Enc64 {
665645 // Vector I/O operations
666646 //===----------------------------------------------------------------------===//
667647
668 class DS pattern> :
669 InstSI {
670
671 let LGKM_CNT = 1;
672 let DS = 1;
673 let UseNamedOperandTable = 1;
674 let Uses = [M0, EXEC];
675
676 // Most instruction load and store data, so set this as the default.
677 let mayLoad = 1;
678 let mayStore = 1;
679
680 let hasSideEffects = 0;
681 let AsmMatchConverter = "cvtDS";
682 let SchedRW = [WriteLDS];
683 }
684
685648 class MUBUF pattern> :
686649 InstSI {
687650
25842584 }
25852585
25862586 //===----------------------------------------------------------------------===//
2587 // Vector I/O classes
2588 //===----------------------------------------------------------------------===//
2589
2590 class DS_Pseudo pattern> :
2591 DS ,
2592 SIMCInstr {
2593 let isPseudo = 1;
2594 let isCodeGenOnly = 1;
2595 }
2596
2597 class DS_Real_si op, string opName, dag outs, dag ins, string asm> :
2598 DS ,
2599 DSe ,
2600 SIMCInstr {
2601 let isCodeGenOnly = 0;
2602 let AssemblerPredicates = [isSICI];
2603 let DecoderNamespace="SICI";
2604 let DisableDecoder = DisableSIDecoder;
2605 }
2606
2607 class DS_Real_vi op, string opName, dag outs, dag ins, string asm> :
2608 DS ,
2609 DSe_vi ,
2610 SIMCInstr {
2611 let isCodeGenOnly = 0;
2612 let AssemblerPredicates = [isVI];
2613 let DecoderNamespace="VI";
2614 let DisableDecoder = DisableVIDecoder;
2615 }
2616
2617 class DS_Off16_Real_si op, string opName, dag outs, dag ins, string asm> :
2618 DS_Real_si {
2619
2620 // Single load interpret the 2 i8imm operands as a single i16 offset.
2621 bits<16> offset;
2622 let offset0 = offset{7-0};
2623 let offset1 = offset{15-8};
2624 }
2625
2626 class DS_Off16_Real_vi op, string opName, dag outs, dag ins, string asm> :
2627 DS_Real_vi {
2628
2629 // Single load interpret the 2 i8imm operands as a single i16 offset.
2630 bits<16> offset;
2631 let offset0 = offset{7-0};
2632 let offset1 = offset{15-8};
2633 }
2634
2635 multiclass DS_1A_RET_
2636 dag outs = (outs rc:$vdst),
2637 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2638 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2639
2640 def "" : DS_Pseudo ;
2641
2642 let data0 = 0, data1 = 0 in {
2643 def _si : DS_Off16_Real_si ;
2644 def _vi : DS_Off16_Real_vi ;
2645 }
2646 }
2647
2648 // TODO: DS_1A_RET can be inherited from DS_1A_RET_ but its not working
2649 // for some reason. In fact we can remove this class if use dsop everywhere
2650 multiclass DS_1A_RET op, string opName, RegisterClass rc,
2651 dag outs = (outs rc:$vdst),
2652 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2653 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
2654
2655 def "" : DS_Pseudo ;
2656
2657 let data0 = 0, data1 = 0 in {
2658 def _si : DS_Off16_Real_si ;
2659 def _vi : DS_Off16_Real_vi ;
2660 }
2661 }
2662
2663 multiclass DS_1A_Off8_RET op, string opName, RegisterClass rc,
2664 dag outs = (outs rc:$vdst),
2665 dag ins = (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1,
2666 gds:$gds),
2667 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
2668
2669 def "" : DS_Pseudo ;
2670
2671 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
2672 def _si : DS_Real_si ;
2673 def _vi : DS_Real_vi ;
2674 }
2675 }
2676
2677 multiclass DS_1A1D_NORET op, string opName, RegisterClass rc,
2678 dag outs = (outs),
2679 dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
2680 string asm = opName#" $addr, $data0"#"$offset$gds"> {
2681
2682 def "" : DS_Pseudo ,
2683 AtomicNoRet;
2684
2685 let data1 = 0, vdst = 0 in {
2686 def _si : DS_Off16_Real_si ;
2687 def _vi : DS_Off16_Real_vi ;
2688 }
2689 }
2690
2691 multiclass DS_1A_Off8_NORET op, string opName,
2692 dag outs = (outs),
2693 dag ins = (ins VGPR_32:$addr,
2694 offset0:$offset0, offset1:$offset1, gds:$gds),
2695 string asm = opName#" $addr $offset0"#"$offset1$gds"> {
2696
2697 def "" : DS_Pseudo ;
2698
2699 let data0 = 0, data1 = 0, vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
2700 def _si : DS_Real_si ;
2701 def _vi : DS_Real_vi ;
2702 }
2703 }
2704
2705 multiclass DS_1A2D_Off8_NORET op, string opName, RegisterClass rc,
2706 dag outs = (outs),
2707 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2708 offset0:$offset0, offset1:$offset1, gds:$gds),
2709 string asm = opName#" $addr, $data0, $data1$offset0$offset1$gds"> {
2710
2711 def "" : DS_Pseudo ;
2712
2713 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
2714 def _si : DS_Real_si ;
2715 def _vi : DS_Real_vi ;
2716 }
2717 }
2718
2719 multiclass DS_1A1D_RET op, string opName, RegisterClass rc,
2720 string noRetOp = "",
2721 dag outs = (outs rc:$vdst),
2722 dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds),
2723 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
2724
2725 let hasPostISelHook = 1 in {
2726 def "" : DS_Pseudo ,
2727 AtomicNoRet;
2728
2729 let data1 = 0 in {
2730 def _si : DS_Off16_Real_si ;
2731 def _vi : DS_Off16_Real_vi ;
2732 }
2733 }
2734 }
2735
2736 multiclass DS_1A1D_PERMUTE op, string opName, RegisterClass rc,
2737 SDPatternOperator node = null_frag,
2738 dag outs = (outs rc:$vdst),
2739 dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset),
2740 string asm = opName#" $vdst, $addr, $data0"#"$offset"> {
2741
2742 let mayLoad = 0, mayStore = 0, isConvergent = 1 in {
2743 def "" : DS_Pseudo
2744 [(set i32:$vdst,
2745 (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))]>;
2746
2747 let data1 = 0, gds = 0 in {
2748 def "_vi" : DS_Off16_Real_vi ;
2749 }
2750 }
2751 }
2752
2753 multiclass DS_1A2D_RET_m op, string opName, RegisterClass rc,
2754 string noRetOp = "", dag ins,
2755 dag outs = (outs rc:$vdst),
2756 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
2757
2758 let hasPostISelHook = 1 in {
2759 def "" : DS_Pseudo ,
2760 AtomicNoRet;
2761
2762 def _si : DS_Off16_Real_si ;
2763 def _vi : DS_Off16_Real_vi ;
2764 }
2765 }
2766
2767 multiclass DS_1A2D_RET op, string asm, RegisterClass rc,
2768 string noRetOp = "", RegisterClass src = rc> :
2769 DS_1A2D_RET_m
2770 (ins VGPR_32:$addr, src:$data0, src:$data1,
2771 offset:$offset, gds:$gds)
2772 >;
2773
2774 multiclass DS_1A2D_NORET op, string opName, RegisterClass rc,
2775 string noRetOp = opName,
2776 dag outs = (outs),
2777 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2778 offset:$offset, gds:$gds),
2779 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
2780
2781 def "" : DS_Pseudo ,
2782 AtomicNoRet;
2783
2784 let vdst = 0 in {
2785 def _si : DS_Off16_Real_si ;
2786 def _vi : DS_Off16_Real_vi ;
2787 }
2788 }
2789
2790 multiclass DS_0A_RET op, string opName,
2791 dag outs = (outs VGPR_32:$vdst),
2792 dag ins = (ins offset:$offset, gds:$gds),
2793 string asm = opName#" $vdst"#"$offset"#"$gds"> {
2794
2795 let mayLoad = 1, mayStore = 1 in {
2796 def "" : DS_Pseudo ;
2797
2798 let addr = 0, data0 = 0, data1 = 0 in {
2799 def _si : DS_Off16_Real_si ;
2800 def _vi : DS_Off16_Real_vi ;
2801 } // end addr = 0, data0 = 0, data1 = 0
2802 } // end mayLoad = 1, mayStore = 1
2803 }
2804
2805 multiclass DS_1A_RET_GDS op, string opName,
2806 dag outs = (outs VGPR_32:$vdst),
2807 dag ins = (ins VGPR_32:$addr, offset:$offset),
2808 string asm = opName#" $vdst, $addr"#"$offset gds"> {
2809
2810 def "" : DS_Pseudo ;
2811
2812 let data0 = 0, data1 = 0, gds = 1 in {
2813 def _si : DS_Off16_Real_si ;
2814 def _vi : DS_Off16_Real_vi ;
2815 } // end data0 = 0, data1 = 0, gds = 1
2816 }
2817
2818 multiclass DS_1A_GDS op, string opName,
2819 dag outs = (outs),
2820 dag ins = (ins VGPR_32:$addr),
2821 string asm = opName#" $addr gds"> {
2822
2823 def "" : DS_Pseudo ;
2824
2825 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
2826 def _si : DS_Real_si ;
2827 def _vi : DS_Real_vi ;
2828 } // end vdst = 0, data = 0, data1 = 0, gds = 1
2829 }
2830
2831 multiclass DS_1A op, string opName,
2832 dag outs = (outs),
2833 dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds),
2834 string asm = opName#" $addr"#"$offset"#"$gds"> {
2835
2836 let mayLoad = 1, mayStore = 1 in {
2837 def "" : DS_Pseudo ;
2838
2839 let vdst = 0, data0 = 0, data1 = 0 in {
2840 def _si : DS_Off16_Real_si ;
2841 def _vi : DS_Off16_Real_vi ;
2842 } // let vdst = 0, data0 = 0, data1 = 0
2843 } // end mayLoad = 1, mayStore = 1
2844 }
2845
2846 //===----------------------------------------------------------------------===//
28472587 // MTBUF classes
28482588 //===----------------------------------------------------------------------===//
28492589
37263466 include "SIInstructions.td"
37273467 include "CIInstructions.td"
37283468 include "VIInstructions.td"
3469
3470 include "DSInstructions.td"
757757 defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 , "v_cmpx_class_f32">;
758758 defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 , "v_cmp_class_f64">;
759759 defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 , "v_cmpx_class_f64">;
760
761 //===----------------------------------------------------------------------===//
762 // DS Instructions
763 //===----------------------------------------------------------------------===//
764
765 defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>;
766 defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>;
767 defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>;
768 defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
769 defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
770 defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>;
771 defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>;
772 defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>;
773 defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>;
774 defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>;
775 defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>;
776 defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>;
777 defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>;
778 let mayLoad = 0 in {
779 defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>;
780 defm DS_WRITE2_B32 : DS_1A2D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>;
781 defm DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>;
782 }
783 defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>;
784 defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>;
785 defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>;
786 defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>;
787
788 defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">;
789 defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">;
790 defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">;
791 defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">;
792 defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">;
793 let mayLoad = 0 in {
794 defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>;
795 defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>;
796 }
797 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
798 defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
799 defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
800 defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
801 defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
802 defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
803 defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
804 defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
805 defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
806 defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
807 defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
808 defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
809 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
810 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>;
811 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET <
812 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32
813 >;
814 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET <
815 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32
816 >;
817 defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
818 defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
819 defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
820 defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
821
822 let Uses = [EXEC], mayLoad =0, mayStore = 0, isConvergent = 1 in {
823 defm DS_SWIZZLE_B32 : DS_1A_RET_ , "ds_swizzle_b32", VGPR_32>;
824 }
825
826 let mayStore = 0 in {
827 defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>;
828 defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>;
829 defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>;
830 defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>;
831 defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>;
832 defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>;
833 defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>;
834 }
835 defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">;
836 defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">;
837 defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">;
838 defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
839 defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
840 defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
841 defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
842 defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
843 defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
844 defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
845 defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
846 defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
847 defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
848 defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
849 defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
850 defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
851 let mayLoad = 0 in {
852 defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>;
853 defm DS_WRITE2_B64 : DS_1A2D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>;
854 defm DS_WRITE2ST64_B64 : DS_1A2D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>;
855 }
856 defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
857 defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
858 defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
859 defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
860
861 defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
862 defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
863 defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
864 defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
865 defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
866 defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
867 defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
868 defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
869 defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
870 defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
871 defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
872 defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
873 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
874 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
875 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>;
876 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>;
877 defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
878 defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
879 defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">;
880 defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">;
881
882 let mayStore = 0 in {
883 defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>;
884 defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>;
885 defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>;
886 }
887
888 defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">;
889 defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">;
890 defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">;
891 defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">;
892 defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">;
893 defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">;
894 defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">;
895 defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">;
896 defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">;
897 defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">;
898 defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">;
899 defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">;
900 defm DS_WRITE_SRC2_B32 : DS_1A_Off8_NORET <0x8d, "ds_write_src2_b32">;
901
902 defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">;
903 defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">;
904
905 defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">;
906 defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">;
907 defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">;
908 defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">;
909 defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">;
910 defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">;
911 defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">;
912 defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">;
913 defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">;
914 defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">;
915 defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">;
916 defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">;
917 defm DS_WRITE_SRC2_B64 : DS_1A_Off8_NORET <0xcd, "ds_write_src2_b64">;
918
919 defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">;
920 defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">;
921760
922761 //===----------------------------------------------------------------------===//
923762 // MUBUF Instructions
23602199 >;
23612200
23622201 //===----------------------------------------------------------------------===//
2363 // DS_SWIZZLE Intrinsic Pattern.
2364 //===----------------------------------------------------------------------===//
2365 def : Pat <
2366 (int_amdgcn_ds_swizzle i32:$src, imm:$offset16),
2367 (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0))
2368 >;
2369
2370 //===----------------------------------------------------------------------===//
23712202 // V_ICMPIntrinsic Pattern.
23722203 //===----------------------------------------------------------------------===//
23732204 class ICMP_Pattern : Pat <
24312262 def : FCMP_Pattern ;
24322263 def : FCMP_Pattern ;
24332264 def : FCMP_Pattern ;
2434
2435 //===----------------------------------------------------------------------===//
24362265 // SMRD Patterns
24372266 //===----------------------------------------------------------------------===//
24382267
31402969 defm : BFIPatterns ;
31412970 def : ROTRPattern ;
31422971
3143 /********** ======================= **********/
3144 /********** Load/Store Patterns **********/
3145 /********** ======================= **********/
3146
3147 class DSReadPat : Pat <
3148 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
3149 (inst $ptr, (as_i16imm $offset), (i1 0))
3150 >;
3151
3152 def : DSReadPat ;
3153 def : DSReadPat ;
3154 def : DSReadPat ;
3155 def : DSReadPat ;
3156 def : DSReadPat ;
3157
3158 let AddedComplexity = 100 in {
3159
3160 def : DSReadPat ;
3161
3162 } // End AddedComplexity = 100
3163
3164 def : Pat <
3165 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
3166 i8:$offset1))),
3167 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0))
3168 >;
3169
3170 class DSWritePat : Pat <
3171 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
3172 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
3173 >;
3174
3175 def : DSWritePat ;
3176 def : DSWritePat ;
3177 def : DSWritePat ;
3178
3179 let AddedComplexity = 100 in {
3180
3181 def : DSWritePat ;
3182 } // End AddedComplexity = 100
3183
3184 def : Pat <
3185 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
3186 i8:$offset1)),
3187 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0),
3188 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1,
3189 (i1 0))
3190 >;
3191
3192 class DSAtomicRetPat : Pat <
3193 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
3194 (inst $ptr, $value, (as_i16imm $offset), (i1 0))
3195 >;
3196
3197 class DSAtomicCmpXChg : Pat <
3198 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
3199 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0))
3200 >;
3201
3202
3203 // 32-bit atomics.
3204 def : DSAtomicRetPat;
3205 def : DSAtomicRetPat;
3206 def : DSAtomicRetPat;
3207 def : DSAtomicRetPat;
3208 def : DSAtomicRetPat;
3209 def : DSAtomicRetPat;
3210 def : DSAtomicRetPat;
3211 def : DSAtomicRetPat;
3212 def : DSAtomicRetPat;
3213 def : DSAtomicRetPat;
3214 def : DSAtomicRetPat;
3215 def : DSAtomicRetPat;
3216 def : DSAtomicCmpXChg;
3217
3218 // 64-bit atomics.
3219 def : DSAtomicRetPat;
3220 def : DSAtomicRetPat;
3221 def : DSAtomicRetPat;
3222 def : DSAtomicRetPat;
3223 def : DSAtomicRetPat;
3224 def : DSAtomicRetPat;
3225 def : DSAtomicRetPat;
3226 def : DSAtomicRetPat;
3227 def : DSAtomicRetPat;
3228 def : DSAtomicRetPat;
3229 def : DSAtomicRetPat;
3230 def : DSAtomicRetPat;
3231
3232 def : DSAtomicCmpXChg;
3233
3234
32352972 //===----------------------------------------------------------------------===//
32362973 // MUBUF Patterns
32372974 //===----------------------------------------------------------------------===//
99 // VI Instruction format definitions.
1010 //
1111 //===----------------------------------------------------------------------===//
12
13 class DSe_vi op> : Enc64 {
14 bits<8> vdst;
15 bits<1> gds;
16 bits<8> addr;
17 bits<8> data0;
18 bits<8> data1;
19 bits<8> offset0;
20 bits<8> offset1;
21
22 let Inst{7-0} = offset0;
23 let Inst{15-8} = offset1;
24 let Inst{16} = gds;
25 let Inst{24-17} = op;
26 let Inst{31-26} = 0x36; //encoding
27 let Inst{39-32} = addr;
28 let Inst{47-40} = data0;
29 let Inst{55-48} = data1;
30 let Inst{63-56} = vdst;
31 }
3212
3313 class MUBUFe_vi op> : Enc64 {
3414 bits<12> offset;
143143 (S_MEMREALTIME)
144144 >;
145145
146 //===----------------------------------------------------------------------===//
147 // DS_PERMUTE/DS_BPERMUTE Instructions.
148 //===----------------------------------------------------------------------===//
149
150 let Uses = [EXEC] in {
151 defm DS_PERMUTE_B32 : DS_1A1D_PERMUTE <0x3e, "ds_permute_b32", VGPR_32,
152 int_amdgcn_ds_permute>;
153 defm DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <0x3f, "ds_bpermute_b32", VGPR_32,
154 int_amdgcn_ds_bpermute>;
155 }
156
157146 } // End Predicates = [isVI]
269269 // SICI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0xf0,0xd8,0x02,0x00,0x00,0x08]
270270 // VI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x00,0x00,0x08]
271271
272 ds_consume v8
273 // SICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
274 // VI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08]
275
276 ds_append v8
277 // SICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
278 // VI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08]
279
280 ds_ordered_count v8, v2 gds
281 // SICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
282 // VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
272
273 //ds_consume v8
274 // FIXMESICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
275 // FIXMEVI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08]
276
277 //ds_append v8
278 // FIXMESICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
279 // FIXMEVI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08]
280
281 //ds_ordered_count v8, v2 gds
282 // FIXMESICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
283 // FIXMEVI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
283284
284285 ds_add_u64 v2, v[4:5]
285286 // SICI: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00]
185185 # VI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x00,0x00,0x08]
186186 0x00 0x00 0x78 0xd8 0x02 0x00 0x00 0x08
187187
188 # VI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08]
189 0x00 0x00 0x7a 0xd8 0x00 0x00 0x00 0x08
190
191 # FIXME: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08]
192 0x00 0x00 0x7c 0xd8 0x00 0x00 0x00 0x08
193
194 # VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
195 0x00 0x00 0x7f 0xd8 0x02 0x00 0x00 0x08
196
197188 # VI: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x00]
198189 0x00 0x00 0x80 0xd8 0x02 0x04 0x00 0x00
199190