llvm.org GIT mirror llvm / 16db710
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 8 years ago
2 changed file(s) with 14 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
64636463 EVT VT = Op.getValueType();
64646464 DebugLoc dl = Op.getDebugLoc();
64656465 unsigned NumElems = VT.getVectorNumElements();
6466 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
64666467 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
64676468 bool V1IsSplat = false;
64686469 bool V2IsSplat = false;
64746475
64756476 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
64766477
6477 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
6478 if (V1IsUndef && V2IsUndef)
6479 return DAG.getUNDEF(VT);
6480
6481 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
64786482
64796483 // Vector shuffle lowering takes 3 steps:
64806484 //
5353 ; CHECK-NOT: vinsertf128
5454 %shuffle.i = shufflevector <2 x double> %1, <2 x double> , <4 x i32>
5555 ret <4 x double> %shuffle.i
56 }
56 }
57
58 define <16 x i16> @test7(<4 x i16> %a) nounwind {
59 ; CHECK: test7
60
61 %b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32>
62 ret <16 x i16> %b
63 }
64