llvm.org GIT mirror llvm / 16c29b5
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 9 years ago
138 changed file(s) with 7335 addition(s) and 7314 deletion(s). Raw diff Collapse all Expand all
2626 class Type;
2727 class MachineFunction;
2828 class MachineBasicBlock;
29 class TargetFrameInfo;
29 class TargetFrameLowering;
3030 class BitVector;
3131
3232 /// The CalleeSavedInfo class tracks the information need to locate where a
195195 /// spill slots.
196196 SmallVector SpillObjects;
197197
198 /// TargetFrameInfo - Target information about frame layout.
199 ///
200 const TargetFrameInfo &TFI;
198 /// TargetFrameLowering - Target information about frame layout.
199 ///
200 const TargetFrameLowering &TFI;
201201
202202 /// LocalFrameObjects - References to frame indices which are mapped
203203 /// into the local frame allocation block.
216216 bool UseLocalStackAllocationBlock;
217217
218218 public:
219 explicit MachineFrameInfo(const TargetFrameInfo &tfi) : TFI(tfi) {
219 explicit MachineFrameInfo(const TargetFrameLowering &tfi) : TFI(tfi) {
220220 StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
221221 HasVarSizedObjects = false;
222222 FrameAddressTaken = false;
1515
1616 #include "llvm/CodeGen/MachineLocation.h"
1717 #include "llvm/Target/TargetLoweringObjectFile.h"
18 #include "llvm/Target/TargetFrameInfo.h"
18 #include "llvm/Target/TargetFrameLowering.h"
1919 #include "llvm/Target/TargetRegisterInfo.h"
2020
2121 namespace llvm {
2727 class TargetAsmInfo {
2828 unsigned PointerSize;
2929 bool IsLittleEndian;
30 TargetFrameInfo::StackDirection StackDir;
30 TargetFrameLowering::StackDirection StackDir;
3131 const TargetRegisterInfo *TRI;
3232 std::vector InitialFrameState;
3333 const TargetLoweringObjectFile *TLOF;
4545 return IsLittleEndian;
4646 }
4747
48 TargetFrameInfo::StackDirection getStackGrowthDirection() const {
48 TargetFrameLowering::StackDirection getStackGrowthDirection() const {
4949 return StackDir;
5050 }
5151
+0
-196
include/llvm/Target/TargetFrameInfo.h less more
None //===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Interface to describe the layout of a stack frame on the target machine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_TARGETFRAMEINFO_H
14 #define LLVM_TARGET_TARGETFRAMEINFO_H
15
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17
18 #include
19 #include
20
21 namespace llvm {
22 class CalleeSavedInfo;
23 class MachineFunction;
24 class MachineBasicBlock;
25 class MachineMove;
26 class RegScavenger;
27
28 /// Information about stack frame layout on the target. It holds the direction
29 /// of stack growth, the known stack alignment on entry to each function, and
30 /// the offset to the locals area.
31 ///
32 /// The offset to the local area is the offset from the stack pointer on
33 /// function entry to the first location where function data (local variables,
34 /// spill locations) can be stored.
35 class TargetFrameInfo {
36 public:
37 enum StackDirection {
38 StackGrowsUp, // Adding to the stack increases the stack address
39 StackGrowsDown // Adding to the stack decreases the stack address
40 };
41
42 // Maps a callee saved register to a stack slot with a fixed offset.
43 struct SpillSlot {
44 unsigned Reg;
45 int Offset; // Offset relative to stack pointer on function entry.
46 };
47 private:
48 StackDirection StackDir;
49 unsigned StackAlignment;
50 unsigned TransientStackAlignment;
51 int LocalAreaOffset;
52 public:
53 TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO,
54 unsigned TransAl = 1)
55 : StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
56 LocalAreaOffset(LAO) {}
57
58 virtual ~TargetFrameInfo();
59
60 // These methods return information that describes the abstract stack layout
61 // of the target machine.
62
63 /// getStackGrowthDirection - Return the direction the stack grows
64 ///
65 StackDirection getStackGrowthDirection() const { return StackDir; }
66
67 /// getStackAlignment - This method returns the number of bytes to which the
68 /// stack pointer must be aligned on entry to a function. Typically, this
69 /// is the largest alignment for any data object in the target.
70 ///
71 unsigned getStackAlignment() const { return StackAlignment; }
72
73 /// getTransientStackAlignment - This method returns the number of bytes to
74 /// which the stack pointer must be aligned at all times, even between
75 /// calls.
76 ///
77 unsigned getTransientStackAlignment() const {
78 return TransientStackAlignment;
79 }
80
81 /// getOffsetOfLocalArea - This method returns the offset of the local area
82 /// from the stack pointer on entrance to a function.
83 ///
84 int getOffsetOfLocalArea() const { return LocalAreaOffset; }
85
86 /// getCalleeSavedSpillSlots - This method returns a pointer to an array of
87 /// pairs, that contains an entry for each callee saved register that must be
88 /// spilled to a particular stack location if it is spilled.
89 ///
90 /// Each entry in this array contains a pair, indicating the
91 /// fixed offset from the incoming stack pointer that each register should be
92 /// spilled at. If a register is not listed here, the code generator is
93 /// allowed to spill it anywhere it chooses.
94 ///
95 virtual const SpillSlot *
96 getCalleeSavedSpillSlots(unsigned &NumEntries) const {
97 NumEntries = 0;
98 return 0;
99 }
100
101 /// targetHandlesStackFrameRounding - Returns true if the target is
102 /// responsible for rounding up the stack frame (probably at emitPrologue
103 /// time).
104 virtual bool targetHandlesStackFrameRounding() const {
105 return false;
106 }
107
108 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
109 /// the function.
110 virtual void emitPrologue(MachineFunction &MF) const = 0;
111 virtual void emitEpilogue(MachineFunction &MF,
112 MachineBasicBlock &MBB) const = 0;
113
114 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
115 /// saved registers and returns true if it isn't possible / profitable to do
116 /// so by issuing a series of store instructions via
117 /// storeRegToStackSlot(). Returns false otherwise.
118 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
119 MachineBasicBlock::iterator MI,
120 const std::vector &CSI,
121 const TargetRegisterInfo *TRI) const {
122 return false;
123 }
124
125 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
126 /// saved registers and returns true if it isn't possible / profitable to do
127 /// so by issuing a series of load instructions via loadRegToStackSlot().
128 /// Returns false otherwise.
129 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator MI,
131 const std::vector &CSI,
132 const TargetRegisterInfo *TRI) const {
133 return false;
134 }
135
136 /// hasFP - Return true if the specified function should have a dedicated
137 /// frame pointer register. For most targets this is true only if the function
138 /// has variable sized allocas or if frame pointer elimination is disabled.
139 virtual bool hasFP(const MachineFunction &MF) const = 0;
140
141 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
142 /// not required, we reserve argument space for call sites in the function
143 /// immediately on entry to the current function. This eliminates the need for
144 /// add/sub sp brackets around call sites. Returns true if the call frame is
145 /// included as part of the stack frame.
146 virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
147 return !hasFP(MF);
148 }
149
150 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
151 /// call frame pseudo ops before doing frame index elimination. This is
152 /// possible only when frame index references between the pseudos won't
153 /// need adjusting for the call frame adjustments. Normally, that's true
154 /// if the function has a reserved call frame or a frame pointer. Some
155 /// targets (Thumb2, for example) may have more complicated criteria,
156 /// however, and can override this behavior.
157 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
158 return hasReservedCallFrame(MF) || hasFP(MF);
159 }
160
161 /// getInitialFrameState - Returns a list of machine moves that are assumed
162 /// on entry to all functions. Note that LabelID is ignored (assumed to be
163 /// the beginning of the function.)
164 virtual void getInitialFrameState(std::vector &Moves) const;
165
166 /// getFrameIndexOffset - Returns the displacement from the frame register to
167 /// the stack frame of the specified index.
168 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
169
170 /// getFrameIndexReference - This method should return the base register
171 /// and offset used to reference a frame index location. The offset is
172 /// returned directly, and the base register is returned via FrameReg.
173 virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
174 unsigned &FrameReg) const;
175
176 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
177 /// before PrologEpilogInserter scans the physical registers used to determine
178 /// what callee saved registers should be spilled. This method is optional.
179 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
180 RegScavenger *RS = NULL) const {
181
182 }
183
184 /// processFunctionBeforeFrameFinalized - This method is called immediately
185 /// before the specified function's frame layout (MF.getFrameInfo()) is
186 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
187 /// replaced with direct constants. This method is optional.
188 ///
189 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
190 }
191 };
192
193 } // End llvm namespace
194
195 #endif
0 //===-- llvm/Target/TargetFrameLowering.h ---------------------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Interface to describe the layout of a stack frame on the target machine.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_TARGET_TARGETFRAMELOWERING_H
14 #define LLVM_TARGET_TARGETFRAMELOWERING_H
15
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17
18 #include
19 #include
20
21 namespace llvm {
22 class CalleeSavedInfo;
23 class MachineFunction;
24 class MachineBasicBlock;
25 class MachineMove;
26 class RegScavenger;
27
28 /// Information about stack frame layout on the target. It holds the direction
29 /// of stack growth, the known stack alignment on entry to each function, and
30 /// the offset to the locals area.
31 ///
32 /// The offset to the local area is the offset from the stack pointer on
33 /// function entry to the first location where function data (local variables,
34 /// spill locations) can be stored.
35 class TargetFrameLowering {
36 public:
37 enum StackDirection {
38 StackGrowsUp, // Adding to the stack increases the stack address
39 StackGrowsDown // Adding to the stack decreases the stack address
40 };
41
42 // Maps a callee saved register to a stack slot with a fixed offset.
43 struct SpillSlot {
44 unsigned Reg;
45 int Offset; // Offset relative to stack pointer on function entry.
46 };
47 private:
48 StackDirection StackDir;
49 unsigned StackAlignment;
50 unsigned TransientStackAlignment;
51 int LocalAreaOffset;
52 public:
53 TargetFrameLowering(StackDirection D, unsigned StackAl, int LAO,
54 unsigned TransAl = 1)
55 : StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl),
56 LocalAreaOffset(LAO) {}
57
58 virtual ~TargetFrameLowering();
59
60 // These methods return information that describes the abstract stack layout
61 // of the target machine.
62
63 /// getStackGrowthDirection - Return the direction the stack grows
64 ///
65 StackDirection getStackGrowthDirection() const { return StackDir; }
66
67 /// getStackAlignment - This method returns the number of bytes to which the
68 /// stack pointer must be aligned on entry to a function. Typically, this
69 /// is the largest alignment for any data object in the target.
70 ///
71 unsigned getStackAlignment() const { return StackAlignment; }
72
73 /// getTransientStackAlignment - This method returns the number of bytes to
74 /// which the stack pointer must be aligned at all times, even between
75 /// calls.
76 ///
77 unsigned getTransientStackAlignment() const {
78 return TransientStackAlignment;
79 }
80
81 /// getOffsetOfLocalArea - This method returns the offset of the local area
82 /// from the stack pointer on entrance to a function.
83 ///
84 int getOffsetOfLocalArea() const { return LocalAreaOffset; }
85
86 /// getCalleeSavedSpillSlots - This method returns a pointer to an array of
87 /// pairs, that contains an entry for each callee saved register that must be
88 /// spilled to a particular stack location if it is spilled.
89 ///
90 /// Each entry in this array contains a pair, indicating the
91 /// fixed offset from the incoming stack pointer that each register should be
92 /// spilled at. If a register is not listed here, the code generator is
93 /// allowed to spill it anywhere it chooses.
94 ///
95 virtual const SpillSlot *
96 getCalleeSavedSpillSlots(unsigned &NumEntries) const {
97 NumEntries = 0;
98 return 0;
99 }
100
101 /// targetHandlesStackFrameRounding - Returns true if the target is
102 /// responsible for rounding up the stack frame (probably at emitPrologue
103 /// time).
104 virtual bool targetHandlesStackFrameRounding() const {
105 return false;
106 }
107
108 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
109 /// the function.
110 virtual void emitPrologue(MachineFunction &MF) const = 0;
111 virtual void emitEpilogue(MachineFunction &MF,
112 MachineBasicBlock &MBB) const = 0;
113
114 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
115 /// saved registers and returns true if it isn't possible / profitable to do
116 /// so by issuing a series of store instructions via
117 /// storeRegToStackSlot(). Returns false otherwise.
118 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
119 MachineBasicBlock::iterator MI,
120 const std::vector &CSI,
121 const TargetRegisterInfo *TRI) const {
122 return false;
123 }
124
125 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
126 /// saved registers and returns true if it isn't possible / profitable to do
127 /// so by issuing a series of load instructions via loadRegToStackSlot().
128 /// Returns false otherwise.
129 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
130 MachineBasicBlock::iterator MI,
131 const std::vector &CSI,
132 const TargetRegisterInfo *TRI) const {
133 return false;
134 }
135
136 /// hasFP - Return true if the specified function should have a dedicated
137 /// frame pointer register. For most targets this is true only if the function
138 /// has variable sized allocas or if frame pointer elimination is disabled.
139 virtual bool hasFP(const MachineFunction &MF) const = 0;
140
141 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
142 /// not required, we reserve argument space for call sites in the function
143 /// immediately on entry to the current function. This eliminates the need for
144 /// add/sub sp brackets around call sites. Returns true if the call frame is
145 /// included as part of the stack frame.
146 virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
147 return !hasFP(MF);
148 }
149
150 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
151 /// call frame pseudo ops before doing frame index elimination. This is
152 /// possible only when frame index references between the pseudos won't
153 /// need adjusting for the call frame adjustments. Normally, that's true
154 /// if the function has a reserved call frame or a frame pointer. Some
155 /// targets (Thumb2, for example) may have more complicated criteria,
156 /// however, and can override this behavior.
157 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
158 return hasReservedCallFrame(MF) || hasFP(MF);
159 }
160
161 /// getInitialFrameState - Returns a list of machine moves that are assumed
162 /// on entry to all functions. Note that LabelID is ignored (assumed to be
163 /// the beginning of the function.)
164 virtual void getInitialFrameState(std::vector &Moves) const;
165
166 /// getFrameIndexOffset - Returns the displacement from the frame register to
167 /// the stack frame of the specified index.
168 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
169
170 /// getFrameIndexReference - This method should return the base register
171 /// and offset used to reference a frame index location. The offset is
172 /// returned directly, and the base register is returned via FrameReg.
173 virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
174 unsigned &FrameReg) const;
175
176 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
177 /// before PrologEpilogInserter scans the physical registers used to determine
178 /// what callee saved registers should be spilled. This method is optional.
179 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
180 RegScavenger *RS = NULL) const {
181
182 }
183
184 /// processFunctionBeforeFrameFinalized - This method is called immediately
185 /// before the specified function's frame layout (MF.getFrameInfo()) is
186 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
187 /// replaced with direct constants. This method is optional.
188 ///
189 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
190 }
191 };
192
193 } // End llvm namespace
194
195 #endif
2828 class TargetJITInfo;
2929 class TargetLowering;
3030 class TargetSelectionDAGInfo;
31 class TargetFrameInfo;
31 class TargetFrameLowering;
3232 class JITCodeEmitter;
3333 class MCContext;
3434 class TargetRegisterInfo;
116116 // -- Stack frame information
117117 // -- Selection DAG lowering information
118118 //
119 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
120 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
119 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
120 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
121121 virtual const TargetLowering *getTargetLowering() const { return 0; }
122122 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
123 virtual const TargetData *getTargetData() const { return 0; }
123 virtual const TargetData *getTargetData() const { return 0; }
124124
125125 /// getMCAsmInfo - Return target specific asm information.
126126 ///
1818 #include "llvm/MC/MCStreamer.h"
1919 #include "llvm/MC/MCSymbol.h"
2020 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetFrameLowering.h"
2222 #include "llvm/Target/TargetLoweringObjectFile.h"
2323 #include "llvm/Target/TargetMachine.h"
2424 #include "llvm/Target/TargetRegisterInfo.h"
213213 const TargetRegisterInfo *RI = TM.getRegisterInfo();
214214
215215 int stackGrowth = TM.getTargetData()->getPointerSize();
216 if (TM.getFrameInfo()->getStackGrowthDirection() !=
217 TargetFrameInfo::StackGrowsUp)
216 if (TM.getFrameLowering()->getStackGrowthDirection() !=
217 TargetFrameLowering::StackGrowsUp)
218218 stackGrowth *= -1;
219219
220220 for (unsigned i = 0, N = Moves.size(); i < N; ++i) {
2323 #include "llvm/MC/MCSymbol.h"
2424 #include "llvm/Target/Mangler.h"
2525 #include "llvm/Target/TargetData.h"
26 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetFrameLowering.h"
2727 #include "llvm/Target/TargetLoweringObjectFile.h"
2828 #include "llvm/Target/TargetMachine.h"
2929 #include "llvm/Target/TargetRegisterInfo.h"
593593 void DwarfDebug::addVariableAddress(DbgVariable *&DV, DIE *Die, int64_t FI) {
594594 MachineLocation Location;
595595 unsigned FrameReg;
596 const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
596 const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
597597 int Offset = TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
598598 Location.set(FrameReg, Offset);
599599
32933293 return;
32943294
32953295 int stackGrowth = Asm->getTargetData().getPointerSize();
3296 if (Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
3297 TargetFrameInfo::StackGrowsDown)
3296 if (Asm->TM.getFrameLowering()->getStackGrowthDirection() ==
3297 TargetFrameLowering::StackGrowsDown)
32983298 stackGrowth *= -1;
32993299
33003300 // Start the dwarf frame section.
33173317 Asm->EmitSLEB128(stackGrowth, "CIE Data Alignment Factor");
33183318 Asm->OutStreamer.AddComment("CIE RA Column");
33193319 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
3320 const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
3320 const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
33213321 Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false));
33223322
33233323 std::vector Moves;
2525 #include "llvm/MC/MCSymbol.h"
2626 #include "llvm/Target/Mangler.h"
2727 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetFrameLowering.h"
2929 #include "llvm/Target/TargetLoweringObjectFile.h"
3030 #include "llvm/Target/TargetMachine.h"
3131 #include "llvm/Target/TargetOptions.h"
4949 void DwarfException::EmitCIE(const Function *PersonalityFn, unsigned Index) {
5050 // Size and sign of stack growth.
5151 int stackGrowth = Asm->getTargetData().getPointerSize();
52 if (Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
53 TargetFrameInfo::StackGrowsDown)
52 if (Asm->TM.getFrameLowering()->getStackGrowthDirection() ==
53 TargetFrameLowering::StackGrowsDown)
5454 stackGrowth *= -1;
5555
5656 const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering();
126126 Asm->OutStreamer.AddComment("CIE Return Address Column");
127127
128128 const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
129 const TargetFrameInfo *TFI = Asm->TM.getFrameInfo();
129 const TargetFrameLowering *TFI = Asm->TM.getFrameLowering();
130130 Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
131131
132132 if (Augmentation[0]) {
2323 #include "llvm/CodeGen/MachineFunctionPass.h"
2424 #include "llvm/CodeGen/MachineInstrBuilder.h"
2525 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetFrameLowering.h"
2727 #include "llvm/Target/TargetInstrInfo.h"
2828 #include "llvm/Target/TargetMachine.h"
2929 #include "llvm/Target/TargetRegisterInfo.h"
381381 }
382382
383383 void MachineCodeAnalysis::FindStackOffsets(MachineFunction &MF) {
384 const TargetFrameInfo *TFI = TM->getFrameInfo();
384 const TargetFrameLowering *TFI = TM->getFrameLowering();
385385 assert(TFI && "TargetRegisterInfo not available!");
386386
387387 for (GCFunctionInfo::roots_iterator RI = FI->roots_begin(),
3333 #include "llvm/Support/ErrorHandling.h"
3434 #include "llvm/Support/raw_ostream.h"
3535 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetFrameInfo.h"
36 #include "llvm/Target/TargetFrameLowering.h"
3737
3838 using namespace llvm;
3939
151151 void LocalStackSlotPass::calculateFrameObjectOffsets(MachineFunction &Fn) {
152152 // Loop over all of the stack objects, assigning sequential addresses...
153153 MachineFrameInfo *MFI = Fn.getFrameInfo();
154 const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
154 const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
155155 bool StackGrowsDown =
156 TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
156 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
157157 int64_t Offset = 0;
158158 unsigned MaxAlign = 0;
159159
226226
227227 MachineFrameInfo *MFI = Fn.getFrameInfo();
228228 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
229 const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
229 const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
230230 bool StackGrowsDown =
231 TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
231 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
232232
233233 // Collect all of the instructions in the block that reference
234234 // a frame index. Also store the frame index referenced to ease later
3232 #include "llvm/Target/TargetData.h"
3333 #include "llvm/Target/TargetLowering.h"
3434 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetFrameLowering.h"
3636 #include "llvm/ADT/SmallString.h"
3737 #include "llvm/ADT/STLExtras.h"
3838 #include "llvm/Support/GraphWriter.h"
5959 else
6060 RegInfo = 0;
6161 MFInfo = 0;
62 FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameInfo());
62 FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameLowering());
6363 if (Fn->hasFnAttr(Attribute::StackAlignment))
6464 FrameInfo->setMaxAlignment(Attribute::getStackAlignmentFromAttrs(
6565 Fn->getAttributes().getFnAttributes()));
491491 void MachineFrameInfo::print(const MachineFunction &MF, raw_ostream &OS) const{
492492 if (Objects.empty()) return;
493493
494 const TargetFrameInfo *FI = MF.getTarget().getFrameInfo();
494 const TargetFrameLowering *FI = MF.getTarget().getFrameLowering();
495495 int ValOffset = (FI ? FI->getOffsetOfLocalArea() : 0);
496496
497497 OS << "Frame Objects:\n";
2929 #include "llvm/CodeGen/RegisterScavenging.h"
3030 #include "llvm/Target/TargetMachine.h"
3131 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Target/TargetFrameInfo.h"
32 #include "llvm/Target/TargetFrameLowering.h"
3333 #include "llvm/Target/TargetInstrInfo.h"
3434 #include "llvm/Support/CommandLine.h"
3535 #include "llvm/Support/Compiler.h"
6565 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
6666 const Function* F = Fn.getFunction();
6767 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
68 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
68 const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
6969
7070 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
7171 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
144144 /// pseudo instructions.
145145 void PEI::calculateCallsInformation(MachineFunction &Fn) {
146146 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
147 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
147 const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
148148 MachineFrameInfo *MFI = Fn.getFrameInfo();
149149
150150 unsigned MaxCallFrameSize = 0;
198198 /// registers.
199199 void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) {
200200 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
201 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
201 const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
202202 MachineFrameInfo *MFI = Fn.getFrameInfo();
203203
204204 // Get the callee saved register list...
237237 return; // Early exit if no callee saved registers are modified!
238238
239239 unsigned NumFixedSpillSlots;
240 const TargetFrameInfo::SpillSlot *FixedSpillSlots =
240 const TargetFrameLowering::SpillSlot *FixedSpillSlots =
241241 TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots);
242242
243243 // Now that we know which registers need to be saved and restored, allocate
255255
256256 // Check to see if this physreg must be spilled to a particular stack slot
257257 // on this target.
258 const TargetFrameInfo::SpillSlot *FixedSlot = FixedSpillSlots;
258 const TargetFrameLowering::SpillSlot *FixedSlot = FixedSpillSlots;
259259 while (FixedSlot != FixedSpillSlots+NumFixedSpillSlots &&
260260 FixedSlot->Reg != Reg)
261261 ++FixedSlot;
298298 return;
299299
300300 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
301 const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo();
301 const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering();
302302 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
303303 MachineBasicBlock::iterator I;
304304
489489 /// abstract stack objects.
490490 ///
491491 void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
492 const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
492 const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
493493
494494 bool StackGrowsDown =
495 TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
495 TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
496496
497497 // Loop over all of the stack objects, assigning sequential addresses...
498498 MachineFrameInfo *MFI = Fn.getFrameInfo();
681681 /// prolog and epilog code to the function.
682682 ///
683683 void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
684 const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
684 const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering();
685685
686686 // Add prologue to the function...
687687 TFI.emitPrologue(Fn);
703703 const TargetMachine &TM = Fn.getTarget();
704704 assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!");
705705 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
706 const TargetFrameInfo *TFI = TM.getFrameInfo();
706 const TargetFrameLowering *TFI = TM.getFrameLowering();
707707 bool StackGrowsDown =
708 TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
708 TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown;
709709 int FrameSetupOpcode = TRI.getCallFrameSetupOpcode();
710710 int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode();
711711
2424 #include "llvm/CodeGen/PseudoSourceValue.h"
2525 #include "llvm/Analysis/AliasAnalysis.h"
2626 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetFrameInfo.h"
2827 #include "llvm/Target/TargetLowering.h"
2928 #include "llvm/Target/TargetMachine.h"
3029 #include "llvm/Target/TargetOptions.h"
2828 #include "llvm/CodeGen/MachineRegisterInfo.h"
2929 #include "llvm/Target/TargetRegisterInfo.h"
3030 #include "llvm/Target/TargetData.h"
31 #include "llvm/Target/TargetFrameInfo.h"
3231 #include "llvm/Target/TargetInstrInfo.h"
3332 #include "llvm/Target/TargetLowering.h"
3433 #include "llvm/Target/TargetOptions.h"
1818 #include "llvm/CodeGen/MachineModuleInfo.h"
1919 #include "llvm/CodeGen/PseudoSourceValue.h"
2020 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetFrameLowering.h"
2222 #include "llvm/Target/TargetLowering.h"
2323 #include "llvm/Target/TargetData.h"
2424 #include "llvm/Target/TargetMachine.h"
17181718 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
17191719 Chain = SP.getValue(1);
17201720 unsigned Align = cast(Tmp3)->getZExtValue();
1721 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1721 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
17221722 if (Align > StackAlign)
17231723 SP = DAG.getNode(ISD::AND, dl, VT, SP,
17241724 DAG.getConstant(-(uint64_t)Align, VT));
3030 #include "llvm/CodeGen/PseudoSourceValue.h"
3131 #include "llvm/Target/TargetRegisterInfo.h"
3232 #include "llvm/Target/TargetData.h"
33 #include "llvm/Target/TargetFrameInfo.h"
3433 #include "llvm/Target/TargetLowering.h"
3534 #include "llvm/Target/TargetSelectionDAGInfo.h"
3635 #include "llvm/Target/TargetOptions.h"
4444 #include "llvm/CodeGen/SelectionDAG.h"
4545 #include "llvm/Analysis/DebugInfo.h"
4646 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameInfo.h"
47 #include "llvm/Target/TargetFrameLowering.h"
4848 #include "llvm/Target/TargetInstrInfo.h"
4949 #include "llvm/Target/TargetIntrinsicInfo.h"
5050 #include "llvm/Target/TargetLowering.h"
29732973 // Handle alignment. If the requested alignment is less than or equal to
29742974 // the stack alignment, ignore it. If the size is greater than or equal to
29752975 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2976 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2976 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
29772977 if (Align <= StackAlign)
29782978 Align = 0;
29792979
2525 #include "llvm/MC/MCSymbol.h"
2626 #include "llvm/Target/TargetData.h"
2727 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetFrameLowering.h"
2929 #include "llvm/Target/TargetMachine.h"
3030 #include "llvm/Target/TargetRegisterInfo.h"
3131 using namespace llvm;
4242
4343 const TargetMachine& TM = F.getTarget();
4444 TD = TM.getTargetData();
45 stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection();
45 stackGrowthDirection = TM.getFrameLowering()->getStackGrowthDirection();
4646 RI = TM.getRegisterInfo();
47 TFI = TM.getFrameInfo();
47 TFI = TM.getFrameLowering();
4848 JCE = &jce;
4949
5050 unsigned char* ExceptionTable = EmitExceptionTable(&F, StartFunction,
6666 JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr,
6767 const std::vector &Moves) const {
6868 unsigned PointerSize = TD->getPointerSize();
69 int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
69 int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ?
7070 PointerSize : -PointerSize;
7171 MCSymbol *BaseLabel = 0;
7272
481481 unsigned char*
482482 JITDwarfEmitter::EmitCommonEHFrame(const Function* Personality) const {
483483 unsigned PointerSize = TD->getPointerSize();
484 int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ?
484 int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ?
485485 PointerSize : -PointerSize;
486486
487487 unsigned char* StartCommonPtr = (unsigned char*)JCE->getCurrentPCValue();
2222 class MachineModuleInfo;
2323 class MachineMove;
2424 class TargetData;
25 class TargetFrameInfo;
25 class TargetFrameLowering;
2626 class TargetMachine;
2727 class TargetRegisterInfo;
2828
3030 const TargetData* TD;
3131 JITCodeEmitter* JCE;
3232 const TargetRegisterInfo* RI;
33 const TargetFrameInfo *TFI;
33 const TargetFrameLowering *TFI;
3434 MachineModuleInfo* MMI;
3535 JIT& Jit;
3636 bool stackGrowthDirection;
432432 MCContext &context = streamer.getContext();
433433 const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
434434 int size = asmInfo.getPointerSize();
435 if (asmInfo.getStackGrowthDirection() == TargetFrameInfo::StackGrowsUp)
435 if (asmInfo.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp)
436436 return size;
437437 else
438438 return -size;
1414 #include "ARMAddressingModes.h"
1515 #include "ARMBaseInstrInfo.h"
1616 #include "ARMBaseRegisterInfo.h"
17 #include "ARMFrameInfo.h"
17 #include "ARMFrameLowering.h"
1818 #include "ARMInstrInfo.h"
1919 #include "ARMMachineFunctionInfo.h"
2020 #include "ARMSubtarget.h"
3232 #include "llvm/Support/Debug.h"
3333 #include "llvm/Support/ErrorHandling.h"
3434 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetFrameLowering.h"
3636 #include "llvm/Target/TargetMachine.h"
3737 #include "llvm/Target/TargetOptions.h"
3838 #include "llvm/ADT/BitVector.h"
8585
8686 BitVector ARMBaseRegisterInfo::
8787 getReservedRegs(const MachineFunction &MF) const {
88 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
88 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
8989
9090 // FIXME: avoid re-calculating this everytime.
9191 BitVector Reserved(getNumRegs());
104104
105105 bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
106106 unsigned Reg) const {
107 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
107 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
108108
109109 switch (Reg) {
110110 default: break;
353353 ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354354 unsigned HintType, unsigned HintReg,
355355 const MachineFunction &MF) const {
356 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
356 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
357357 // Alternative register allocation orders when favoring even / odd registers
358358 // of register pairs.
359359
574574 needsStackRealignment(const MachineFunction &MF) const {
575575 const MachineFrameInfo *MFI = MF.getFrameInfo();
576576 const Function *F = MF.getFunction();
577 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
577 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
578578 bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
579579 F->hasFnAttr(Attribute::StackAlignment));
580580
596596
597597 unsigned
598598 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
599 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
599 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
600600
601601 if (TFI->hasFP(MF))
602602 return FramePtr;
851851 void ARMBaseRegisterInfo::
852852 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
853853 MachineBasicBlock::iterator I) const {
854 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
854 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
855855 if (!TFI->hasReservedCallFrame(MF)) {
856856 // If we have alloca, convert as follows:
857857 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
863863 // We need to keep the stack aligned properly. To do this, we round the
864864 // amount of space needed for the outgoing arguments up to the next
865865 // alignment boundary.
866 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
866 unsigned Align = TFI->getStackAlignment();
867867 Amount = (Amount+Align-1)/Align*Align;
868868
869869 ARMFunctionInfo *AFI = MF.getInfo();
983983 // Note that the incoming offset is based on the SP value at function entry,
984984 // so it'll be negative.
985985 MachineFunction &MF = *MI->getParent()->getParent();
986 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
986 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
987987 MachineFrameInfo *MFI = MF.getFrameInfo();
988988 ARMFunctionInfo *AFI = MF.getInfo();
989989
10101010 // The FP is only available if there is no dynamic realignment. We
10111011 // don't know for sure yet whether we'll need that, so we guess based
10121012 // on whether there are any local variables that would trigger it.
1013 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1013 unsigned StackAlign = TFI->getStackAlignment();
10141014 if (TFI->hasFP(MF) &&
10151015 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
10161016 if (isFrameOffsetLegal(MI, FPOffset))
11541154 MachineInstr &MI = *II;
11551155 MachineBasicBlock &MBB = *MI.getParent();
11561156 MachineFunction &MF = *MBB.getParent();
1157 const ARMFrameInfo *TFI =
1158 static_cast(MF.getTarget().getFrameInfo());
1157 const ARMFrameLowering *TFI =
1158 static_cast(MF.getTarget().getFrameLowering());
11591159 ARMFunctionInfo *AFI = MF.getInfo();
11601160 assert(!AFI->isThumb1OnlyFunction() &&
11611161 "This eliminateFrameIndex does not support Thumb1!");
2323 #include "llvm/CodeGen/MachineFrameInfo.h"
2424 #include "llvm/CodeGen/MachineFunctionPass.h"
2525 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetFrameLowering.h"
2727 #include "llvm/Target/TargetRegisterInfo.h"
2828 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
2929 using namespace llvm;
638638 ARMFunctionInfo *AFI = MF.getInfo();
639639 int32_t NumBytes = AFI->getFramePtrSpillOffset();
640640 unsigned FramePtr = RI.getFrameRegister(MF);
641 assert(MF.getTarget().getFrameInfo()->hasFP(MF) &&
641 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
642642 "base pointer without frame pointer?");
643643
644644 if (AFI->isThumb2Function()) {
+0
-1012
lib/Target/ARM/ARMFrameInfo.cpp less more
None //=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMFrameInfo.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/RegisterScavenging.h"
22 #include "llvm/Target/TargetOptions.h"
23
24 using namespace llvm;
25
26 /// hasFP - Return true if the specified function should have a dedicated frame
27 /// pointer register. This is true if the function has variable sized allocas
28 /// or if frame pointer elimination is disabled.
29 ///
30 bool ARMFrameInfo::hasFP(const MachineFunction &MF) const {
31 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
32
33 // Mac OS X requires FP not to be clobbered for backtracing purpose.
34 if (STI.isTargetDarwin())
35 return true;
36
37 const MachineFrameInfo *MFI = MF.getFrameInfo();
38 // Always eliminate non-leaf frame pointers.
39 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
40 RegInfo->needsStackRealignment(MF) ||
41 MFI->hasVarSizedObjects() ||
42 MFI->isFrameAddressTaken());
43 }
44
45 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
46 // not required, we reserve argument space for call sites in the function
47 // immediately on entry to the current function. This eliminates the need for
48 // add/sub sp brackets around call sites. Returns true if the call frame is
49 // included as part of the stack frame.
50 bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
51 const MachineFrameInfo *FFI = MF.getFrameInfo();
52 unsigned CFSize = FFI->getMaxCallFrameSize();
53 // It's not always a good idea to include the call frame as part of the
54 // stack frame. ARM (especially Thumb) has small immediate offset to
55 // address the stack frame. So a large call frame can cause poor codegen
56 // and may even makes it impossible to scavenge a register.
57 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
58 return false;
59
60 return !MF.getFrameInfo()->hasVarSizedObjects();
61 }
62
63 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
64 // call frame pseudos can be simplified. Unlike most targets, having a FP
65 // is not sufficient here since we still may reference some objects via SP
66 // even when FP is available in Thumb2 mode.
67 bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
68 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
69 }
70
71 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
72 for (unsigned i = 0; CSRegs[i]; ++i)
73 if (Reg == CSRegs[i])
74 return true;
75 return false;
76 }
77
78 static bool isCSRestore(MachineInstr *MI,
79 const ARMBaseInstrInfo &TII,
80 const unsigned *CSRegs) {
81 // Integer spill area is handled with "pop".
82 if (MI->getOpcode() == ARM::LDMIA_RET ||
83 MI->getOpcode() == ARM::t2LDMIA_RET ||
84 MI->getOpcode() == ARM::LDMIA_UPD ||
85 MI->getOpcode() == ARM::t2LDMIA_UPD ||
86 MI->getOpcode() == ARM::VLDMDIA_UPD) {
87 // The first two operands are predicates. The last two are
88 // imp-def and imp-use of SP. Check everything in between.
89 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
90 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
91 return false;
92 return true;
93 }
94 if ((MI->getOpcode() == ARM::LDR_POST ||
95 MI->getOpcode() == ARM::t2LDR_POST) &&
96 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
97 MI->getOperand(1).getReg() == ARM::SP)
98 return true;
99
100 return false;
101 }
102
103 static void
104 emitSPUpdate(bool isARM,
105 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
106 DebugLoc dl, const ARMBaseInstrInfo &TII,
107 int NumBytes,
108 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
109 if (isARM)
110 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
111 Pred, PredReg, TII);
112 else
113 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
114 Pred, PredReg, TII);
115 }
116
117 void ARMFrameInfo::emitPrologue(MachineFunction &MF) const {
118 MachineBasicBlock &MBB = MF.front();
119 MachineBasicBlock::iterator MBBI = MBB.begin();
120 MachineFrameInfo *MFI = MF.getFrameInfo();
121 ARMFunctionInfo *AFI = MF.getInfo();
122 const ARMBaseRegisterInfo *RegInfo =
123 static_cast(MF.getTarget().getRegisterInfo());
124 const ARMBaseInstrInfo &TII =
125 *static_cast(MF.getTarget().getInstrInfo());
126 assert(!AFI->isThumb1OnlyFunction() &&
127 "This emitPrologue does not support Thumb1!");
128 bool isARM = !AFI->isThumbFunction();
129 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
130 unsigned NumBytes = MFI->getStackSize();
131 const std::vector &CSI = MFI->getCalleeSavedInfo();
132 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
133 unsigned FramePtr = RegInfo->getFrameRegister(MF);
134
135 // Determine the sizes of each callee-save spill areas and record which frame
136 // belongs to which callee-save spill areas.
137 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
138 int FramePtrSpillFI = 0;
139
140 // Allocate the vararg register save area. This is not counted in NumBytes.
141 if (VARegSaveSize)
142 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
143
144 if (!AFI->hasStackFrame()) {
145 if (NumBytes != 0)
146 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
147 return;
148 }
149
150 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
151 unsigned Reg = CSI[i].getReg();
152 int FI = CSI[i].getFrameIdx();
153 switch (Reg) {
154 case ARM::R4:
155 case ARM::R5:
156 case ARM::R6:
157 case ARM::R7:
158 case ARM::LR:
159 if (Reg == FramePtr)
160 FramePtrSpillFI = FI;
161 AFI->addGPRCalleeSavedArea1Frame(FI);
162 GPRCS1Size += 4;
163 break;
164 case ARM::R8:
165 case ARM::R9:
166 case ARM::R10:
167 case ARM::R11:
168 if (Reg == FramePtr)
169 FramePtrSpillFI = FI;
170 if (STI.isTargetDarwin()) {
171 AFI->addGPRCalleeSavedArea2Frame(FI);
172 GPRCS2Size += 4;
173 } else {
174 AFI->addGPRCalleeSavedArea1Frame(FI);
175 GPRCS1Size += 4;
176 }
177 break;
178 default:
179 AFI->addDPRCalleeSavedAreaFrame(FI);
180 DPRCSSize += 8;
181 }
182 }
183
184 // Move past area 1.
185 if (GPRCS1Size > 0) MBBI++;
186
187 // Set FP to point to the stack slot that contains the previous FP.
188 // For Darwin, FP is R7, which has now been stored in spill area 1.
189 // Otherwise, if this is not Darwin, all the callee-saved registers go
190 // into spill area 1, including the FP in R11. In either case, it is
191 // now safe to emit this assignment.
192 bool HasFP = hasFP(MF);
193 if (HasFP) {
194 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
195 MachineInstrBuilder MIB =
196 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
197 .addFrameIndex(FramePtrSpillFI).addImm(0);
198 AddDefaultCC(AddDefaultPred(MIB));
199 }
200
201 // Move past area 2.
202 if (GPRCS2Size > 0) MBBI++;
203
204 // Determine starting offsets of spill areas.
205 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
206 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
207 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
208 if (HasFP)
209 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
210 NumBytes);
211 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
212 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
213 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
214
215 // Move past area 3.
216 if (DPRCSSize > 0) MBBI++;
217
218 NumBytes = DPRCSOffset;
219 if (NumBytes) {
220 // Adjust SP after all the callee-save spills.
221 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
222 if (HasFP && isARM)
223 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
224 // Note it's not safe to do this in Thumb2 mode because it would have
225 // taken two instructions:
226 // mov sp, r7
227 // sub sp, #24
228 // If an interrupt is taken between the two instructions, then sp is in
229 // an inconsistent state (pointing to the middle of callee-saved area).
230 // The interrupt handler can end up clobbering the registers.
231 AFI->setShouldRestoreSPFromFP(true);
232 }
233
234 if (STI.isTargetELF() && hasFP(MF))
235 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
236 AFI->getFramePtrSpillOffset());
237
238 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
239 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
240 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
241
242 // If we need dynamic stack realignment, do it here. Be paranoid and make
243 // sure if we also have VLAs, we have a base pointer for frame access.
244 if (RegInfo->needsStackRealignment(MF)) {
245 unsigned MaxAlign = MFI->getMaxAlignment();
246 assert (!AFI->isThumb1OnlyFunction());
247 if (!AFI->isThumbFunction()) {
248 // Emit bic sp, sp, MaxAlign
249 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
250 TII.get(ARM::BICri), ARM::SP)
251 .addReg(ARM::SP, RegState::Kill)
252 .addImm(MaxAlign-1)));
253 } else {
254 // We cannot use sp as source/dest register here, thus we're emitting the
255 // following sequence:
256 // mov r4, sp
257 // bic r4, r4, MaxAlign
258 // mov sp, r4
259 // FIXME: It will be better just to find spare register here.
260 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
261 .addReg(ARM::SP, RegState::Kill);
262 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
263 TII.get(ARM::t2BICri), ARM::R4)
264 .addReg(ARM::R4, RegState::Kill)
265 .addImm(MaxAlign-1)));
266 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
267 .addReg(ARM::R4, RegState::Kill);
268 }
269
270 AFI->setShouldRestoreSPFromFP(true);
271 }
272
273 // If we need a base pointer, set it up here. It's whatever the value
274 // of the stack pointer is at this point. Any variable size objects
275 // will be allocated after this, so we can still use the base pointer
276 // to reference locals.
277 if (RegInfo->hasBasePointer(MF)) {
278 if (isARM)
279 BuildMI(MBB, MBBI, dl,
280 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
281 .addReg(ARM::SP)
282 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
283 else
284 BuildMI(MBB, MBBI, dl,
285 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
286 .addReg(ARM::SP);
287 }
288
289 // If the frame has variable sized objects then the epilogue must restore
290 // the sp from fp.
291 if (MFI->hasVarSizedObjects())
292 AFI->setShouldRestoreSPFromFP(true);
293 }
294
295 void ARMFrameInfo::emitEpilogue(MachineFunction &MF,
296 MachineBasicBlock &MBB) const {
297 MachineBasicBlock::iterator MBBI = prior(MBB.end());
298 assert(MBBI->getDesc().isReturn() &&
299 "Can only insert epilog into returning blocks");
300 unsigned RetOpcode = MBBI->getOpcode();
301 DebugLoc dl = MBBI->getDebugLoc();
302 MachineFrameInfo *MFI = MF.getFrameInfo();
303 ARMFunctionInfo *AFI = MF.getInfo();
304 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
305 const ARMBaseInstrInfo &TII =
306 *static_cast(MF.getTarget().getInstrInfo());
307 assert(!AFI->isThumb1OnlyFunction() &&
308 "This emitEpilogue does not support Thumb1!");
309 bool isARM = !AFI->isThumbFunction();
310
311 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
312 int NumBytes = (int)MFI->getStackSize();
313 unsigned FramePtr = RegInfo->getFrameRegister(MF);
314
315 if (!AFI->hasStackFrame()) {
316 if (NumBytes != 0)
317 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
318 } else {
319 // Unwind MBBI to point to first LDR / VLDRD.
320 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
321 if (MBBI != MBB.begin()) {
322 do
323 --MBBI;
324 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
325 if (!isCSRestore(MBBI, TII, CSRegs))
326 ++MBBI;
327 }
328
329 // Move SP to start of FP callee save spill area.
330 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
331 AFI->getGPRCalleeSavedArea2Size() +
332 AFI->getDPRCalleeSavedAreaSize());
333
334 // Reset SP based on frame pointer only if the stack frame extends beyond
335 // frame pointer stack slot or target is ELF and the function has FP.
336 if (AFI->shouldRestoreSPFromFP()) {
337 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
338 if (NumBytes) {
339 if (isARM)
340 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
341 ARMCC::AL, 0, TII);
342 else {
343 // It's not possible to restore SP from FP in a single instruction.
344 // For Darwin, this looks like:
345 // mov sp, r7
346 // sub sp, #24
347 // This is bad, if an interrupt is taken after the mov, sp is in an
348 // inconsistent state.
349 // Use the first callee-saved register as a scratch register.
350 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
351 "No scratch register to restore SP from FP!");
352 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
353 ARMCC::AL, 0, TII);
354 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
355 .addReg(ARM::R4);
356 }
357 } else {
358 // Thumb2 or ARM.
359 if (isARM)
360 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
361 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
362 else
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
364 .addReg(FramePtr);
365 }
366 } else if (NumBytes)
367 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
368
369 // Increment past our save areas.
370 if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
371 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
372 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
373 }
374
375 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
376 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
377 // Tail call return: adjust the stack pointer and jump to callee.
378 MBBI = prior(MBB.end());
379 MachineOperand &JumpTarget = MBBI->getOperand(0);
380
381 // Jump to label or value in register.
382 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
383 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
384 ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)
385 : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND);
386 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
387 if (JumpTarget.isGlobal())
388 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
389 JumpTarget.getTargetFlags());
390 else {
391 assert(JumpTarget.isSymbol());
392 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
393 JumpTarget.getTargetFlags());
394 }
395 } else if (RetOpcode == ARM::TCRETURNri) {
396 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
397 addReg(JumpTarget.getReg(), RegState::Kill);
398 } else if (RetOpcode == ARM::TCRETURNriND) {
399 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
400 addReg(JumpTarget.getReg(), RegState::Kill);
401 }
402
403 MachineInstr *NewMI = prior(MBBI);
404 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
405 NewMI->addOperand(MBBI->getOperand(i));
406
407 // Delete the pseudo instruction TCRETURN.
408 MBB.erase(MBBI);
409 }
410
411 if (VARegSaveSize)
412 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
413 }
414
415 // Provide a base+offset reference to an FI slot for debug info. It's the
416 // same as what we use for resolving the code-gen references for now.
417 // FIXME: This can go wrong when references are SP-relative and simple call
418 // frames aren't used.
419 int
420 ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
421 unsigned &FrameReg) const {
422 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
423 }
424
425 int
426 ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF,
427 int FI,
428 unsigned &FrameReg,
429 int SPAdj) const {
430 const MachineFrameInfo *MFI = MF.getFrameInfo();
431 const ARMBaseRegisterInfo *RegInfo =
432 static_cast(MF.getTarget().getRegisterInfo());
433 const ARMFunctionInfo *AFI = MF.getInfo();
434 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
435 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
436 bool isFixed = MFI->isFixedObjectIndex(FI);
437
438 FrameReg = ARM::SP;
439 Offset += SPAdj;
440 if (AFI->isGPRCalleeSavedArea1Frame(FI))
441 return Offset - AFI->getGPRCalleeSavedArea1Offset();
442 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
443 return Offset - AFI->getGPRCalleeSavedArea2Offset();
444 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
445 return Offset - AFI->getDPRCalleeSavedAreaOffset();
446
447 // When dynamically realigning the stack, use the frame pointer for
448 // parameters, and the stack/base pointer for locals.
449 if (RegInfo->needsStackRealignment(MF)) {
450 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
451 if (isFixed) {
452 FrameReg = RegInfo->getFrameRegister(MF);
453 Offset = FPOffset;
454 } else if (MFI->hasVarSizedObjects()) {
455 assert(RegInfo->hasBasePointer(MF) &&
456 "VLAs and dynamic stack alignment, but missing base pointer!");
457 FrameReg = RegInfo->getBaseRegister();
458 }
459 return Offset;
460 }
461
462 // If there is a frame pointer, use it when we can.
463 if (hasFP(MF) && AFI->hasStackFrame()) {
464 // Use frame pointer to reference fixed objects. Use it for locals if
465 // there are VLAs (and thus the SP isn't reliable as a base).
466 if (isFixed || (MFI->hasVarSizedObjects() &&
467 !RegInfo->hasBasePointer(MF))) {
468 FrameReg = RegInfo->getFrameRegister(MF);
469 return FPOffset;
470 } else if (MFI->hasVarSizedObjects()) {
471 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
472 // Try to use the frame pointer if we can, else use the base pointer
473 // since it's available. This is handy for the emergency spill slot, in
474 // particular.
475 if (AFI->isThumb2Function()) {
476 if (FPOffset >= -255 && FPOffset < 0) {
477 FrameReg = RegInfo->getFrameRegister(MF);
478 return FPOffset;
479 }
480 } else
481 FrameReg = RegInfo->getBaseRegister();
482 } else if (AFI->isThumb2Function()) {
483 // In Thumb2 mode, the negative offset is very limited. Try to avoid
484 // out of range references.
485 if (FPOffset >= -255 && FPOffset < 0) {
486 FrameReg = RegInfo->getFrameRegister(MF);
487 return FPOffset;
488 }
489 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
490 // Otherwise, use SP or FP, whichever is closer to the stack slot.
491 FrameReg = RegInfo->getFrameRegister(MF);
492 return FPOffset;
493 }
494 }
495 // Use the base pointer if we have one.
496 if (RegInfo->hasBasePointer(MF))
497 FrameReg = RegInfo->getBaseRegister();
498 return Offset;
499 }
500
501 int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
502 unsigned FrameReg;
503 return getFrameIndexReference(MF, FI, FrameReg);
504 }
505
506 void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
507 MachineBasicBlock::iterator MI,
508 const std::vector &CSI,
509 unsigned StmOpc, unsigned StrOpc, bool NoGap,
510 bool(*Func)(unsigned, bool)) const {
511 MachineFunction &MF = *MBB.getParent();
512 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
513
514 DebugLoc DL;
515 if (MI != MBB.end()) DL = MI->getDebugLoc();
516
517 SmallVector, 4> Regs;
518 unsigned i = CSI.size();
519 while (i != 0) {
520 unsigned LastReg = 0;
521 for (; i != 0; --i) {
522 unsigned Reg = CSI[i-1].getReg();
523 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
524
525 // Add the callee-saved register as live-in unless it's LR and
526 // @llvm.returnaddress is called. If LR is returned for
527 // @llvm.returnaddress then it's already added to the function and
528 // entry block live-in sets.
529 bool isKill = true;
530 if (Reg == ARM::LR) {
531 if (MF.getFrameInfo()->isReturnAddressTaken() &&
532 MF.getRegInfo().isLiveIn(Reg))
533 isKill = false;
534 }
535
536 if (isKill)
537 MBB.addLiveIn(Reg);
538
539 // If NoGap is true, push consecutive registers and then leave the rest
540 // for other instructions. e.g.
541 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
542 if (NoGap && LastReg && LastReg != Reg-1)
543 break;
544 LastReg = Reg;
545 Regs.push_back(std::make_pair(Reg, isKill));
546 }
547
548 if (Regs.empty())
549 continue;
550 if (Regs.size() > 1 || StrOpc== 0) {
551 MachineInstrBuilder MIB =
552 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
553 .addReg(ARM::SP));
554 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
555 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
556 } else if (Regs.size() == 1) {
557 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
558 ARM::SP)
559 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
560 .addReg(ARM::SP);
561 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
562 // that refactoring is complete (eventually).
563 if (StrOpc == ARM::STR_PRE) {
564 MIB.addReg(0);
565 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
566 } else
567 MIB.addImm(-4);
568 AddDefaultPred(MIB);
569 }
570 Regs.clear();
571 }
572 }
573
574 void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
575 MachineBasicBlock::iterator MI,
576 const std::vector &CSI,
577 unsigned LdmOpc, unsigned LdrOpc,
578 bool isVarArg, bool NoGap,
579 bool(*Func)(unsigned, bool)) const {
580 MachineFunction &MF = *MBB.getParent();
581 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
582 ARMFunctionInfo *AFI = MF.getInfo();
583 DebugLoc DL = MI->getDebugLoc();
584
585 SmallVector Regs;
586 unsigned i = CSI.size();
587 while (i != 0) {
588 unsigned LastReg = 0;
589 bool DeleteRet = false;
590 for (; i != 0; --i) {
591 unsigned Reg = CSI[i-1].getReg();
592 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
593
594 if (Reg == ARM::LR && !isVarArg && STI.hasV5TOps()) {
595 Reg = ARM::PC;
596 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
597 // Fold the return instruction into the LDM.
598 DeleteRet = true;
599 }
600
601 // If NoGap is true, pop consecutive registers and then leave the rest
602 // for other instructions. e.g.
603 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
604 if (NoGap && LastReg && LastReg != Reg-1)
605 break;
606
607 LastReg = Reg;
608 Regs.push_back(Reg);
609 }
610
611 if (Regs.empty())
612 continue;
613 if (Regs.size() > 1 || LdrOpc == 0) {
614 MachineInstrBuilder MIB =
615 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
616 .addReg(ARM::SP));
617 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
618 MIB.addReg(Regs[i], getDefRegState(true));
619 if (DeleteRet)
620 MI->eraseFromParent();
621 MI = MIB;
622 } else if (Regs.size() == 1) {
623 // If we adjusted the reg to PC from LR above, switch it back here. We
624 // only do that for LDM.
625 if (Regs[0] == ARM::PC)
626 Regs[0] = ARM::LR;
627 MachineInstrBuilder MIB =
628 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
629 .addReg(ARM::SP, RegState::Define)
630 .addReg(ARM::SP);
631 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
632 // that refactoring is complete (eventually).
633 if (LdrOpc == ARM::LDR_POST) {
634 MIB.addReg(0);
635 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
636 } else
637 MIB.addImm(4);
638 AddDefaultPred(MIB);
639 }
640 Regs.clear();
641 }
642 }
643
644 bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
645 MachineBasicBlock::iterator MI,
646 const std::vector &CSI,
647 const TargetRegisterInfo *TRI) const {
648 if (CSI.empty())
649 return false;
650
651 MachineFunction &MF = *MBB.getParent();
652 ARMFunctionInfo *AFI = MF.getInfo();
653 DebugLoc DL = MI->getDebugLoc();
654
655 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
656 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
657 unsigned FltOpc = ARM::VSTMDDB_UPD;
658 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register);
659 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register);
660 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register);
661
662 return true;
663 }
664
665 bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
666 MachineBasicBlock::iterator MI,
667 const std::vector &CSI,
668 const TargetRegisterInfo *TRI) const {
669 if (CSI.empty())
670 return false;
671
672 MachineFunction &MF = *MBB.getParent();
673 ARMFunctionInfo *AFI = MF.getInfo();
674 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
675 DebugLoc DL = MI->getDebugLoc();
676
677 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
678 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
679 unsigned FltOpc = ARM::VLDMDIA_UPD;
680 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
681 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
682 &isARMArea2Register);
683 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
684 &isARMArea1Register);
685
686 return true;
687 }
688
689 // FIXME: Make generic?
690 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
691 const ARMBaseInstrInfo &TII) {
692 unsigned FnSize = 0;
693 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
694 MBBI != E; ++MBBI) {
695 const MachineBasicBlock &MBB = *MBBI;
696 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
697 I != E; ++I)
698 FnSize += TII.GetInstSizeInBytes(I);
699 }
700 return FnSize;
701 }
702
703 /// estimateStackSize - Estimate and return the size of the frame.
704 /// FIXME: Make generic?
705 static unsigned estimateStackSize(MachineFunction &MF) {
706 const MachineFrameInfo *FFI = MF.getFrameInfo();
707 int Offset = 0;
708 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
709 int FixedOff = -FFI->getObjectOffset(i);
710 if (FixedOff > Offset) Offset = FixedOff;
711 }
712 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
713 if (FFI->isDeadObjectIndex(i))
714 continue;
715 Offset += FFI->getObjectSize(i);
716 unsigned Align = FFI->getObjectAlignment(i);
717 // Adjust to alignment boundary
718 Offset = (Offset+Align-1)/Align*Align;
719 }
720 return (unsigned)Offset;
721 }
722
723 /// estimateRSStackSizeLimit - Look at each instruction that references stack
724 /// frames and return the stack size limit beyond which some of these
725 /// instructions will require a scratch register during their expansion later.
726 // FIXME: Move to TII?
727 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
728 const TargetFrameInfo *TFI) {
729 const ARMFunctionInfo *AFI = MF.getInfo();
730 unsigned Limit = (1 << 12) - 1;
731 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
732 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
733 I != E; ++I) {
734 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
735 if (!I->getOperand(i).isFI()) continue;
736
737 // When using ADDri to get the address of a stack object, 255 is the
738 // largest offset guaranteed to fit in the immediate offset.
739 if (I->getOpcode() == ARM::ADDri) {
740 Limit = std::min(Limit, (1U << 8) - 1);
741 break;
742 }
743
744 // Otherwise check the addressing mode.
745 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
746 case ARMII::AddrMode3:
747 case ARMII::AddrModeT2_i8:
748 Limit = std::min(Limit, (1U << 8) - 1);
749 break;
750 case ARMII::AddrMode5:
751 case ARMII::AddrModeT2_i8s4:
752 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
753 break;
754 case ARMII::AddrModeT2_i12:
755 // i12 supports only positive offset so these will be converted to
756 // i8 opcodes. See llvm::rewriteT2FrameIndex.
757 if (TFI->hasFP(MF) && AFI->hasStackFrame())
758 Limit = std::min(Limit, (1U << 8) - 1);
759 break;
760 case ARMII::AddrMode4:
761 case ARMII::AddrMode6:
762 // Addressing modes 4 & 6 (load/store) instructions can't encode an
763 // immediate offset for stack references.
764 return 0;
765 default:
766 break;
767 }
768 break; // At most one FI per instruction
769 }
770 }
771 }
772
773 return Limit;
774 }
775
776 void
777 ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
778 RegScavenger *RS) const {
779 // This tells PEI to spill the FP as if it is any other callee-save register
780 // to take advantage the eliminateFrameIndex machinery. This also ensures it
781 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
782 // to combine multiple loads / stores.
783 bool CanEliminateFrame = true;
784 bool CS1Spilled = false;
785 bool LRSpilled = false;
786 unsigned NumGPRSpills = 0;
787 SmallVector UnspilledCS1GPRs;
788 SmallVector UnspilledCS2GPRs;
789 const ARMBaseRegisterInfo *RegInfo =
790 static_cast(MF.getTarget().getRegisterInfo());
791 const ARMBaseInstrInfo &TII =
792 *static_cast(MF.getTarget().getInstrInfo());
793 ARMFunctionInfo *AFI = MF.getInfo();
794 MachineFrameInfo *MFI = MF.getFrameInfo();
795 unsigned FramePtr = RegInfo->getFrameRegister(MF);
796
797 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
798 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
799 // since it's always posible to restore sp from fp in a single instruction.
800 // FIXME: It will be better just to find spare register here.
801 if (AFI->isThumb2Function() &&
802 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
803 MF.getRegInfo().setPhysRegUsed(ARM::R4);
804
805 // Spill LR if Thumb1 function uses variable length argument lists.
806 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
807 MF.getRegInfo().setPhysRegUsed(ARM::LR);
808
809 // Spill the BasePtr if it's used.
810 if (RegInfo->hasBasePointer(MF))
811 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
812
813 // Don't spill FP if the frame can be eliminated. This is determined
814 // by scanning the callee-save registers to see if any is used.
815 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
816 for (unsigned i = 0; CSRegs[i]; ++i) {
817 unsigned Reg = CSRegs[i];
818 bool Spilled = false;
819 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
820 AFI->setCSRegisterIsSpilled(Reg);
821 Spilled = true;
822 CanEliminateFrame = false;
823 } else {
824 // Check alias registers too.
825 for (const unsigned *Aliases =
826 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
827 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
828 Spilled = true;
829 CanEliminateFrame = false;
830 }
831 }
832 }
833
834 if (!ARM::GPRRegisterClass->contains(Reg))
835 continue;
836
837 if (Spilled) {
838 NumGPRSpills++;
839
840 if (!STI.isTargetDarwin()) {
841 if (Reg == ARM::LR)
842 LRSpilled = true;
843 CS1Spilled = true;
844 continue;
845 }
846
847 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
848 switch (Reg) {
849 case ARM::LR:
850 LRSpilled = true;
851 // Fallthrough
852 case ARM::R4: case ARM::R5:
853 case ARM::R6: case ARM::R7:
854 CS1Spilled = true;
855 break;
856 default:
857 break;
858 }
859 } else {
860 if (!STI.isTargetDarwin()) {
861 UnspilledCS1GPRs.push_back(Reg);
862 continue;
863 }
864
865 switch (Reg) {
866 case ARM::R4: case ARM::R5:
867 case ARM::R6: case ARM::R7:
868 case ARM::LR:
869 UnspilledCS1GPRs.push_back(Reg);
870 break;
871 default:
872 UnspilledCS2GPRs.push_back(Reg);
873 break;
874 }
875 }
876 }
877
878 bool ForceLRSpill = false;
879 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
880 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
881 // Force LR to be spilled if the Thumb function size is > 2048. This enables
882 // use of BL to implement far jump. If it turns out that it's not needed
883 // then the branch fix up path will undo it.
884 if (FnSize >= (1 << 11)) {
885 CanEliminateFrame = false;
886 ForceLRSpill = true;
887 }
888 }
889
890 // If any of the stack slot references may be out of range of an immediate
891 // offset, make sure a register (or a spill slot) is available for the
892 // register scavenger. Note that if we're indexing off the frame pointer, the
893 // effective stack size is 4 bytes larger since the FP points to the stack
894 // slot of the previous FP. Also, if we have variable sized objects in the
895 // function, stack slot references will often be negative, and some of
896 // our instructions are positive-offset only, so conservatively consider
897 // that case to want a spill slot (or register) as well. Similarly, if
898 // the function adjusts the stack pointer during execution and the
899 // adjustments aren't already part of our stack size estimate, our offset
900 // calculations may be off, so be conservative.
901 // FIXME: We could add logic to be more precise about negative offsets
902 // and which instructions will need a scratch register for them. Is it
903 // worth the effort and added fragility?
904 bool BigStack =
905 (RS &&
906 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
907 estimateRSStackSizeLimit(MF, this)))
908 || MFI->hasVarSizedObjects()
909 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
910
911 bool ExtraCSSpill = false;
912 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
913 AFI->setHasStackFrame(true);
914
915 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
916 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
917 if (!LRSpilled && CS1Spilled) {
918 MF.getRegInfo().setPhysRegUsed(ARM::LR);
919 AFI->setCSRegisterIsSpilled(ARM::LR);
920 NumGPRSpills++;
921 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
922 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
923 ForceLRSpill = false;
924 ExtraCSSpill = true;
925 }
926
927 if (hasFP(MF)) {
928 MF.getRegInfo().setPhysRegUsed(FramePtr);
929 NumGPRSpills++;
930 }
931
932 // If stack and double are 8-byte aligned and we are spilling an odd number
933 // of GPRs, spill one extra callee save GPR so we won't have to pad between
934 // the integer and double callee save areas.
935 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
936 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
937 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
938 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
939 unsigned Reg = UnspilledCS1GPRs[i];
940 // Don't spill high register if the function is thumb1
941 if (!AFI->isThumb1OnlyFunction() ||
942 isARMLowRegister(Reg) || Reg == ARM::LR) {
943 MF.getRegInfo().setPhysRegUsed(Reg);
944 AFI->setCSRegisterIsSpilled(Reg);
945 if (!RegInfo->isReservedReg(MF, Reg))
946 ExtraCSSpill = true;
947 break;
948 }
949 }
950 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
951 unsigned Reg = UnspilledCS2GPRs.front();
952 MF.getRegInfo().setPhysRegUsed(Reg);
953 AFI->setCSRegisterIsSpilled(Reg);
954 if (!RegInfo->isReservedReg(MF, Reg))
955 ExtraCSSpill = true;
956 }
957 }
958
959 // Estimate if we might need to scavenge a register at some point in order
960 // to materialize a stack offset. If so, either spill one additional
961 // callee-saved register or reserve a special spill slot to facilitate
962 // register scavenging. Thumb1 needs a spill slot for stack pointer
963 // adjustments also, even when the frame itself is small.
964 if (BigStack && !ExtraCSSpill) {
965 // If any non-reserved CS register isn't spilled, just spill one or two
966 // extra. That should take care of it!
967 unsigned NumExtras = TargetAlign / 4;
968 SmallVector Extras;
969 while (NumExtras && !UnspilledCS1GPRs.empty()) {
970 unsigned Reg = UnspilledCS1GPRs.back();
971 UnspilledCS1GPRs.pop_back();
972 if (!RegInfo->isReservedReg(MF, Reg) &&
973 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
974 Reg == ARM::LR)) {
975 Extras.push_back(Reg);
976 NumExtras--;
977 }
978 }
979 // For non-Thumb1 functions, also check for hi-reg CS registers
980 if (!AFI->isThumb1OnlyFunction()) {
981 while (NumExtras && !UnspilledCS2GPRs.empty()) {
982 unsigned Reg = UnspilledCS2GPRs.back();
983 UnspilledCS2GPRs.pop_back();
984 if (!RegInfo->isReservedReg(MF, Reg)) {
985 Extras.push_back(Reg);
986 NumExtras--;
987 }
988 }
989 }
990 if (Extras.size() && NumExtras == 0) {
991 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
992 MF.getRegInfo().setPhysRegUsed(Extras[i]);
993 AFI->setCSRegisterIsSpilled(Extras[i]);
994 }
995 } else if (!AFI->isThumb1OnlyFunction()) {
996 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
997 // closest to SP or frame pointer.
998 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
999 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1000 RC->getAlignment(),
1001 false));
1002 }
1003 }
1004 }
1005
1006 if (ForceLRSpill) {
1007 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1008 AFI->setCSRegisterIsSpilled(ARM::LR);
1009 AFI->setLRIsSpilledForFarJump(true);
1010 }
1011 }
+0
-73
lib/Target/ARM/ARMFrameInfo.h less more
None //===-- ARMTargetFrameInfo.h - Define TargetFrameInfo for ARM ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ARM_FRAMEINFO_H
14 #define ARM_FRAMEINFO_H
15
16 #include "ARM.h"
17 #include "ARMSubtarget.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19
20 namespace llvm {
21 class ARMSubtarget;
22
23 class ARMFrameInfo : public TargetFrameInfo {
24 protected:
25 const ARMSubtarget &STI;
26
27 public:
28 explicit ARMFrameInfo(const ARMSubtarget &sti)
29 : TargetFrameInfo(StackGrowsDown, sti.getStackAlignment(), 0, 4), STI(sti) {
30 }
31
32 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
33 /// the function.
34 void emitPrologue(MachineFunction &MF) const;
35 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
36
37 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 const std::vector &CSI,
40 const TargetRegisterInfo *TRI) const;
41
42 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator MI,
44 const std::vector &CSI,
45 const TargetRegisterInfo *TRI) const;
46
47 bool hasFP(const MachineFunction &MF) const;
48 bool hasReservedCallFrame(const MachineFunction &MF) const;
49 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
50 int getFrameIndexReference(const MachineFunction &MF, int FI,
51 unsigned &FrameReg) const;
52 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
53 unsigned &FrameReg, int SPAdj) const;
54 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
55
56 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
57 RegScavenger *RS) const;
58
59 private:
60 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
61 const std::vector &CSI, unsigned StmOpc,
62 unsigned StrOpc, bool NoGap,
63 bool(*Func)(unsigned, bool)) const;
64 void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
65 const std::vector &CSI, unsigned LdmOpc,
66 unsigned LdrOpc, bool isVarArg, bool NoGap,
67 bool(*Func)(unsigned, bool)) const;
68 };
69
70 } // End llvm namespace
71
72 #endif
0 //=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMFrameLowering.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/RegisterScavenging.h"
22 #include "llvm/Target/TargetOptions.h"
23
24 using namespace llvm;
25
26 /// hasFP - Return true if the specified function should have a dedicated frame
27 /// pointer register. This is true if the function has variable sized allocas
28 /// or if frame pointer elimination is disabled.
29 ///
30 bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
31 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
32
33 // Mac OS X requires FP not to be clobbered for backtracing purpose.
34 if (STI.isTargetDarwin())
35 return true;
36
37 const MachineFrameInfo *MFI = MF.getFrameInfo();
38 // Always eliminate non-leaf frame pointers.
39 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
40 RegInfo->needsStackRealignment(MF) ||
41 MFI->hasVarSizedObjects() ||
42 MFI->isFrameAddressTaken());
43 }
44
45 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
46 // not required, we reserve argument space for call sites in the function
47 // immediately on entry to the current function. This eliminates the need for
48 // add/sub sp brackets around call sites. Returns true if the call frame is
49 // included as part of the stack frame.
50 bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
51 const MachineFrameInfo *FFI = MF.getFrameInfo();
52 unsigned CFSize = FFI->getMaxCallFrameSize();
53 // It's not always a good idea to include the call frame as part of the
54 // stack frame. ARM (especially Thumb) has small immediate offset to
55 // address the stack frame. So a large call frame can cause poor codegen
56 // and may even makes it impossible to scavenge a register.
57 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
58 return false;
59
60 return !MF.getFrameInfo()->hasVarSizedObjects();
61 }
62
63 // canSimplifyCallFramePseudos - If there is a reserved call frame, the
64 // call frame pseudos can be simplified. Unlike most targets, having a FP
65 // is not sufficient here since we still may reference some objects via SP
66 // even when FP is available in Thumb2 mode.
67 bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const {
68 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
69 }
70
71 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
72 for (unsigned i = 0; CSRegs[i]; ++i)
73 if (Reg == CSRegs[i])
74 return true;
75 return false;
76 }
77
78 static bool isCSRestore(MachineInstr *MI,
79 const ARMBaseInstrInfo &TII,
80 const unsigned *CSRegs) {
81 // Integer spill area is handled with "pop".
82 if (MI->getOpcode() == ARM::LDMIA_RET ||
83 MI->getOpcode() == ARM::t2LDMIA_RET ||
84 MI->getOpcode() == ARM::LDMIA_UPD ||
85 MI->getOpcode() == ARM::t2LDMIA_UPD ||
86 MI->getOpcode() == ARM::VLDMDIA_UPD) {
87 // The first two operands are predicates. The last two are
88 // imp-def and imp-use of SP. Check everything in between.
89 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
90 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
91 return false;
92 return true;
93 }
94 if ((MI->getOpcode() == ARM::LDR_POST ||
95 MI->getOpcode() == ARM::t2LDR_POST) &&
96 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
97 MI->getOperand(1).getReg() == ARM::SP)
98 return true;
99
100 return false;
101 }
102
103 static void
104 emitSPUpdate(bool isARM,
105 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
106 DebugLoc dl, const ARMBaseInstrInfo &TII,
107 int NumBytes,
108 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
109 if (isARM)
110 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
111 Pred, PredReg, TII);
112 else
113 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
114 Pred, PredReg, TII);
115 }
116
117 void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
118 MachineBasicBlock &MBB = MF.front();
119 MachineBasicBlock::iterator MBBI = MBB.begin();
120 MachineFrameInfo *MFI = MF.getFrameInfo();
121 ARMFunctionInfo *AFI = MF.getInfo();
122 const ARMBaseRegisterInfo *RegInfo =
123 static_cast(MF.getTarget().getRegisterInfo());
124 const ARMBaseInstrInfo &TII =
125 *static_cast(MF.getTarget().getInstrInfo());
126 assert(!AFI->isThumb1OnlyFunction() &&
127 "This emitPrologue does not support Thumb1!");
128 bool isARM = !AFI->isThumbFunction();
129 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
130 unsigned NumBytes = MFI->getStackSize();
131 const std::vector &CSI = MFI->getCalleeSavedInfo();
132 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
133 unsigned FramePtr = RegInfo->getFrameRegister(MF);
134
135 // Determine the sizes of each callee-save spill areas and record which frame
136 // belongs to which callee-save spill areas.
137 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
138 int FramePtrSpillFI = 0;
139
140 // Allocate the vararg register save area. This is not counted in NumBytes.
141 if (VARegSaveSize)
142 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
143
144 if (!AFI->hasStackFrame()) {
145 if (NumBytes != 0)
146 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
147 return;
148 }
149
150 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
151 unsigned Reg = CSI[i].getReg();
152 int FI = CSI[i].getFrameIdx();
153 switch (Reg) {
154 case ARM::R4:
155 case ARM::R5:
156 case ARM::R6:
157 case ARM::R7:
158 case ARM::LR:
159 if (Reg == FramePtr)
160 FramePtrSpillFI = FI;
161 AFI->addGPRCalleeSavedArea1Frame(FI);
162 GPRCS1Size += 4;
163 break;
164 case ARM::R8:
165 case ARM::R9:
166 case ARM::R10:
167 case ARM::R11:
168 if (Reg == FramePtr)
169 FramePtrSpillFI = FI;
170 if (STI.isTargetDarwin()) {
171 AFI->addGPRCalleeSavedArea2Frame(FI);
172 GPRCS2Size += 4;
173 } else {
174 AFI->addGPRCalleeSavedArea1Frame(FI);
175 GPRCS1Size += 4;
176 }
177 break;
178 default:
179 AFI->addDPRCalleeSavedAreaFrame(FI);
180 DPRCSSize += 8;
181 }
182 }
183
184 // Move past area 1.
185 if (GPRCS1Size > 0) MBBI++;
186
187 // Set FP to point to the stack slot that contains the previous FP.
188 // For Darwin, FP is R7, which has now been stored in spill area 1.
189 // Otherwise, if this is not Darwin, all the callee-saved registers go
190 // into spill area 1, including the FP in R11. In either case, it is
191 // now safe to emit this assignment.
192 bool HasFP = hasFP(MF);
193 if (HasFP) {
194 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
195 MachineInstrBuilder MIB =
196 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
197 .addFrameIndex(FramePtrSpillFI).addImm(0);
198 AddDefaultCC(AddDefaultPred(MIB));
199 }
200
201 // Move past area 2.
202 if (GPRCS2Size > 0) MBBI++;
203
204 // Determine starting offsets of spill areas.
205 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
206 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
207 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
208 if (HasFP)
209 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
210 NumBytes);
211 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
212 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
213 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
214
215 // Move past area 3.
216 if (DPRCSSize > 0) MBBI++;
217
218 NumBytes = DPRCSOffset;
219 if (NumBytes) {
220 // Adjust SP after all the callee-save spills.
221 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
222 if (HasFP && isARM)
223 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
224 // Note it's not safe to do this in Thumb2 mode because it would have
225 // taken two instructions:
226 // mov sp, r7
227 // sub sp, #24
228 // If an interrupt is taken between the two instructions, then sp is in
229 // an inconsistent state (pointing to the middle of callee-saved area).
230 // The interrupt handler can end up clobbering the registers.
231 AFI->setShouldRestoreSPFromFP(true);
232 }
233
234 if (STI.isTargetELF() && hasFP(MF))
235 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
236 AFI->getFramePtrSpillOffset());
237
238 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
239 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
240 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
241
242 // If we need dynamic stack realignment, do it here. Be paranoid and make
243 // sure if we also have VLAs, we have a base pointer for frame access.
244 if (RegInfo->needsStackRealignment(MF)) {
245 unsigned MaxAlign = MFI->getMaxAlignment();
246 assert (!AFI->isThumb1OnlyFunction());
247 if (!AFI->isThumbFunction()) {
248 // Emit bic sp, sp, MaxAlign
249 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
250 TII.get(ARM::BICri), ARM::SP)
251 .addReg(ARM::SP, RegState::Kill)
252 .addImm(MaxAlign-1)));
253 } else {
254 // We cannot use sp as source/dest register here, thus we're emitting the
255 // following sequence:
256 // mov r4, sp
257 // bic r4, r4, MaxAlign
258 // mov sp, r4
259 // FIXME: It will be better just to find spare register here.
260 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
261 .addReg(ARM::SP, RegState::Kill);
262 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
263 TII.get(ARM::t2BICri), ARM::R4)
264 .addReg(ARM::R4, RegState::Kill)
265 .addImm(MaxAlign-1)));
266 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
267 .addReg(ARM::R4, RegState::Kill);
268 }
269
270 AFI->setShouldRestoreSPFromFP(true);
271 }
272
273 // If we need a base pointer, set it up here. It's whatever the value
274 // of the stack pointer is at this point. Any variable size objects
275 // will be allocated after this, so we can still use the base pointer
276 // to reference locals.
277 if (RegInfo->hasBasePointer(MF)) {
278 if (isARM)
279 BuildMI(MBB, MBBI, dl,
280 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
281 .addReg(ARM::SP)
282 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
283 else
284 BuildMI(MBB, MBBI, dl,
285 TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
286 .addReg(ARM::SP);
287 }
288
289 // If the frame has variable sized objects then the epilogue must restore
290 // the sp from fp.
291 if (MFI->hasVarSizedObjects())
292 AFI->setShouldRestoreSPFromFP(true);
293 }
294
295 void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
296 MachineBasicBlock &MBB) const {
297 MachineBasicBlock::iterator MBBI = prior(MBB.end());
298 assert(MBBI->getDesc().isReturn() &&
299 "Can only insert epilog into returning blocks");
300 unsigned RetOpcode = MBBI->getOpcode();
301 DebugLoc dl = MBBI->getDebugLoc();
302 MachineFrameInfo *MFI = MF.getFrameInfo();
303 ARMFunctionInfo *AFI = MF.getInfo();
304 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
305 const ARMBaseInstrInfo &TII =
306 *static_cast(MF.getTarget().getInstrInfo());
307 assert(!AFI->isThumb1OnlyFunction() &&
308 "This emitEpilogue does not support Thumb1!");
309 bool isARM = !AFI->isThumbFunction();
310
311 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
312 int NumBytes = (int)MFI->getStackSize();
313 unsigned FramePtr = RegInfo->getFrameRegister(MF);
314
315 if (!AFI->hasStackFrame()) {
316 if (NumBytes != 0)
317 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
318 } else {
319 // Unwind MBBI to point to first LDR / VLDRD.
320 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
321 if (MBBI != MBB.begin()) {
322 do
323 --MBBI;
324 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
325 if (!isCSRestore(MBBI, TII, CSRegs))
326 ++MBBI;
327 }
328
329 // Move SP to start of FP callee save spill area.
330 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
331 AFI->getGPRCalleeSavedArea2Size() +
332 AFI->getDPRCalleeSavedAreaSize());
333
334 // Reset SP based on frame pointer only if the stack frame extends beyond
335 // frame pointer stack slot or target is ELF and the function has FP.
336 if (AFI->shouldRestoreSPFromFP()) {
337 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
338 if (NumBytes) {
339 if (isARM)
340 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
341 ARMCC::AL, 0, TII);
342 else {
343 // It's not possible to restore SP from FP in a single instruction.
344 // For Darwin, this looks like:
345 // mov sp, r7
346 // sub sp, #24
347 // This is bad, if an interrupt is taken after the mov, sp is in an
348 // inconsistent state.
349 // Use the first callee-saved register as a scratch register.
350 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) &&
351 "No scratch register to restore SP from FP!");
352 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
353 ARMCC::AL, 0, TII);
354 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
355 .addReg(ARM::R4);
356 }
357 } else {
358 // Thumb2 or ARM.
359 if (isARM)
360 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
361 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
362 else
363 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
364 .addReg(FramePtr);
365 }
366 } else if (NumBytes)
367 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
368
369 // Increment past our save areas.
370 if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
371 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
372 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
373 }
374
375 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
376 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
377 // Tail call return: adjust the stack pointer and jump to callee.
378 MBBI = prior(MBB.end());
379 MachineOperand &JumpTarget = MBBI->getOperand(0);
380
381 // Jump to label or value in register.
382 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) {
383 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi)
384 ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)
385 : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND);
386 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
387 if (JumpTarget.isGlobal())
388 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
389 JumpTarget.getTargetFlags());
390 else {
391 assert(JumpTarget.isSymbol());
392 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
393 JumpTarget.getTargetFlags());
394 }
395 } else if (RetOpcode == ARM::TCRETURNri) {
396 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
397 addReg(JumpTarget.getReg(), RegState::Kill);
398 } else if (RetOpcode == ARM::TCRETURNriND) {
399 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
400 addReg(JumpTarget.getReg(), RegState::Kill);
401 }
402
403 MachineInstr *NewMI = prior(MBBI);
404 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
405 NewMI->addOperand(MBBI->getOperand(i));
406
407 // Delete the pseudo instruction TCRETURN.
408 MBB.erase(MBBI);
409 }
410
411 if (VARegSaveSize)
412 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
413 }
414
415 // Provide a base+offset reference to an FI slot for debug info. It's the
416 // same as what we use for resolving the code-gen references for now.
417 // FIXME: This can go wrong when references are SP-relative and simple call
418 // frames aren't used.
419 int
420 ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
421 unsigned &FrameReg) const {
422 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
423 }
424
425 int
426 ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF,
427 int FI,
428 unsigned &FrameReg,
429 int SPAdj) const {
430 const MachineFrameInfo *MFI = MF.getFrameInfo();
431 const ARMBaseRegisterInfo *RegInfo =
432 static_cast(MF.getTarget().getRegisterInfo());
433 const ARMFunctionInfo *AFI = MF.getInfo();
434 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
435 int FPOffset = Offset - AFI->getFramePtrSpillOffset();
436 bool isFixed = MFI->isFixedObjectIndex(FI);
437
438 FrameReg = ARM::SP;
439 Offset += SPAdj;
440 if (AFI->isGPRCalleeSavedArea1Frame(FI))
441 return Offset - AFI->getGPRCalleeSavedArea1Offset();
442 else if (AFI->isGPRCalleeSavedArea2Frame(FI))
443 return Offset - AFI->getGPRCalleeSavedArea2Offset();
444 else if (AFI->isDPRCalleeSavedAreaFrame(FI))
445 return Offset - AFI->getDPRCalleeSavedAreaOffset();
446
447 // When dynamically realigning the stack, use the frame pointer for
448 // parameters, and the stack/base pointer for locals.
449 if (RegInfo->needsStackRealignment(MF)) {
450 assert (hasFP(MF) && "dynamic stack realignment without a FP!");
451 if (isFixed) {
452 FrameReg = RegInfo->getFrameRegister(MF);
453 Offset = FPOffset;
454 } else if (MFI->hasVarSizedObjects()) {
455 assert(RegInfo->hasBasePointer(MF) &&
456 "VLAs and dynamic stack alignment, but missing base pointer!");
457 FrameReg = RegInfo->getBaseRegister();
458 }
459 return Offset;
460 }
461
462 // If there is a frame pointer, use it when we can.
463 if (hasFP(MF) && AFI->hasStackFrame()) {
464 // Use frame pointer to reference fixed objects. Use it for locals if
465 // there are VLAs (and thus the SP isn't reliable as a base).
466 if (isFixed || (MFI->hasVarSizedObjects() &&
467 !RegInfo->hasBasePointer(MF))) {
468 FrameReg = RegInfo->getFrameRegister(MF);
469 return FPOffset;
470 } else if (MFI->hasVarSizedObjects()) {
471 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
472 // Try to use the frame pointer if we can, else use the base pointer
473 // since it's available. This is handy for the emergency spill slot, in
474 // particular.
475 if (AFI->isThumb2Function()) {
476 if (FPOffset >= -255 && FPOffset < 0) {
477 FrameReg = RegInfo->getFrameRegister(MF);
478 return FPOffset;
479 }
480 } else
481 FrameReg = RegInfo->getBaseRegister();
482 } else if (AFI->isThumb2Function()) {
483 // In Thumb2 mode, the negative offset is very limited. Try to avoid
484 // out of range references.
485 if (FPOffset >= -255 && FPOffset < 0) {
486 FrameReg = RegInfo->getFrameRegister(MF);
487 return FPOffset;
488 }
489 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
490 // Otherwise, use SP or FP, whichever is closer to the stack slot.
491 FrameReg = RegInfo->getFrameRegister(MF);
492 return FPOffset;
493 }
494 }
495 // Use the base pointer if we have one.
496 if (RegInfo->hasBasePointer(MF))
497 FrameReg = RegInfo->getBaseRegister();
498 return Offset;
499 }
500
501 int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
502 unsigned FrameReg;
503 return getFrameIndexReference(MF, FI, FrameReg);
504 }
505
506 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
507 MachineBasicBlock::iterator MI,
508 const std::vector &CSI,
509 unsigned StmOpc, unsigned StrOpc, bool NoGap,
510 bool(*Func)(unsigned, bool)) const {
511 MachineFunction &MF = *MBB.getParent();
512 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
513
514 DebugLoc DL;
515 if (MI != MBB.end()) DL = MI->getDebugLoc();
516
517 SmallVector, 4> Regs;
518 unsigned i = CSI.size();
519 while (i != 0) {
520 unsigned LastReg = 0;
521 for (; i != 0; --i) {
522 unsigned Reg = CSI[i-1].getReg();
523 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
524
525 // Add the callee-saved register as live-in unless it's LR and
526 // @llvm.returnaddress is called. If LR is returned for
527 // @llvm.returnaddress then it's already added to the function and
528 // entry block live-in sets.
529 bool isKill = true;
530 if (Reg == ARM::LR) {
531 if (MF.getFrameInfo()->isReturnAddressTaken() &&
532 MF.getRegInfo().isLiveIn(Reg))
533 isKill = false;
534 }
535
536 if (isKill)
537 MBB.addLiveIn(Reg);
538
539 // If NoGap is true, push consecutive registers and then leave the rest
540 // for other instructions. e.g.
541 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
542 if (NoGap && LastReg && LastReg != Reg-1)
543 break;
544 LastReg = Reg;
545 Regs.push_back(std::make_pair(Reg, isKill));
546 }
547
548 if (Regs.empty())
549 continue;
550 if (Regs.size() > 1 || StrOpc== 0) {
551 MachineInstrBuilder MIB =
552 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
553 .addReg(ARM::SP));
554 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
555 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
556 } else if (Regs.size() == 1) {
557 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
558 ARM::SP)
559 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
560 .addReg(ARM::SP);
561 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
562 // that refactoring is complete (eventually).
563 if (StrOpc == ARM::STR_PRE) {
564 MIB.addReg(0);
565 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
566 } else
567 MIB.addImm(-4);
568 AddDefaultPred(MIB);
569 }
570 Regs.clear();
571 }
572 }
573
574 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
575 MachineBasicBlock::iterator MI,
576 const std::vector &CSI,
577 unsigned LdmOpc, unsigned LdrOpc,
578 bool isVarArg, bool NoGap,
579 bool(*Func)(unsigned, bool)) const {
580 MachineFunction &MF = *MBB.getParent();
581 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
582 ARMFunctionInfo *AFI = MF.getInfo();
583 DebugLoc DL = MI->getDebugLoc();
584
585 SmallVector Regs;
586 unsigned i = CSI.size();
587 while (i != 0) {
588 unsigned LastReg = 0;
589 bool DeleteRet = false;
590 for (; i != 0; --i) {
591 unsigned Reg = CSI[i-1].getReg();
592 if (!(Func)(Reg, STI.isTargetDarwin())) continue;
593
594 if (Reg == ARM::LR && !isVarArg && STI.hasV5TOps()) {
595 Reg = ARM::PC;
596 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
597 // Fold the return instruction into the LDM.
598 DeleteRet = true;
599 }
600
601 // If NoGap is true, pop consecutive registers and then leave the rest
602 // for other instructions. e.g.
603 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
604 if (NoGap && LastReg && LastReg != Reg-1)
605 break;
606
607 LastReg = Reg;
608 Regs.push_back(Reg);
609 }
610
611 if (Regs.empty())
612 continue;
613 if (Regs.size() > 1 || LdrOpc == 0) {
614 MachineInstrBuilder MIB =
615 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
616 .addReg(ARM::SP));
617 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
618 MIB.addReg(Regs[i], getDefRegState(true));
619 if (DeleteRet)
620 MI->eraseFromParent();
621 MI = MIB;
622 } else if (Regs.size() == 1) {
623 // If we adjusted the reg to PC from LR above, switch it back here. We
624 // only do that for LDM.
625 if (Regs[0] == ARM::PC)
626 Regs[0] = ARM::LR;
627 MachineInstrBuilder MIB =
628 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
629 .addReg(ARM::SP, RegState::Define)
630 .addReg(ARM::SP);
631 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
632 // that refactoring is complete (eventually).
633 if (LdrOpc == ARM::LDR_POST) {
634 MIB.addReg(0);
635 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
636 } else
637 MIB.addImm(4);
638 AddDefaultPred(MIB);
639 }
640 Regs.clear();
641 }
642 }
643
644 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
645 MachineBasicBlock::iterator MI,
646 const std::vector &CSI,
647 const TargetRegisterInfo *TRI) const {
648 if (CSI.empty())
649 return false;
650
651 MachineFunction &MF = *MBB.getParent();
652 ARMFunctionInfo *AFI = MF.getInfo();
653 DebugLoc DL = MI->getDebugLoc();
654
655 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
656 unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
657 unsigned FltOpc = ARM::VSTMDDB_UPD;
658 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register);
659 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register);
660 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register);
661
662 return true;
663 }
664
665 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
666 MachineBasicBlock::iterator MI,
667 const std::vector &CSI,
668 const TargetRegisterInfo *TRI) const {
669 if (CSI.empty())
670 return false;
671
672 MachineFunction &MF = *MBB.getParent();
673 ARMFunctionInfo *AFI = MF.getInfo();
674 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
675 DebugLoc DL = MI->getDebugLoc();
676
677 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
678 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
679 unsigned FltOpc = ARM::VLDMDIA_UPD;
680 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
681 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
682 &isARMArea2Register);
683 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
684 &isARMArea1Register);
685
686 return true;
687 }
688
689 // FIXME: Make generic?
690 static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
691 const ARMBaseInstrInfo &TII) {
692 unsigned FnSize = 0;
693 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
694 MBBI != E; ++MBBI) {
695 const MachineBasicBlock &MBB = *MBBI;
696 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
697 I != E; ++I)
698 FnSize += TII.GetInstSizeInBytes(I);
699 }
700 return FnSize;
701 }
702
703 /// estimateStackSize - Estimate and return the size of the frame.
704 /// FIXME: Make generic?
705 static unsigned estimateStackSize(MachineFunction &MF) {
706 const MachineFrameInfo *FFI = MF.getFrameInfo();
707 int Offset = 0;
708 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
709 int FixedOff = -FFI->getObjectOffset(i);
710 if (FixedOff > Offset) Offset = FixedOff;
711 }
712 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
713 if (FFI->isDeadObjectIndex(i))
714 continue;
715 Offset += FFI->getObjectSize(i);
716 unsigned Align = FFI->getObjectAlignment(i);
717 // Adjust to alignment boundary
718 Offset = (Offset+Align-1)/Align*Align;
719 }
720 return (unsigned)Offset;
721 }
722
723 /// estimateRSStackSizeLimit - Look at each instruction that references stack
724 /// frames and return the stack size limit beyond which some of these
725 /// instructions will require a scratch register during their expansion later.
726 // FIXME: Move to TII?
727 static unsigned estimateRSStackSizeLimit(MachineFunction &MF,
728 const TargetFrameLowering *TFI) {
729 const ARMFunctionInfo *AFI = MF.getInfo();
730 unsigned Limit = (1 << 12) - 1;
731 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
732 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
733 I != E; ++I) {
734 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
735 if (!I->getOperand(i).isFI()) continue;
736
737 // When using ADDri to get the address of a stack object, 255 is the
738 // largest offset guaranteed to fit in the immediate offset.
739 if (I->getOpcode() == ARM::ADDri) {
740 Limit = std::min(Limit, (1U << 8) - 1);
741 break;
742 }
743
744 // Otherwise check the addressing mode.
745 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
746 case ARMII::AddrMode3:
747 case ARMII::AddrModeT2_i8:
748 Limit = std::min(Limit, (1U << 8) - 1);
749 break;
750 case ARMII::AddrMode5:
751 case ARMII::AddrModeT2_i8s4:
752 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
753 break;
754 case ARMII::AddrModeT2_i12:
755 // i12 supports only positive offset so these will be converted to
756 // i8 opcodes. See llvm::rewriteT2FrameIndex.
757 if (TFI->hasFP(MF) && AFI->hasStackFrame())
758 Limit = std::min(Limit, (1U << 8) - 1);
759 break;
760 case ARMII::AddrMode4:
761 case ARMII::AddrMode6:
762 // Addressing modes 4 & 6 (load/store) instructions can't encode an
763 // immediate offset for stack references.
764 return 0;
765 default:
766 break;
767 }
768 break; // At most one FI per instruction
769 }
770 }
771 }
772
773 return Limit;
774 }
775
776 void
777 ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
778 RegScavenger *RS) const {
779 // This tells PEI to spill the FP as if it is any other callee-save register
780 // to take advantage the eliminateFrameIndex machinery. This also ensures it
781 // is spilled in the order specified by getCalleeSavedRegs() to make it easier
782 // to combine multiple loads / stores.
783 bool CanEliminateFrame = true;
784 bool CS1Spilled = false;
785 bool LRSpilled = false;
786 unsigned NumGPRSpills = 0;
787 SmallVector UnspilledCS1GPRs;
788 SmallVector UnspilledCS2GPRs;
789 const ARMBaseRegisterInfo *RegInfo =
790 static_cast(MF.getTarget().getRegisterInfo());
791 const ARMBaseInstrInfo &TII =
792 *static_cast(MF.getTarget().getInstrInfo());
793 ARMFunctionInfo *AFI = MF.getInfo();
794 MachineFrameInfo *MFI = MF.getFrameInfo();
795 unsigned FramePtr = RegInfo->getFrameRegister(MF);
796
797 // Spill R4 if Thumb2 function requires stack realignment - it will be used as
798 // scratch register. Also spill R4 if Thumb2 function has varsized objects,
799 // since it's always posible to restore sp from fp in a single instruction.
800 // FIXME: It will be better just to find spare register here.
801 if (AFI->isThumb2Function() &&
802 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF)))
803 MF.getRegInfo().setPhysRegUsed(ARM::R4);
804
805 // Spill LR if Thumb1 function uses variable length argument lists.
806 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
807 MF.getRegInfo().setPhysRegUsed(ARM::LR);
808
809 // Spill the BasePtr if it's used.
810 if (RegInfo->hasBasePointer(MF))
811 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
812
813 // Don't spill FP if the frame can be eliminated. This is determined
814 // by scanning the callee-save registers to see if any is used.
815 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
816 for (unsigned i = 0; CSRegs[i]; ++i) {
817 unsigned Reg = CSRegs[i];
818 bool Spilled = false;
819 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
820 AFI->setCSRegisterIsSpilled(Reg);
821 Spilled = true;
822 CanEliminateFrame = false;
823 } else {
824 // Check alias registers too.
825 for (const unsigned *Aliases =
826 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) {
827 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
828 Spilled = true;
829 CanEliminateFrame = false;
830 }
831 }
832 }
833
834 if (!ARM::GPRRegisterClass->contains(Reg))
835 continue;
836
837 if (Spilled) {
838 NumGPRSpills++;
839
840 if (!STI.isTargetDarwin()) {
841 if (Reg == ARM::LR)
842 LRSpilled = true;
843 CS1Spilled = true;
844 continue;
845 }
846
847 // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
848 switch (Reg) {
849 case ARM::LR:
850 LRSpilled = true;
851 // Fallthrough
852 case ARM::R4: case ARM::R5:
853 case ARM::R6: case ARM::R7:
854 CS1Spilled = true;
855 break;
856 default:
857 break;
858 }
859 } else {
860 if (!STI.isTargetDarwin()) {
861 UnspilledCS1GPRs.push_back(Reg);
862 continue;
863 }
864
865 switch (Reg) {
866 case ARM::R4: case ARM::R5:
867 case ARM::R6: case ARM::R7:
868 case ARM::LR:
869 UnspilledCS1GPRs.push_back(Reg);
870 break;
871 default:
872 UnspilledCS2GPRs.push_back(Reg);
873 break;
874 }
875 }
876 }
877
878 bool ForceLRSpill = false;
879 if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
880 unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
881 // Force LR to be spilled if the Thumb function size is > 2048. This enables
882 // use of BL to implement far jump. If it turns out that it's not needed
883 // then the branch fix up path will undo it.
884 if (FnSize >= (1 << 11)) {
885 CanEliminateFrame = false;
886 ForceLRSpill = true;
887 }
888 }
889
890 // If any of the stack slot references may be out of range of an immediate
891 // offset, make sure a register (or a spill slot) is available for the
892 // register scavenger. Note that if we're indexing off the frame pointer, the
893 // effective stack size is 4 bytes larger since the FP points to the stack
894 // slot of the previous FP. Also, if we have variable sized objects in the
895 // function, stack slot references will often be negative, and some of
896 // our instructions are positive-offset only, so conservatively consider
897 // that case to want a spill slot (or register) as well. Similarly, if
898 // the function adjusts the stack pointer during execution and the
899 // adjustments aren't already part of our stack size estimate, our offset
900 // calculations may be off, so be conservative.
901 // FIXME: We could add logic to be more precise about negative offsets
902 // and which instructions will need a scratch register for them. Is it
903 // worth the effort and added fragility?
904 bool BigStack =
905 (RS &&
906 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
907 estimateRSStackSizeLimit(MF, this)))
908 || MFI->hasVarSizedObjects()
909 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
910
911 bool ExtraCSSpill = false;
912 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
913 AFI->setHasStackFrame(true);
914
915 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
916 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
917 if (!LRSpilled && CS1Spilled) {
918 MF.getRegInfo().setPhysRegUsed(ARM::LR);
919 AFI->setCSRegisterIsSpilled(ARM::LR);
920 NumGPRSpills++;
921 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
922 UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
923 ForceLRSpill = false;
924 ExtraCSSpill = true;
925 }
926
927 if (hasFP(MF)) {
928 MF.getRegInfo().setPhysRegUsed(FramePtr);
929 NumGPRSpills++;
930 }
931
932 // If stack and double are 8-byte aligned and we are spilling an odd number
933 // of GPRs, spill one extra callee save GPR so we won't have to pad between
934 // the integer and double callee save areas.
935 unsigned TargetAlign = getStackAlignment();
936 if (TargetAlign == 8 && (NumGPRSpills & 1)) {
937 if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
938 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
939 unsigned Reg = UnspilledCS1GPRs[i];
940 // Don't spill high register if the function is thumb1
941 if (!AFI->isThumb1OnlyFunction() ||
942 isARMLowRegister(Reg) || Reg == ARM::LR) {
943 MF.getRegInfo().setPhysRegUsed(Reg);
944 AFI->setCSRegisterIsSpilled(Reg);
945 if (!RegInfo->isReservedReg(MF, Reg))
946 ExtraCSSpill = true;
947 break;
948 }
949 }
950 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
951 unsigned Reg = UnspilledCS2GPRs.front();
952 MF.getRegInfo().setPhysRegUsed(Reg);
953 AFI->setCSRegisterIsSpilled(Reg);
954 if (!RegInfo->isReservedReg(MF, Reg))
955 ExtraCSSpill = true;
956 }
957 }
958
959 // Estimate if we might need to scavenge a register at some point in order
960 // to materialize a stack offset. If so, either spill one additional
961 // callee-saved register or reserve a special spill slot to facilitate
962 // register scavenging. Thumb1 needs a spill slot for stack pointer
963 // adjustments also, even when the frame itself is small.
964 if (BigStack && !ExtraCSSpill) {
965 // If any non-reserved CS register isn't spilled, just spill one or two
966 // extra. That should take care of it!
967 unsigned NumExtras = TargetAlign / 4;
968 SmallVector Extras;
969 while (NumExtras && !UnspilledCS1GPRs.empty()) {
970 unsigned Reg = UnspilledCS1GPRs.back();
971 UnspilledCS1GPRs.pop_back();
972 if (!RegInfo->isReservedReg(MF, Reg) &&
973 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
974 Reg == ARM::LR)) {
975 Extras.push_back(Reg);
976 NumExtras--;
977 }
978 }
979 // For non-Thumb1 functions, also check for hi-reg CS registers
980 if (!AFI->isThumb1OnlyFunction()) {
981 while (NumExtras && !UnspilledCS2GPRs.empty()) {
982 unsigned Reg = UnspilledCS2GPRs.back();
983 UnspilledCS2GPRs.pop_back();
984 if (!RegInfo->isReservedReg(MF, Reg)) {
985 Extras.push_back(Reg);
986 NumExtras--;
987 }
988 }
989 }
990 if (Extras.size() && NumExtras == 0) {
991 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
992 MF.getRegInfo().setPhysRegUsed(Extras[i]);
993 AFI->setCSRegisterIsSpilled(Extras[i]);
994 }
995 } else if (!AFI->isThumb1OnlyFunction()) {
996 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot
997 // closest to SP or frame pointer.
998 const TargetRegisterClass *RC = ARM::GPRRegisterClass;
999 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1000 RC->getAlignment(),
1001 false));
1002 }
1003 }
1004 }
1005
1006 if (ForceLRSpill) {
1007 MF.getRegInfo().setPhysRegUsed(ARM::LR);
1008 AFI->setCSRegisterIsSpilled(ARM::LR);
1009 AFI->setLRIsSpilledForFarJump(true);
1010 }
1011 }
0 //==-- ARMTargetFrameLowering.h - Define frame lowering for ARM --*- C++ -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef ARM_FRAMEINFO_H
14 #define ARM_FRAMEINFO_H
15
16 #include "ARM.h"
17 #include "ARMSubtarget.h"
18 #include "llvm/Target/TargetFrameLowering.h"
19
20 namespace llvm {
21 class ARMSubtarget;
22
23 class ARMFrameLowering : public TargetFrameLowering {
24 protected:
25 const ARMSubtarget &STI;
26
27 public:
28 explicit ARMFrameLowering(const ARMSubtarget &sti)
29 : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4),
30 STI(sti) {
31 }
32
33 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
34 /// the function.
35 void emitPrologue(MachineFunction &MF) const;
36 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
37
38 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator MI,
40 const std::vector &CSI,
41 const TargetRegisterInfo *TRI) const;
42
43 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI,
45 const std::vector &CSI,
46 const TargetRegisterInfo *TRI) const;
47
48 bool hasFP(const MachineFunction &MF) const;
49 bool hasReservedCallFrame(const MachineFunction &MF) const;
50 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
51 int getFrameIndexReference(const MachineFunction &MF, int FI,
52 unsigned &FrameReg) const;
53 int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
54 unsigned &FrameReg, int SPAdj) const;
55 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
56
57 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
58 RegScavenger *RS) const;
59
60 private:
61 void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
62 const std::vector &CSI, unsigned StmOpc,
63 unsigned StrOpc, bool NoGap,
64 bool(*Func)(unsigned, bool)) const;
65 void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
66 const std::vector &CSI, unsigned LdmOpc,
67 unsigned LdrOpc, bool isVarArg, bool NoGap,
68 bool(*Func)(unsigned, bool)) const;
69 };
70
71 } // End llvm namespace
72
73 #endif
901901 return Sched::RegPressure;
902902 }
903903
904 // FIXME: Move to RegInfo
904905 unsigned
905906 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
906907 MachineFunction &MF) const {
907 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
908 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
908909
909910 switch (RC->getID()) {
910911 default:
23162317 unsigned NumGPRs = CCInfo.getFirstUnallocated
23172318 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
23182319
2319 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2320 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
23202321 unsigned VARegSize = (4 - NumGPRs) * 4;
23212322 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
23222323 unsigned ArgOffset = CCInfo.getNextStackOffset();
2727 #include "llvm/CodeGen/MachineRegisterInfo.h"
2828 #include "llvm/CodeGen/RegisterScavenging.h"
2929 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Target/TargetFrameInfo.h"
3130 #include "llvm/Target/TargetMachine.h"
3231 #include "llvm/Target/TargetOptions.h"
3332 #include "llvm/ADT/BitVector.h"
1111
1212 #include "ARMTargetMachine.h"
1313 #include "ARMMCAsmInfo.h"
14 #include "ARMFrameInfo.h"
14 #include "ARMFrameLowering.h"
1515 #include "ARM.h"
1616 #include "llvm/PassManager.h"
1717 #include "llvm/CodeGen/Passes.h"
101101 ELFWriterInfo(*this),
102102 TLInfo(*this),
103103 TSInfo(*this),
104 FrameInfo(Subtarget) {
104 FrameLowering(Subtarget) {
105105 if (!Subtarget.hasARMOps())
106106 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
107107 "support ARM mode execution!");
123123 ELFWriterInfo(*this),
124124 TLInfo(*this),
125125 TSInfo(*this),
126 FrameInfo(Subtarget.hasThumb2()
127 ? new ARMFrameInfo(Subtarget)
128 : (ARMFrameInfo*)new Thumb1FrameInfo(Subtarget)) {
126 FrameLowering(Subtarget.hasThumb2()
127 ? new ARMFrameLowering(Subtarget)
128 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
129129 }
130130
131131 // Pass Pipeline Configuration
1515
1616 #include "ARMInstrInfo.h"
1717 #include "ARMELFWriterInfo.h"
18 #include "ARMFrameInfo.h"
18 #include "ARMFrameLowering.h"
1919 #include "ARMJITInfo.h"
2020 #include "ARMSubtarget.h"
2121 #include "ARMISelLowering.h"
2222 #include "ARMSelectionDAGInfo.h"
2323 #include "Thumb1InstrInfo.h"
24 #include "Thumb1FrameInfo.h"
24 #include "Thumb1FrameLowering.h"
2525 #include "Thumb2InstrInfo.h"
2626 #include "llvm/Target/TargetMachine.h"
2727 #include "llvm/Target/TargetData.h"
6666 ARMELFWriterInfo ELFWriterInfo;
6767 ARMTargetLowering TLInfo;
6868 ARMSelectionDAGInfo TSInfo;
69 ARMFrameInfo FrameInfo;
69 ARMFrameLowering FrameLowering;
7070 public:
7171 ARMTargetMachine(const Target &T, const std::string &TT,
7272 const std::string &FS);
8282 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
8383 return &TSInfo;
8484 }
85 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
85 virtual const ARMFrameLowering *getFrameLowering() const {
86 return &FrameLowering;
87 }
8688
8789 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
8890 virtual const TargetData *getTargetData() const { return &DataLayout; }
102104 ARMELFWriterInfo ELFWriterInfo;
103105 ARMTargetLowering TLInfo;
104106 ARMSelectionDAGInfo TSInfo;
105 // Either Thumb1FrameInfo or ARMFrameInfo.
106 OwningPtr FrameInfo;
107 // Either Thumb1FrameLowering or ARMFrameLowering.
108 OwningPtr FrameLowering;
107109 public:
108110 ThumbTargetMachine(const Target &T, const std::string &TT,
109111 const std::string &FS);
125127 virtual const ARMBaseInstrInfo *getInstrInfo() const {
126128 return InstrInfo.get();
127129 }
128 /// returns either Thumb1FrameInfo or ARMFrameInfo
129 virtual const ARMFrameInfo *getFrameInfo() const {
130 return FrameInfo.get();
130 /// returns either Thumb1FrameLowering or ARMFrameLowering
131 virtual const ARMFrameLowering *getFrameLowering() const {
132 return FrameLowering.get();
131133 }
132134 virtual const TargetData *getTargetData() const { return &DataLayout; }
133135 virtual const ARMELFWriterInfo *getELFWriterInfo() const {
+0
-345
lib/Target/ARM/Thumb1FrameInfo.cpp less more
None //=======- Thumb1FrameInfo.cpp - Thumb1 Frame Information ------*- C++ -*-====//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb1 implementation of TargetFrameInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "Thumb1FrameInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMMachineFunctionInfo.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20
21 using namespace llvm;
22
23 bool Thumb1FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const {
24 const MachineFrameInfo *FFI = MF.getFrameInfo();
25 unsigned CFSize = FFI->getMaxCallFrameSize();
26 // It's not always a good idea to include the call frame as part of the
27 // stack frame. ARM (especially Thumb) has small immediate offset to
28 // address the stack frame. So a large call frame can cause poor codegen
29 // and may even makes it impossible to scavenge a register.
30 if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
31 return false;
32
33 return !MF.getFrameInfo()->hasVarSizedObjects();
34 }
35
36 static void emitSPUpdate(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator &MBBI,
38 const TargetInstrInfo &TII, DebugLoc dl,
39 const Thumb1RegisterInfo &MRI,
40 int NumBytes) {
41 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII,
42 MRI, dl);
43 }
44
45 void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const {
46 MachineBasicBlock &MBB = MF.front();
47 MachineBasicBlock::iterator MBBI = MBB.begin();
48 MachineFrameInfo *MFI = MF.getFrameInfo();
49 ARMFunctionInfo *AFI = MF.getInfo();
50 const Thumb1RegisterInfo *RegInfo =
51 static_cast(MF.getTarget().getRegisterInfo());
52 const Thumb1InstrInfo &TII =
53 *static_cast(MF.getTarget().getInstrInfo());
54
55 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
56 unsigned NumBytes = MFI->getStackSize();
57 const std::vector &CSI = MFI->getCalleeSavedInfo();
58 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
59 unsigned FramePtr = RegInfo->getFrameRegister(MF);
60 unsigned BasePtr = RegInfo->getBaseRegister();
61
62 // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
63 NumBytes = (NumBytes + 3) & ~3;
64 MFI->setStackSize(NumBytes);
65
66 // Determine the sizes of each callee-save spill areas and record which frame
67 // belongs to which callee-save spill areas.
68 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
69 int FramePtrSpillFI = 0;
70
71 if (VARegSaveSize)
72 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize);
73
74 if (!AFI->hasStackFrame()) {
75 if (NumBytes != 0)
76 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
77 return;
78 }
79
80 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
81 unsigned Reg = CSI[i].getReg();
82 int FI = CSI[i].getFrameIdx();
83 switch (Reg) {
84 case ARM::R4:
85 case ARM::R5:
86 case ARM::R6:
87 case ARM::R7:
88 case ARM::LR:
89 if (Reg == FramePtr)
90 FramePtrSpillFI = FI;
91 AFI->addGPRCalleeSavedArea1Frame(FI);
92 GPRCS1Size += 4;
93 break;
94 case ARM::R8:
95 case ARM::R9:
96 case ARM::R10:
97 case ARM::R11:
98 if (Reg == FramePtr)
99 FramePtrSpillFI = FI;
100 if (STI.isTargetDarwin()) {
101 AFI->addGPRCalleeSavedArea2Frame(FI);
102 GPRCS2Size += 4;
103 } else {
104 AFI->addGPRCalleeSavedArea1Frame(FI);
105 GPRCS1Size += 4;
106 }
107 break;
108 default:
109 AFI->addDPRCalleeSavedAreaFrame(FI);
110 DPRCSSize += 8;
111 }
112 }
113
114 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
115 ++MBBI;
116 if (MBBI != MBB.end())
117 dl = MBBI->getDebugLoc();
118 }
119
120 // Determine starting offsets of spill areas.
121 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
122 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
123 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
124 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
125 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
126 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
127 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
128 NumBytes = DPRCSOffset;
129
130 // Adjust FP so it point to the stack slot that contains the previous FP.
131 if (hasFP(MF)) {
132 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
133 .addFrameIndex(FramePtrSpillFI).addImm(0);
134 if (NumBytes > 7)
135 // If offset is > 7 then sp cannot be adjusted in a single instruction,
136 // try restoring from fp instead.
137 AFI->setShouldRestoreSPFromFP(true);
138 }
139
140 if (NumBytes)
141 // Insert it after all the callee-save spills.
142 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes);
143
144 if (STI.isTargetELF() && hasFP(MF))
145 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
146 AFI->getFramePtrSpillOffset());
147
148 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
149 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
150 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
151
152