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Merging r314798: ------------------------------------------------------------------------ r314798 | sdardis | 2017-10-03 06:45:49 -0700 (Tue, 03 Oct 2017) | 9 lines [mips] Enable spilling and reloading of the dsp register set. The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318183 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 9 months ago
4 changed file(s) with 69 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
414414 class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
415415 NoItinerary>;
416416
417 let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp",
418 AdditionalPredicates = [HasDSP, InMicroMips] in {
419 def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel,
420 LW_FM_MM<0x3f>;
421 def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel,
422 LW_FM_MM<0x3e>;
423 }
417424 // Instruction defs.
418425 // microMIPS DSP Rev 1
419426 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
12831283 def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
12841284 }
12851285
1286 let DecoderNamespace = "MipsDSP", Arch = "dsp",
1287 AdditionalPredicates = [HasDSP] in {
1288 def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
1289 def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
1290 }
1291
12861292 // Pseudo CMP and PICK instructions.
12871293 class PseudoCMP :
12881294 PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
225225 Opc = Mips::SW;
226226 else if (Mips::HI64RegClass.hasSubClassEq(RC))
227227 Opc = Mips::SD;
228 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
229 Opc = Mips::SWDSP;
228230
229231 // Hi, Lo are normally caller save but they are callee save
230232 // for interrupt handling.
301303 Opc = Mips::LW;
302304 else if (Mips::LO64RegClass.hasSubClassEq(RC))
303305 Opc = Mips::LD;
306 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
307 Opc = Mips::LWDSP;
304308
305309 assert(Opc && "Register class not handled!");
306310
0 ; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
1 ; RUN: --check-prefixes=ASM,ALL
2 ; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
3 ; RUN: llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
4
5 ; Test that spill and reloads use the dsp "variant" instructions. We use -O0
6 ; to use the simple register allocator.
7
8 ; To test the micromips output, we have to take a round trip through the
9 ; object file encoder/decoder as the instruction mapping tables are used to
10 ; support micromips.
11
12 ; FIXME: We should be able to get rid of those instructions with the variable
13 ; value registers.
14
15 ; ALL-LABEL: spill_reload:
16
17 define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
18 entry:
19 %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)
20 %cond = icmp eq i32 %g, 0
21 br i1 %cond, label %true, label %end
22
23 ; ASM: SWDSP
24 ; ASM: SWDSP
25 ; ASM: SWDSP
26
27 ; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
28 ; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
29 ; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
30 ; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
31
32 true:
33 ret <4 x i8> %c
34
35 ; ASM: LWDSP
36
37 ; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
38
39 end:
40 %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a)
41 ret <4 x i8> %d
42
43 ; ASM: LWDSP
44 ; ASM: LWDSP
45
46 ; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
47 ; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
48
49 }
50
51 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind