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[X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268871 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 3 years ago
6 changed file(s) with 11 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
493493 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
494494 }
495495
496 let Predicates = [HasAVX] in
496 let Predicates = [HasAVX] in {
497497 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498
499 let Predicates = [HasAVX2] in {
500498 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
501499 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
502500 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
503501 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
504 }
505
506 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
507 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
508 let Predicates = [HasAVX1Only] in {
509 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
510 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
511 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512
513 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
514 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
515 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516
517 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
518 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
519 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520
521 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
522 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
523 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
524502 }
525503
526504 // We set canFoldAsLoad because this can be converted to a constant-pool
77 ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
88 ; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = xmm0[0,0]
99 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm1
10 ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
10 ; CHECK-NEXT: vxorps %ymm2, %ymm2, %ymm2
1111 ; CHECK-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1,2,3,4,5,6],ymm1[7]
12 ; CHECK-NEXT: vxorps %ymm2, %ymm2, %ymm2
1312 ; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3,4,5,6,7]
1413 ; CHECK-NEXT: vmovaps %ymm0, (%eax)
1514 ; CHECK-NEXT: vmovaps %ymm1, (%eax)
33 define void @bad_cast() {
44 ; CHECK-LABEL: bad_cast:
55 ; CHECK: # BB#0:
6 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
6 ; CHECK-NEXT: vxorps %ymm0, %ymm0, %ymm0
77 ; CHECK-NEXT: vmovaps %xmm0, (%eax)
88 ; CHECK-NEXT: movl $0, (%eax)
99 ; CHECK-NEXT: vzeroupper
33 define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
44 ; CHECK-LABEL: select00:
55 ; CHECK: ## BB#0:
6 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
6 ; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1
77 ; CHECK-NEXT: cmpl $255, %edi
88 ; CHECK-NEXT: je LBB0_2
99 ; CHECK-NEXT: ## BB#1:
2020 define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
2121 ; CHECK-LABEL: select01:
2222 ; CHECK: ## BB#0:
23 ; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1
23 ; CHECK-NEXT: vxorps %ymm1, %ymm1, %ymm1
2424 ; CHECK-NEXT: cmpl $255, %edi
2525 ; CHECK-NEXT: je LBB1_2
2626 ; CHECK-NEXT: ## BB#1:
431431 define <8 x i32> @merge_8i32_i32_1u3u5zu8(i32* %ptr) nounwind uwtable noinline ssp {
432432 ; AVX1-LABEL: merge_8i32_i32_1u3u5zu8:
433433 ; AVX1: # BB#0:
434 ; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
434 ; AVX1-NEXT: vxorps %ymm0, %ymm0, %ymm0
435435 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
436436 ; AVX1-NEXT: retq
437437 ;
450450 ; X32-AVX-LABEL: merge_8i32_i32_1u3u5zu8:
451451 ; X32-AVX: # BB#0:
452452 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
453 ; X32-AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
453 ; X32-AVX-NEXT: vxorps %ymm0, %ymm0, %ymm0
454454 ; X32-AVX-NEXT: vblendps {{.*#+}} ymm0 = mem[0,1,2,3,4],ymm0[5],mem[6,7]
455455 ; X32-AVX-NEXT: retl
456456 %ptr0 = getelementptr inbounds i32, i32* %ptr, i64 1
19061906 define <8 x i32> @shuffle_v8i32_zuu8zuuc(<8 x i32> %a) {
19071907 ; AVX1-LABEL: shuffle_v8i32_zuu8zuuc:
19081908 ; AVX1: # BB#0:
1909 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1909 ; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1
19101910 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,0],ymm1[4,5],ymm0[6,4]
19111911 ; AVX1-NEXT: retq
19121912 ;
19211921 define <8 x i32> @shuffle_v8i32_9ubzdefz(<8 x i32> %a) {
19221922 ; AVX1-LABEL: shuffle_v8i32_9ubzdefz:
19231923 ; AVX1: # BB#0:
1924 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1924 ; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1
19251925 ; AVX1-NEXT: vshufps {{.*#+}} ymm1 = ymm1[3,0],ymm0[3,0],ymm1[7,4],ymm0[7,4]
19261926 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,2],ymm1[2,0],ymm0[5,6],ymm1[6,4]
19271927 ; AVX1-NEXT: retq
20472047 define <8 x i32> @shuffle_v8i32_z0U2zUz6(<8 x i32> %a) {
20482048 ; AVX1-LABEL: shuffle_v8i32_z0U2zUz6:
20492049 ; AVX1: # BB#0:
2050 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
2050 ; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1
20512051 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
20522052 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[2,0,3,1,6,4,7,5]
20532053 ; AVX1-NEXT: retq
20632063 define <8 x i32> @shuffle_v8i32_1U3z5zUU(<8 x i32> %a) {
20642064 ; AVX1-LABEL: shuffle_v8i32_1U3z5zUU:
20652065 ; AVX1: # BB#0:
2066 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
2066 ; AVX1-NEXT: vxorps %ymm1, %ymm1, %ymm1
20672067 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm1[1,3],ymm0[5,7],ymm1[5,7]
20682068 ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2,1,3,4,6,5,7]
20692069 ; AVX1-NEXT: retq