llvm.org GIT mirror llvm / 168a1af
Revert "[AArch64] This is a work in progress to provide a machine description" This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202773 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 6 years ago
6 changed file(s) with 187 addition(s) and 631 deletion(s). Raw diff Collapse all Expand all
4040
4141 def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
4242
43 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
44 "Cortex-A53 ARM processors",
45 [FeatureFPARMv8,
46 FeatureNEON,
47 FeatureCrypto]>;
43 def : ProcNoItin<"cortex-a53", [FeatureFPARMv8,
44 FeatureNEON,
45 FeatureCrypto]>;
4846
49 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
50 "Cortex-A57 ARM processors",
51 [FeatureFPARMv8,
52 FeatureNEON,
53 FeatureCrypto]>;
54
55 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
56 def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
47 def : ProcNoItin<"cortex-a57", [FeatureFPARMv8,
48 FeatureNEON,
49 FeatureCrypto]>;
5750
5851 //===----------------------------------------------------------------------===//
5952 // Register File Description
349349 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
350350 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
351351 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
352 NoItinerary>,
353 Sched<[WriteALU, ReadALU, ReadALU]>;
352 NoItinerary>;
354353 def w_uxth : A64I_addsubext
355354 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
356355 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
357356 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
358 NoItinerary>,
359 Sched<[WriteALU, ReadALU, ReadALU]>;
357 NoItinerary>;
360358 def w_uxtw : A64I_addsubext
361359 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
362360 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
363361 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
364 NoItinerary>,
365 Sched<[WriteALU, ReadALU, ReadALU]>;
362 NoItinerary>;
366363
367364 def w_sxtb : A64I_addsubext
368365 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
369366 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
370367 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
371 NoItinerary>,
372 Sched<[WriteALU, ReadALU, ReadALU]>;
368 NoItinerary>;
373369 def w_sxth : A64I_addsubext
374370 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
375371 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
376372 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
377 NoItinerary>,
378 Sched<[WriteALU, ReadALU, ReadALU]>;
373 NoItinerary>;
379374 def w_sxtw : A64I_addsubext
380375 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
381376 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
382377 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
383 NoItinerary>,
384 Sched<[WriteALU, ReadALU, ReadALU]>;
378 NoItinerary>;
385379 }
386380
387381 // These two could be merge in with the above, but their patterns aren't really
393387 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
394388 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
395389 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
396 NoItinerary>,
397 Sched<[WriteALU, ReadALU, ReadALU]>;
390 NoItinerary>;
398391
399392 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
400393 outs,
401394 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
402395 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
403396 [/* No Pattern: same as uxtx */],
404 NoItinerary>,
405 Sched<[WriteALU, ReadALU, ReadALU]>;
397 NoItinerary>;
406398 }
407399
408400 multiclass addsub_wxtx {
409401 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
410 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
411 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
412 [/* No pattern: probably same as uxtw */],
413 NoItinerary>,
414 Sched<[WriteALU, ReadALU, ReadALU]>;
402 outs,
403 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
404 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
405 [/* No pattern: probably same as uxtw */],
406 NoItinerary>;
415407
416408 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
417 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
418 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
419 [/* No Pattern: probably same as uxtw */],
420 NoItinerary>,
421 Sched<[WriteALU, ReadALU, ReadALU]>;
409 outs,
410 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
411 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
412 [/* No Pattern: probably same as uxtw */],
413 NoItinerary>;
422414 }
423415
424416 class SetRD
664656 (ins GPRsp:$Rn, imm_operand:$Imm12),
665657 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
666658 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
667 NoItinerary>,
668 Sched<[WriteALU, ReadALU]>;
659 NoItinerary>;
669660
670661
671662 // S variants can read SP but would write to ZR
674665 (ins GPRsp:$Rn, imm_operand:$Imm12),
675666 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
676667 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
677 NoItinerary>,
678 Sched<[WriteALU, ReadALU]> {
668 NoItinerary> {
679669 let Defs = [NZCV];
680670 }
681671
687677 !strconcat(cmpasmop, " $Rn, $Imm12"),
688678 [(set NZCV,
689679 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
690 NoItinerary>,
691 Sched<[WriteALU, ReadALU]> {
680 NoItinerary> {
692681 let Rd = 0b11111;
693682 let Defs = [NZCV];
694683 let isCompare = 1;
750739 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
751740
752741 //===-------------------------------
753 // 1. The "shifted register" operands. Shared with logical insts.
742 // 1. The "shifed register" operands. Shared with logical insts.
754743 //===-------------------------------
755744
756745 multiclass shift_operands {
810799 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
811800 !cast("lsl_operand_" # ty):$Imm6))
812801 )],
813 NoItinerary>,
814 Sched<[WriteALU, ReadALU]>;
802 NoItinerary>;
815803
816804 def _lsr : A64I_addsubshift
817805 (outs GPR:$Rd),
821809 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
822810 !cast("lsr_operand_" # ty):$Imm6))
823811 )],
824 NoItinerary>,
825 Sched<[WriteALU, ReadALU]>;
812 NoItinerary>;
826813
827814 def _asr : A64I_addsubshift
828815 (outs GPR:$Rd),
832819 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
833820 !cast("asr_operand_" # ty):$Imm6))
834821 )],
835 NoItinerary>,
836 Sched<[WriteALU, ReadALU]>;
822 NoItinerary>;
837823 }
838824
839825 def _noshift
919905 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
920906 !cast("lsl_operand_" # ty):$Imm6))
921907 )],
922 NoItinerary>,
923 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
908 NoItinerary>;
924909
925910 def _lsr : A64I_addsubshift
926911 (outs),
930915 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
931916 !cast("lsr_operand_" # ty):$Imm6))
932917 )],
933 NoItinerary>,
934 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
918 NoItinerary>;
935919
936920 def _asr : A64I_addsubshift
937921 (outs),
941925 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
942926 !cast("asr_operand_" # ty):$Imm6))
943927 )],
944 NoItinerary>,
945 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
928 NoItinerary>;
946929 }
947930
948931 def _noshift
969952 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
970953 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
971954 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
972 [], NoItinerary>,
973 Sched<[WriteALU, ReadALU, ReadALU]>;
955 [], NoItinerary>;
974956
975957 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
976958 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
977959 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
978 [], NoItinerary>,
979 Sched<[WriteALU, ReadALU, ReadALU]>;
960 [], NoItinerary>;
980961 }
981962 }
982963
10621043 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
10631044 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
10641045 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1065 [], NoItinerary>,
1066 Sched<[WriteALU, ReadALU]> {
1046 [], NoItinerary> {
10671047 let DecoderMethod = "DecodeBitfieldInstruction";
10681048 }
10691049
10701050 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
10711051 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
10721052 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1073 [], NoItinerary>,
1074 Sched<[WriteALU, ReadALU]> {
1053 [], NoItinerary> {
10751054 let DecoderMethod = "DecodeBitfieldInstruction";
10761055 }
10771056 }
10841063 def BFMwwii :
10851064 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
10861065 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1087 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1088 Sched<[WriteALU, ReadALU]> {
1066 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
10891067 let DecoderMethod = "DecodeBitfieldInstruction";
10901068 let Constraints = "$src = $Rd";
10911069 }
10931071 def BFMxxii :
10941072 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
10951073 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1096 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1097 Sched<[WriteALU, ReadALU]> {
1074 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
10981075 let DecoderMethod = "DecodeBitfieldInstruction";
10991076 let Constraints = "$src = $Rd";
11001077 }
11161093 : A64I_bitfield
11171094 (outs GPRDest:$Rd), (ins GPR32:$Rn),
11181095 !strconcat(asmop, "\t$Rd, $Rn"),
1119 [(set dty:$Rd, pattern)], NoItinerary>,
1120 Sched<[WriteALU, ReadALU]> {
1096 [(set dty:$Rd, pattern)], NoItinerary> {
11211097 let ImmR = 0b000000;
11221098 let ImmS = imms;
11231099 }
11711147 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
11721148 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
11731149 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1174 NoItinerary>,
1175 Sched<[WriteALU, ReadALU]> {
1150 NoItinerary> {
11761151 let ImmS = 31;
11771152 }
11781153
11801155 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
11811156 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
11821157 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1183 NoItinerary>,
1184 Sched<[WriteALU, ReadALU]> {
1158 NoItinerary> {
11851159 let ImmS = 63;
11861160 }
11871161
12221196 : A64I_bitfield
12231197 "lsl\t$Rd, $Rn, $FullImm",
12241198 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1225 NoItinerary>,
1226 Sched<[WriteALU, ReadALU]> {
1199 NoItinerary> {
12271200 bits<12> FullImm;
12281201 let ImmR = FullImm{5-0};
12291202 let ImmS = FullImm{11-6};
12701243 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
12711244 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
12721245 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1273 NoItinerary>,
1274 Sched<[WriteALU, ReadALU]> {
1246 NoItinerary> {
12751247 // As above, no disassembler allowed.
12761248 let isAsmParserOnly = 1;
12771249 }
12801252 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
12811253 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
12821254 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1283 NoItinerary>,
1284 Sched<[WriteALU, ReadALU]> {
1255 NoItinerary> {
12851256 // As above, no disassembler allowed.
12861257 let isAsmParserOnly = 1;
12871258 }
12921263
12931264 // Again, variants based on BFM modify Rd so need it as an input too.
12941265 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1295 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1296 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1297 Sched<[WriteALU, ReadALU]> {
1266 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1267 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
12981268 // As above, no disassembler allowed.
12991269 let isAsmParserOnly = 1;
13001270 let Constraints = "$src = $Rd";
13011271 }
13021272
13031273 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1304 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1305 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1306 Sched<[WriteALU, ReadALU]> {
1274 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1275 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
13071276 // As above, no disassembler allowed.
13081277 let isAsmParserOnly = 1;
13091278 let Constraints = "$src = $Rd";
13831352 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
13841353 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
13851354 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1386 [], NoItinerary>,
1387 Sched<[WriteALU, ReadALU]> {
1355 [], NoItinerary> {
13881356 // As above, no disassembler allowed.
13891357 let isAsmParserOnly = 1;
13901358 }
13921360 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
13931361 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
13941362 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1395 [], NoItinerary>,
1396 Sched<[WriteALU, ReadALU]> {
1363 [], NoItinerary> {
13971364 // As above, no disassembler allowed.
13981365 let isAsmParserOnly = 1;
13991366 }
14051372
14061373 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
14071374 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1408 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1409 Sched<[WriteALU, ReadALU]> {
1375 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
14101376 // As above, no disassembler allowed.
14111377 let isAsmParserOnly = 1;
14121378 let Constraints = "$src = $Rd";
14141380
14151381 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
14161382 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1417 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1418 Sched<[WriteALU, ReadALU]> {
1383 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
14191384 // As above, no disassembler allowed.
14201385 let isAsmParserOnly = 1;
14211386 let Constraints = "$src = $Rd";
14521417 (ins GPR64:$Rt, bcc_target:$Label),
14531418 !strconcat(asmop,"\t$Rt, $Label"),
14541419 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1455 NoItinerary>,
1456 Sched<[WriteBr, ReadBr]>;
1420 NoItinerary>;
14571421
14581422 def w : A64I_cmpbr<0b0, op,
14591423 (outs),
14601424 (ins GPR32:$Rt, bcc_target:$Label),
14611425 !strconcat(asmop,"\t$Rt, $Label"),
14621426 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1463 NoItinerary>,
1464 Sched<[WriteBr, ReadBr]>;
1427 NoItinerary>;
14651428 }
14661429 }
14671430
14921455 def Bcc : A64I_condbr<0b0, 0b0, (outs),
14931456 (ins cond_code:$Cond, bcc_target:$Label),
14941457 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1495 NoItinerary>,
1496 Sched<[WriteBr]> {
1458 NoItinerary> {
14971459 let Uses = [NZCV];
14981460 let isBranch = 1;
14991461 let isTerminator = 1;
15391501 : A64I_condcmpimm
15401502 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
15411503 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1542 [], NoItinerary>,
1543 Sched<[WriteCMP, ReadCMP]> {
1504 [], NoItinerary> {
15441505 let Defs = [NZCV];
15451506 }
15461507
16061567 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
16071568 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
16081569 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1609 NoItinerary>,
1610 Sched<[WriteCMP, ReadCMP]>;
1570 NoItinerary>;
16111571
16121572
16131573 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
16151575 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
16161576 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
16171577 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1618 NoItinerary>,
1619 Sched<[WriteCMP, ReadCMP]>;
1578 NoItinerary>;
16201579 }
16211580 }
16221581
17261685 (outs GPRrc:$Rd),
17271686 (ins GPRrc:$Rn),
17281687 patterns,
1729 itin>,
1730 Sched<[WriteALU, ReadALU]>;
1688 itin>;
17311689
17321690 multiclass A64I_dp_1src opcode, string asmop> {
17331691 let hasSideEffects = 0 in {
17831741 (outs GPRsp:$Rd),
17841742 (ins GPRsp:$Rn, GPRsp:$Rm),
17851743 patterns,
1786 itin>,
1787 Sched<[WriteALU, ReadALU, ReadALU]>;
1744 itin>;
17881745
17891746 multiclass dp_2src_crc {
17901747 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
18351792 defm CRC32 : dp_2src_crc<0b0, "crc32">;
18361793 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
18371794
1838 let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {
1839 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1840 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1841 }
1842
1843 let SchedRW = [WriteALUs, ReadALU, ReadALU] in {
1844 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1845 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1846 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1847 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1848 }
1795 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1796 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1797
1798 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1799 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1800 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1801 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
18491802
18501803 // Extra patterns for an incoming 64-bit value for a 32-bit
18511804 // operation. Since the LLVM operations are undefined (as in C) if the
18781831 : A64I_dp3
18791832 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
18801833 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1881 [(set AccTy:$Rd, pattern)], NoItinerary>,
1882 Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
1834 [(set AccTy:$Rd, pattern)], NoItinerary> {
18831835 RegisterClass AccGPR = AccReg;
18841836 RegisterClass SrcGPR = SrcReg;
18851837 }
19091861 (ins GPR64:$Rn, GPR64:$Rm),
19101862 "umulh\t$Rd, $Rn, $Rm",
19111863 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1912 NoItinerary>,
1913 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1864 NoItinerary>;
19141865
19151866 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
19161867 (ins GPR64:$Rn, GPR64:$Rm),
19171868 "smulh\t$Rd, $Rn, $Rm",
19181869 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1919 NoItinerary>,
1920 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
1870 NoItinerary>;
19211871 }
19221872
19231873 multiclass A64I_dp3_3operand
19651915
19661916 class A64I_exceptImpl opc, bits<2> ll, string asmop>
19671917 : A64I_exception
1968 !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,
1969 Sched<[WriteBr]> {
1918 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
19701919 let isBranch = 1;
19711920 let isTerminator = 1;
19721921 }
19971946 "extr\t$Rd, $Rn, $Rm, $LSB",
19981947 [(set i32:$Rd,
19991948 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
2000 NoItinerary>,
2001 Sched<[WriteALU, ReadALU, ReadALU]>;
1949 NoItinerary>;
20021950 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
20031951 (outs GPR64:$Rd),
20041952 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
20051953 "extr\t$Rd, $Rn, $Rm, $LSB",
20061954 [(set i64:$Rd,
20071955 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
2008 NoItinerary>,
2009 Sched<[WriteALU, ReadALU, ReadALU]>;
1956 NoItinerary>;
20101957
20111958 def : InstAlias<"ror $Rd, $Rs, $LSB",
20121959 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
20532000 multiclass A64I_fpcmpSignal type, bit imm, dag ins, dag pattern> {
20542001 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
20552002 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
2056 NoItinerary>,
2057 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2003 NoItinerary> {
20582004 let Defs = [NZCV];
20592005 }
20602006
20612007 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
2062 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,
2063 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2008 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
20642009 let Defs = [NZCV];
20652010 }
20662011 }
20892034 (outs),
20902035 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
20912036 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2092 [], NoItinerary>,
2093 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
2037 [], NoItinerary> {
20942038 let Defs = [NZCV];
20952039 }
20962040
21082052 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
21092053 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
21102054 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2111 [(set f32:$Rd,
2055 [(set f32:$Rd,
21122056 (simple_select f32:$Rn, f32:$Rm))],
2113 NoItinerary>,
2114 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2057 NoItinerary>;
21152058
21162059
21172060 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
21192062 "fcsel\t$Rd, $Rn, $Rm, $Cond",
21202063 [(set f64:$Rd,
21212064 (simple_select f64:$Rn, f64:$Rm))],
2122 NoItinerary>,
2123 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2065 NoItinerary>;
21242066 }
21252067
21262068 //===----------------------------------------------------------------------===//
21382080 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
21392081 !strconcat(asmstr, "\t$Rd, $Rn"),
21402082 [(set f32:$Rd, (opnode f32:$Rn))],
2141 NoItinerary>,
2142 Sched<[WriteFPALU, ReadFPALU]>;
2083 NoItinerary>;
21432084
21442085 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
21452086 !strconcat(asmstr, "\t$Rd, $Rn"),
21462087 [(set f64:$Rd, (opnode f64:$Rn))],
2147 NoItinerary>,
2148 Sched<[WriteFPALU, ReadFPALU]>;
2088 NoItinerary>;
21492089 }
21502090
21512091 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
21522092 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
21532093 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2154 let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
2155 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2156 }
2094 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
21572095
21582096 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
21592097 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
21822120 {0,0,0,1, DestReg.t1, DestReg.t0},
21832121 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
21842122 "fcvt\t$Rd, $Rn",
2185 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,
2186 Sched<[WriteFPALU, ReadFPALU]>;
2123 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
21872124
21882125 def FCVTds : A64I_fpdp1_fcvt;
21892126 def FCVThs : A64I_fpdp1_fcvt;
22082145 (ins FPR32:$Rn, FPR32:$Rm),
22092146 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
22102147 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2211 NoItinerary>,
2212 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2148 NoItinerary>;
22132149
22142150 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
22152151 (outs FPR64:$Rd),
22162152 (ins FPR64:$Rn, FPR64:$Rm),
22172153 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
22182154 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2219 NoItinerary>,
2220 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
2155 NoItinerary>;
22212156 }
22222157
22232158 let isCommutable = 1 in {
2224 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2225 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2226 }
2159 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
22272160 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
22282161
22292162 // No patterns for these.
22322165 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
22332166 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
22342167
2235 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2236 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2237 PatFrag<(ops node:$lhs, node:$rhs),
2238 (fneg (fmul node:$lhs, node:$rhs))> >;
2239 }
2240 }
2241
2242 let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
2243 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2244 }
2168 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2169 PatFrag<(ops node:$lhs, node:$rhs),
2170 (fneg (fmul node:$lhs, node:$rhs))> >;
2171 }
2172
2173 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
22452174 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
22462175
22472176 //===----------------------------------------------------------------------===//
22622191 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
22632192 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
22642193 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2265 NoItinerary>,
2266 Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;
2194 NoItinerary>;
22672195
22682196 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
22692197 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
23422270 // worth going for a multiclass here. Oh well.
23432271
23442272 class A64I_fptofix type, bits<3> opcode,
2345 RegisterClass GPR, RegisterClass FPR,
2346 ValueType DstTy, ValueType SrcTy,
2273 RegisterClass GPR, RegisterClass FPR,
2274 ValueType DstTy, ValueType SrcTy,
23472275 Operand scale_op, string asmop, SDNode cvtop>
23482276 : A64I_fpfixed
23492277 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
23502278 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
23512279 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2352 NoItinerary>,
2353 Sched<[WriteFPALU, ReadFPALU]>;
2280 NoItinerary>;
23542281
23552282 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
23562283 cvtfix_i32_op, "fcvtzs", fp_to_sint>;
23792306 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
23802307 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
23812308 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2382 NoItinerary>,
2383 Sched<[WriteFPALU, ReadFPALU]>;
2309 NoItinerary>;
23842310
23852311 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
23862312 cvtfix_i32_op, "scvtf", sint_to_fp>;
24072333 class A64I_fpintI type, bits<2> rmode, bits<3> opcode,
24082334 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
24092335 : A64I_fpint
2410 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,
2411 Sched<[WriteFPALU, ReadFPALU]>;
2336 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
24122337
24132338 multiclass A64I_fptointRM rmode, bit o2, string asmop> {
24142339 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
24942419 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
24952420 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
24962421 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2497 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,
2498 Sched<[WriteFPALU, ReadFPALU]>;
2422 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
24992423
25002424 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
25012425 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2502 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,
2503 Sched<[WriteFPALU, ReadFPALU]>;
2426 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
25042427 }
25052428
25062429 let Predicates = [HasFPARMv8] in {
25472470 (ins fmov_operand:$Imm8),
25482471 "fmov\t$Rd, $Imm8",
25492472 [(set VT:$Rd, fmov_operand:$Imm8)],
2550 NoItinerary>,
2551 Sched<[WriteFPALU]>;
2473 NoItinerary>;
25522474
25532475 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
25542476 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
25972519 class A64I_LDRlitSimple opc, bit v, RegisterClass OutReg,
25982520 list patterns = []>
25992521 : A64I_LDRlit
2600 "ldr\t$Rt, $Imm19", patterns, NoItinerary>,
2601 Sched<[WriteLd]>;
2522 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
26022523
26032524 let mayLoad = 1 in {
26042525 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
26192540 (outs GPR64:$Rt),
26202541 (ins ldrlit_label:$Imm19),
26212542 "ldrsw\t$Rt, $Imm19",
2622 [], NoItinerary>,
2623 Sched<[WriteLd]>;
2543 [], NoItinerary>;
26242544
26252545 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
26262546 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
26272547 "prfm\t$Rt, $Imm19",
2628 [], NoItinerary>,
2629 Sched<[WriteLd]>;
2548 [], NoItinerary>;
26302549 }
26312550
26322551 //===----------------------------------------------------------------------===//
27182637 multiclass A64I_LRex opcode> {
27192638 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
27202639 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2721 [], NoItinerary>,
2722 Sched<[WriteLd]>;
2640 [], NoItinerary>;
27232641
27242642 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
27252643 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2726 [], NoItinerary>,
2727 Sched<[WriteLd]>;
2644 [], NoItinerary>;
27282645
27292646 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
27302647 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2731 [], NoItinerary>,
2732 Sched<[WriteLd]>;
2648 [], NoItinerary>;
27332649
27342650 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
27352651 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2736 [], NoItinerary>,
2737 Sched<[WriteLd]>;
2652 [], NoItinerary>;
27382653 }
27392654
27402655 defm LDXR : A64I_LRex<"ldxr", 0b000>;
28602775 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
28612776 (outs GPR32:$Rt, GPR32:$Rt2),
28622777 (ins GPR64xsp0:$Rn),
2863 [], NoItinerary>,
2864 Sched<[WriteLd]>;
2778 [], NoItinerary>;
28652779
28662780 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
28672781 (outs GPR64:$Rt, GPR64:$Rt2),
28682782 (ins GPR64xsp0:$Rn),
2869 [], NoItinerary>,
2870 Sched<[WriteLd]>;
2783 [], NoItinerary>;
28712784 }
28722785
28732786 defm LDXP : A64I_LPex<"ldxp", 0b010>;
30903003 def _LDR : A64I_LSunsigimm
30913004 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
30923005 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3093 [], NoItinerary>,
3094 Sched<[WriteLd, ReadLd]> {
3006 [], NoItinerary> {
30953007 let mayLoad = 1;
30963008 }
30973009 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
31033015 (outs GPR:$Rt),
31043016 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
31053017 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3106 [], NoItinerary>,
3107 Sched<[WriteLd, ReadLd, ReadLd]>;
3018 [], NoItinerary>;
31083019
31093020 def _Xm_RegOffset_LDR : A64I_LSregoff
31103021 (outs GPR:$Rt),
31113022 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
31123023 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3113 [], NoItinerary>,
3114 Sched<[WriteLd, ReadLd, ReadLd]>;
3024 [], NoItinerary>;
31153025 }
31163026 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
31173027 (!cast(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
31473057 def _LDUR : A64I_LSunalimm
31483058 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
31493059 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3150 [], NoItinerary>,
3151 Sched<[WriteLd, ReadLd]> {
3060 [], NoItinerary> {
31523061 let mayLoad = 1;
31533062 }
31543063 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
31713080 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
31723081 (ins GPR64xsp:$Rn, simm9:$SImm9),
31733082 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3174 [], NoItinerary>,
3175 Sched<[WriteLd, ReadLd]> {
3083 [], NoItinerary> {
31763084 let mayLoad = 1;
31773085 let Constraints = "$Rn = $Rn_wb";
31783086 let DecoderMethod = "DecodeSingleIndexedInstruction";
31953103 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
31963104 (ins GPR64xsp:$Rn, simm9:$SImm9),
31973105 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3198 [], NoItinerary>,
3199 Sched<[WriteLd, ReadLd]> {
3106 [], NoItinerary> {
32003107 let mayLoad = 1;
32013108 let Constraints = "$Rn = $Rn_wb";
32023109 let DecoderMethod = "DecodeSingleIndexedInstruction";
32563163 (outs GPR32:$Rt),
32573164 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
32583165 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3259 [], NoItinerary>,
3260 Sched<[WriteLd, ReadLd]> {
3166 [], NoItinerary> {
32613167 let mayLoad = 1;
32623168 }
32633169 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
32673173 (outs GPR64:$Rt),
32683174 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
32693175 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3270 [], NoItinerary>,
3271 Sched<[WriteLd, ReadLd]> {
3176 [], NoItinerary> {
32723177 let mayLoad = 1;
32733178 }
32743179 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
32803185 (outs GPR32:$Rt),
32813186 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
32823187 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3283 [], NoItinerary>,
3284 Sched<[WriteLd, ReadLd, ReadLd]>;
3188 [], NoItinerary>;
32853189
32863190 def w_Xm_RegOffset : A64I_LSregoff
32873191 (outs GPR32:$Rt),
32883192 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
32893193 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3290 [], NoItinerary>,
3291 Sched<[WriteLd, ReadLd, ReadLd]>;
3194 [], NoItinerary>;
32923195
32933196 def x_Wm_RegOffset : A64I_LSregoff
32943197 (outs GPR64:$Rt),
32953198 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
32963199 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3297 [], NoItinerary>,
3298 Sched<[WriteLd, ReadLd, ReadLd]>;
3200 [], NoItinerary>;
32993201
33003202 def x_Xm_RegOffset : A64I_LSregoff
33013203 (outs GPR64:$Rt),
33023204 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
33033205 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3304 [], NoItinerary>,
3305 Sched<[WriteLd, ReadLd, ReadLd]>;
3206 [], NoItinerary>;
33063207 }
33073208 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
33083209 (!cast(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
33193220 (outs GPR32:$Rt),
33203221 (ins GPR64xsp:$Rn, simm9:$SImm9),
33213222 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3322 [], NoItinerary>,
3323 Sched<[WriteLd, ReadLd]>;
3223 [], NoItinerary>;
33243224
33253225 def x_U : A64I_LSunalimm
33263226 (outs GPR64:$Rt),
33273227 (ins GPR64xsp:$Rn, simm9:$SImm9),
33283228 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3329 [], NoItinerary>,
3330 Sched<[WriteLd, ReadLd]>;
3229 [], NoItinerary>;
33313230
33323231
33333232 // Post-indexed
33353234 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
33363235 (ins GPR64xsp:$Rn, simm9:$SImm9),
33373236 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3338 [], NoItinerary>,
3339 Sched<[WriteLd, ReadLd]> {
3237 [], NoItinerary> {
33403238 let Constraints = "$Rn = $Rn_wb";
33413239 let DecoderMethod = "DecodeSingleIndexedInstruction";
33423240 }
33453243 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
33463244 (ins GPR64xsp:$Rn, simm9:$SImm9),
33473245 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3348 [], NoItinerary>,
3349 Sched<[WriteLd, ReadLd]> {
3246 [], NoItinerary> {
33503247 let Constraints = "$Rn = $Rn_wb";
33513248 let DecoderMethod = "DecodeSingleIndexedInstruction";
33523249 }
33563253 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
33573254 (ins GPR64xsp:$Rn, simm9:$SImm9),
33583255 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3359 [], NoItinerary>,
3360 Sched<[WriteLd, ReadLd]> {
3256 [], NoItinerary> {
33613257 let Constraints = "$Rn = $Rn_wb";
33623258 let DecoderMethod = "DecodeSingleIndexedInstruction";
33633259 }
33663262 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
33673263 (ins GPR64xsp:$Rn, simm9:$SImm9),
33683264 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3369 [], NoItinerary>,
3370 Sched<[WriteLd, ReadLd]> {
3265 [], NoItinerary> {
33713266 let Constraints = "$Rn = $Rn_wb";
33723267 let DecoderMethod = "DecodeSingleIndexedInstruction";
33733268 }
33853280 (outs GPR64:$Rt),
33863281 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
33873282 "ldrsw\t$Rt, [$Rn, $UImm12]",
3388 [], NoItinerary>,
3389 Sched<[WriteLd, ReadLd]> {
3283 [], NoItinerary> {
33903284 let mayLoad = 1;
33913285 }
33923286 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
33963290 (outs GPR64:$Rt),
33973291 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
33983292 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3399 [], NoItinerary>,
3400 Sched<[WriteLd, ReadLd, ReadLd]>;
3293 [], NoItinerary>;
34013294
34023295 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
34033296 (outs GPR64:$Rt),
34043297 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
34053298 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3406 [], NoItinerary>,
3407 Sched<[WriteLd, ReadLd, ReadLd]>;
3299 [], NoItinerary>;
34083300 }
34093301 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
34103302 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
34153307 (outs GPR64:$Rt),
34163308 (ins GPR64xsp:$Rn, simm9:$SImm9),
34173309 "ldursw\t$Rt, [$Rn, $SImm9]",
3418 [], NoItinerary>,
3419 Sched<[WriteLd, ReadLd]> {
3310 [], NoItinerary> {
34203311 let mayLoad = 1;
34213312 }
34223313 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
34263317 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
34273318 (ins GPR64xsp:$Rn, simm9:$SImm9),
34283319 "ldrsw\t$Rt, [$Rn], $SImm9",
3429 [], NoItinerary>,
3430 Sched<[WriteLd, ReadLd]> {
3320 [], NoItinerary> {
34313321 let mayLoad = 1;
34323322 let Constraints = "$Rn = $Rn_wb";
34333323 let DecoderMethod = "DecodeSingleIndexedInstruction";
34373327 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
34383328 (ins GPR64xsp:$Rn, simm9:$SImm9),
34393329 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3440 [], NoItinerary>,
3441 Sched<[WriteLd, ReadLd]> {
3330 [], NoItinerary> {
34423331 let mayLoad = 1;
34433332 let Constraints = "$Rn = $Rn_wb";
34443333 let DecoderMethod = "DecodeSingleIndexedInstruction";
34513340 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
34523341 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
34533342 "prfm\t$Rt, [$Rn, $UImm12]",
3454 [], NoItinerary>,
3455 Sched<[WritePreLd, ReadPreLd]> {
3343 [], NoItinerary> {
34563344 let mayLoad = 1;
34573345 }
34583346 def : InstAlias<"prfm $Rt, [$Rn]",
34633351 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
34643352 GPR32:$Rm, dword_Wm_regext:$Ext),
34653353 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3466 [], NoItinerary>,
3467 Sched<[WritePreLd, ReadPreLd]>;
3354 [], NoItinerary>;
34683355 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
34693356 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
34703357 GPR64:$Rm, dword_Xm_regext:$Ext),
34713358 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3472 [], NoItinerary>,
3473 Sched<[WritePreLd, ReadPreLd]>;
3359 [], NoItinerary>;
34743360 }
34753361
34763362 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
34813367 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
34823368 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
34833369 "prfum\t$Rt, [$Rn, $SImm9]",
3484 [], NoItinerary>,
3485 Sched<[WritePreLd, ReadPreLd]> {
3370 [], NoItinerary> {
34863371 let mayLoad = 1;
34873372 }
34883373 def : InstAlias<"prfum $Rt, [$Rn]",
35023387 def _UnPriv_STR : A64I_LSunpriv
35033388 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
35043389 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3505 [], NoItinerary>,
3506 Sched<[WriteLd, ReadLd]> {
3390 [], NoItinerary> {
35073391 let mayStore = 1;
35083392 }
35093393
35133397 def _UnPriv_LDR : A64I_LSunpriv
35143398 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
35153399 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3516 [], NoItinerary>,
3517 Sched<[WriteLd, ReadLd]> {
3400 [], NoItinerary> {
35183401 let mayLoad = 1;
35193402 }
35203403
35433426 (outs GPR32:$Rt),
35443427 (ins GPR64xsp:$Rn, simm9:$SImm9),
35453428 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3546 [], NoItinerary>,
3547 Sched<[WriteLd, ReadLd]>;
3429 [], NoItinerary>;
35483430
35493431 def x : A64I_LSunpriv
35503432 (outs GPR64:$Rt),
35513433 (ins GPR64xsp:$Rn, simm9:$SImm9),
35523434 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3553 [], NoItinerary>,
3554 Sched<[WriteLd, ReadLd]>;
3435 [], NoItinerary>;
35553436 }
35563437
35573438 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
35723453 (outs GPR64:$Rt),
35733454 (ins GPR64xsp:$Rn, simm9:$SImm9),
35743455 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3575 [], NoItinerary>,
3576 Sched<[WriteLd, ReadLd]> {
3456 [], NoItinerary> {
35773457 let mayLoad = 1;
35783458 }
35793459 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
36353515 Operand simm7, string prefix> {
36363516 def _STR : A64I_LSPoffset
36373517 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3638 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3639 Sched<[WriteLd, ReadLd]> {
3518 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
36403519 let mayStore = 1;
36413520 let DecoderMethod = "DecodeLDSTPairInstruction";
36423521 }
36473526 def _LDR : A64I_LSPoffset
36483527 (outs SomeReg:$Rt, SomeReg:$Rt2),
36493528 (ins GPR64xsp:$Rn, simm7:$SImm7),
3650 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3651 Sched<[WriteLd, ReadLd]> {
3529 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
36523530 let mayLoad = 1;
36533531 let DecoderMethod = "DecodeLDSTPairInstruction";
36543532 }
36743552 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
36753553 (ins GPR64xsp:$Rn, simm7:$SImm7),
36763554 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3677 [], NoItinerary>,
3678 Sched<[WriteLd, ReadLd]> {
3555 [], NoItinerary> {
36793556 let mayLoad = 1;
36803557 let Constraints = "$Rn = $Rn_wb";
36813558 let DecoderMethod = "DecodeLDSTPairInstruction";
36943571 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
36953572 (ins GPR64xsp:$Rn, simm7:$SImm7),
36963573 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3697 [], NoItinerary>,
3698 Sched<[WriteLd, ReadLd]> {
3574 [], NoItinerary> {
36993575 let mayLoad = 1;
37003576 let Constraints = "$Rn = $Rn_wb";
37013577 let DecoderMethod = "DecodeLDSTPairInstruction";
37143590 def _NonTemp_LDR : A64I_LSPnontemp
37153591 (outs SomeReg:$Rt, SomeReg:$Rt2),
37163592 (ins GPR64xsp:$Rn, simm7:$SImm7),
3717 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3718 Sched<[WriteLd, ReadLd]> {
3593 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
37193594 let mayLoad = 1;
37203595 let DecoderMethod = "DecodeLDSTPairInstruction";
37213596 }
37403615 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
37413616 (outs GPR64:$Rt, GPR64:$Rt2),
37423617 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3743 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3744 Sched<[WriteLd, ReadLd]> {
3618 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
37453619 let mayLoad = 1;
37463620 let DecoderMethod = "DecodeLDSTPairInstruction";
37473621 }
37623636 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
37633637 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
37643638 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3765 [], NoItinerary>,
3766 Sched<[WriteLd, ReadLd]> {
3639 [], NoItinerary> {
37673640 let mayLoad = 1;
37683641 let Constraints = "$Rn = $Rn_wb";
37693642 let DecoderMethod = "DecodeLDSTPairInstruction";
38083681 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
38093682 [(set i32:$Rd,
38103683 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3811 NoItinerary>,
3812 Sched<[WriteALU, ReadALU]>;
3684 NoItinerary>;
38133685
38143686 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
38153687 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
38163688 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
38173689 [(set i64:$Rd,
38183690 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3819 NoItinerary>,
3820 Sched<[WriteALU, ReadALU]>;
3691 NoItinerary>;
38213692 }
38223693
38233694 defm AND : A64I_logimmSizes<0b00, "and", and>;
38283699 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
38293700 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
38303701 "ands\t$Rd, $Rn, $Imm",
3831 [], NoItinerary>,
3832 Sched<[WriteALU, ReadALU]>;
3702 [], NoItinerary>;
38333703
38343704 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
38353705 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
38363706 "ands\t$Rd, $Rn, $Imm",
3837 [], NoItinerary>,
3838 Sched<[WriteALU, ReadALU]>;
3707 [], NoItinerary>;
38393708 }
38403709
38413710
38803749 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
38813750 !cast("lsl_operand_" # ty):$Imm6))
38823751 )],
3883 NoItinerary>,
3884 Sched<[WriteALU, ReadALU, ReadALU]>;
3752 NoItinerary>;
38853753
38863754 def _lsr : A64I_logicalshift
38873755 (outs GPR:$Rd),
38913759 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
38923760 !cast("lsr_operand_" # ty):$Imm6))
38933761 )],
3894 NoItinerary>,
3895 Sched<[WriteALU, ReadALU, ReadALU]>;
3762 NoItinerary>;
38963763
38973764 def _asr : A64I_logicalshift
38983765 (outs GPR:$Rd),
39023769 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
39033770 !cast("asr_operand_" # ty):$Imm6))
39043771 )],
3905 NoItinerary>,
3906 Sched<[WriteALU, ReadALU, ReadALU]>;
3772 NoItinerary>;
39073773
39083774 def _ror : A64I_logicalshift
39093775 (outs GPR:$Rd),
39133779 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
39143780 !cast("ror_operand_" # ty):$Imm6))
39153781 )],
3916 NoItinerary>,
3917 Sched<[WriteALU, ReadALU, ReadALU]>;
3782 NoItinerary>;
39183783 }
39193784
39203785 def _noshift
39693834 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
39703835 !cast("lsl_operand_" # ty):$Imm6)),
39713836 0, signed_cond))],
3972 NoItinerary>,
3973 Sched<[WriteALU, ReadALU, ReadALU]>;
3837 NoItinerary>;
39743838
39753839
39763840 def _lsr : A64I_logicalshift
39813845 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
39823846 !cast("lsr_operand_" # ty):$Imm6)),
39833847 0, signed_cond))],
3984 NoItinerary>,
3985 Sched<[WriteALU, ReadALU, ReadALU]>;
3848 NoItinerary>;
39863849
39873850 def _asr : A64I_logicalshift
39883851 (outs),
39923855 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
39933856 !cast("asr_operand_" # ty):$Imm6)),
39943857 0, signed_cond))],
3995 NoItinerary>,
3996 Sched<[WriteALU, ReadALU, ReadALU]>;
3858 NoItinerary>;
39973859
39983860 def _ror : A64I_logicalshift
39993861 (outs),
40033865 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
40043866 !cast("ror_operand_" # ty):$Imm6)),
40053867 0, signed_cond))],
4006 NoItinerary>,
4007 Sched<[WriteALU, ReadALU, ReadALU]>;
3868 NoItinerary>;
40083869 }
40093870
40103871 def _noshift : InstAlias<"tst $Rn, $Rm",
40273888 "mvn\t$Rd, $Rm, $Imm6",
40283889 [(set ty:$Rd, (not (shl ty:$Rm,
40293890 !cast("lsl_operand_" # ty):$Imm6)))],
4030 NoItinerary>,
4031 Sched<[WriteALU, ReadALU, ReadALU]>;
3891 NoItinerary>;
40323892
40333893
40343894 def _lsr : A64I_logicalshift
40383898 "mvn\t$Rd, $Rm, $Imm6",
40393899 [(set ty:$Rd, (not (srl ty:$Rm,
40403900 !cast("lsr_operand_" # ty):$Imm6)))],
4041 NoItinerary>,
4042 Sched<[WriteALU, ReadALU, ReadALU]>;
3901 NoItinerary>;
40433902
40443903 def _asr : A64I_logicalshift
40453904 (outs GPR:$Rd),
40483907 "mvn\t$Rd, $Rm, $Imm6",
40493908 [(set ty:$Rd, (not (sra ty:$Rm,
40503909 !cast("asr_operand_" # ty):$Imm6)))],
4051 NoItinerary>,
4052 Sched<[WriteALU, ReadALU, ReadALU]>;
3910 NoItinerary>;
40533911
40543912 def _ror : A64I_logicalshift
40553913 (outs GPR:$Rd),
40583916 "mvn\t$Rd, $Rm, $Imm6",
40593917 [(set ty:$Rd, (not (rotr ty:$Rm,
40603918 !cast("lsl_operand_" # ty):$Imm6)))],
4061 NoItinerary>,
4062 Sched<[WriteALU, ReadALU, ReadALU]>;
3919 NoItinerary>;
40633920 }
40643921
40653922 def _noshift : InstAlias<"mvn $Rn, $Rm",
41143971
41153972 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
41163973 !strconcat(asmop, "\t$Rd, $FullImm"),
4117 [], NoItinerary>,
4118 Sched<[WriteALU]> {
3974 [], NoItinerary> {
41193975 bits<18> FullImm;
41203976 let UImm16 = FullImm{15-0};
41213977 let Shift = FullImm{17-16};
41233979
41243980 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
41253981 !strconcat(asmop, "\t$Rd, $FullImm"),
4126 [], NoItinerary>,
4127 Sched<[WriteALU]> {
3982 [], NoItinerary> {
41283983 bits<18> FullImm;
41293984 let UImm16 = FullImm{15-0};
41303985 let Shift = FullImm{17-16};
42324087
42334088 let hasSideEffects = 0 in {
42344089 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4235 "adr\t$Rd, $Label", [], NoItinerary>,
4236 Sched<[WriteALUs]>;
4090 "adr\t$Rd, $Label", [], NoItinerary>;
42374091
42384092 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4239 "adrp\t$Rd, $Label", [], NoItinerary>,
4240 Sched<[WriteALUs]>;
4093 "adrp\t$Rd, $Label", [], NoItinerary>;
42414094 }
42424095
42434096 //===----------------------------------------------------------------------===//
45234376 "tbz\t$Rt, $Imm, $Label",
45244377 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
45254378 A64eq, bb:$Label)],
4526 NoItinerary>,
4527 Sched<[WriteBr]>;
4379 NoItinerary>;
45284380
45294381 def TBNZxii : A64I_TBimm<0b1, (outs),
45304382 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
45314383 "tbnz\t$Rt, $Imm, $Label",
45324384 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
45334385 A64ne, bb:$Label)],
4534 NoItinerary>,
4535 Sched<[WriteBr]>;
4386 NoItinerary>;
45364387
45374388
45384389 // Note, these instructions overlap with the above 64-bit patterns. This is
45444395 "tbz\t$Rt, $Imm, $Label",
45454396 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
45464397 A64eq, bb:$Label)],
4547 NoItinerary>,
4548 Sched<[WriteBr]> {
4398 NoItinerary> {
45494399 let Imm{5} = 0b0;
45504400 }
45514401
45544404 "tbnz\t$Rt, $Imm, $Label",
45554405 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
45564406 A64ne, bb:$Label)],
4557 NoItinerary>,
4558 Sched<[WriteBr]> {
4407 NoItinerary> {
45594408 let Imm{5} = 0b0;
45604409 }
45614410 }
45904439 class A64I_BimmImpl patterns, Operand lbl_type>
45914440 : A64I_Bimm
45924441 !strconcat(asmop, "\t$Label"), patterns,
4593 NoItinerary>,
4594 Sched<[WriteBr]>;
4442 NoItinerary>;
45954443
45964444 let isBranch = 1 in {
45974445 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
45994447 let isBarrier = 1;
46004448 }
46014449
4602 let SchedRW = [WriteBrL] in {
4603 def BLimm : A64I_BimmImpl<0b1, "bl",
4604 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4605 let isCall = 1;
4606 let Defs = [X30];
4607 }
4450 def BLimm : A64I_BimmImpl<0b1, "bl",
4451 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4452 let isCall = 1;
4453 let Defs = [X30];
46084454 }
46094455 }
46104456
46214467 dag outs, dag ins, string asmstr, list patterns,
46224468 InstrItinClass itin = NoItinerary>
46234469 : A64I_Breg
4624 outs, ins, asmstr, patterns, itin>,
4625 Sched<[WriteBr]> {
4470 outs, ins, asmstr, patterns, itin> {
46264471 let isBranch = 1;
46274472 let isIndirectBranch = 1;
46284473 }
46384483 let isTerminator = 1;
46394484 }
46404485
4641 let SchedRW = [WriteBrL] in {
4642 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4643 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4644 let isBarrier = 0;
4645 let isCall = 1;
4646 let Defs = [X30];
4647 }
4486 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4487 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4488 let isBarrier = 0;
4489 let isCall = 1;
4490 let Defs = [X30];
46484491 }
46494492
46504493 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
66 //
77 //===----------------------------------------------------------------------===//
88
9 //===----------------------------------------------------------------------===//
10 // Generic processor itineraries for legacy compatibility.
11
129 def GenericItineraries : ProcessorItineraries<[], [], []>;
13
14
15 //===----------------------------------------------------------------------===//
16 // Base SchedReadWrite types
17
18 // Basic ALU
19 def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation
20 def WriteALUs : SchedWrite; // Shift only with no ALU operation
21 def ReadALU : SchedRead; // Operand not needed for shifting
22 def ReadALUs : SchedRead; // Operand needed for shifting
23
24 // Multiply with optional accumulate
25 def WriteMAC : SchedWrite;
26 def ReadMAC : SchedRead;
27
28 // Compares
29 def WriteCMP : SchedWrite;
30 def ReadCMP : SchedRead;
31
32 // Division
33 def WriteDiv : SchedWrite;
34 def ReadDiv : SchedRead;
35
36 // Loads
37 def WriteLd : SchedWrite;
38 def WritePreLd : SchedWrite;
39 def ReadLd : SchedRead;
40 def ReadPreLd : SchedRead;
41
42 // Branches
43 def WriteBr : SchedWrite;
44 def WriteBrL : SchedWrite;
45 def ReadBr : SchedRead;
46
47 // Floating Point ALU
48 def WriteFPALU : SchedWrite;
49 def ReadFPALU : SchedRead;
50
51 // Floating Point MAC, Mul, Div, Sqrt
52 // Most processors will simply send all of these down a dedicated pipe, but
53 // they're explicitly seperated here for flexibility of modeling later. May
54 // consider consolidating them into a single WriteFPXXXX type in the future.
55 def WriteFPMAC : SchedWrite;
56 def WriteFPMul : SchedWrite;
57 def WriteFPDiv : SchedWrite;
58 def WriteFPSqrt : SchedWrite;
59 def ReadFPMAC : SchedRead;
60 def ReadFPMul : SchedRead;
61 def ReadFPDiv : SchedRead;
62 def ReadFPSqrt : SchedRead;
63
64 // Noop
65 def WriteNoop : SchedWrite;
66
67
68 //===----------------------------------------------------------------------===//
69 // Subtarget specific Machine Models.
70
71 include "AArch64ScheduleA53.td"
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lib/Target/AArch64/AArch64ScheduleA53.td less more
None //=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the itinerary class data for the ARM Cortex A53 processors.
10 //
11 //===----------------------------------------------------------------------===//
12
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the simpler per-operand machine model.
15 // This works with MachineScheduler. See MCSchedModel.h for details.
16
17 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
18 def CortexA53Model : SchedMachineModel {
19 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
20 let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
21 let LoadLatency = 2; // Optimistic load latency assuming bypass.
22 // This is overriden by OperandCycles if the
23 // Itineraries are queried instead.
24 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
25 // Specification - Instruction Timings"
26 // v 1.0 Spreadsheet
27 }
28
29
30 //===----------------------------------------------------------------------===//
31 // Define each kind of processor resource and number available.
32
33 // Modeling each pipeline as a ProcResource using the default BufferSize = -1.
34 // Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
35 // current configuration performs better with the basic latencies provided so
36 // far. Will revisit BufferSize once the latency information is more accurate.
37
38 let SchedModel = CortexA53Model in {
39
40 def A53UnitALU : ProcResource<2>; // Int ALU
41 def A53UnitMAC : ProcResource<1>; // Int MAC
42 def A53UnitDiv : ProcResource<1>; // Int Division
43 def A53UnitLdSt : ProcResource<1>; // Load/Store
44 def A53UnitB : ProcResource<1>; // Branch
45 def A53UnitFPALU : ProcResource<1>; // FP ALU
46 def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
47
48
49 //===----------------------------------------------------------------------===//
50 // Subtarget-specific SchedWrite types which both map the ProcResources and
51 // set the latency.
52
53 // Issue - Every instruction must consume an A53WriteIssue. Optionally,
54 // instructions that cannot be dual-issued will also include the
55 // A53WriteIssue2nd in their SchedRW list. That second WriteRes will
56 // ensure that a second issue slot is consumed.
57 def A53WriteIssue : SchedWriteRes<[]>;
58 def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
59
60 // ALU - These are reduced to 1 despite a true latency of 4 in order to easily
61 // model forwarding logic. Once forwarding is properly modelled, then
62 // they'll be corrected.
63 def : WriteRes { let Latency = 1; }
64 def : WriteRes { let Latency = 1; }
65 def : WriteRes { let Latency = 1; }
66
67 // MAC
68 def : WriteRes { let Latency = 4; }
69
70 // Div
71 def : WriteRes { let Latency = 4; }
72
73 // Load
74 def : WriteRes { let Latency = 4; }
75 def : WriteRes { let Latency = 4; }
76
77 // Branch
78 def : WriteRes;
79 def : WriteRes;
80
81 // FP ALU
82 def : WriteRes {let Latency = 6; }
83
84 // FP MAC, Mul, Div, Sqrt
85 // Using Double Precision numbers for now as a worst case. Additionally, not
86 // modeling the exact hazard but instead treating the whole pipe as a hazard.
87 // As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
88 // have a total latency of 33 and 32 respectively but only a hazard of 29 and
89 // 28 (double-prescion example).
90 def : WriteRes { let Latency = 10; }
91 def : WriteRes { let Latency = 6; }
92 def : WriteRes { let Latency = 33;
93 let ResourceCycles = [29]; }
94 def : WriteRes { let Latency = 32;
95 let ResourceCycles = [28]; }
96
97
98 //===----------------------------------------------------------------------===//
99 // Subtarget-specific SchedRead types.
100
101 // No forwarding defined for ReadALU yet.
102 def : ReadAdvance;
103
104 // No forwarding defined for ReadCMP yet.
105 def : ReadAdvance;
106
107 // No forwarding defined for ReadBr yet.
108 def : ReadAdvance;
109
110 // No forwarding defined for ReadMAC yet.
111 def : ReadAdvance;
112
113 // No forwarding defined for ReadDiv yet.
114 def : ReadAdvance;
115
116 // No forwarding defined for ReadLd, ReadPreLd yet.
117 def : ReadAdvance;
118 def : ReadAdvance;
119
120 // No forwarding defined for ReadFPALU yet.
121 def : ReadAdvance;
122
123 // No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
124 def : ReadAdvance;
125 def : ReadAdvance;
126 def : ReadAdvance;
127 def : ReadAdvance;
128
129 }
2828 class AArch64Subtarget : public AArch64GenSubtargetInfo {
2929 virtual void anchor();
3030 protected:
31 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
32
33 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
34 ARMProcFamilyEnum ARMProcFamily;
35
3631 bool HasFPARMv8;
3732 bool HasNEON;
3833 bool HasCrypto;
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test/CodeGen/AArch64/misched-basic-A53.ll less more
None ; REQUIRES: asserts
1 ; RUN: llc < %s -march=aarch64 -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
2 ;
3 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
4 ; much higher than the ADD instructions in order to hide latency. When not
5 ; specifying a subtarget, the MADD will remain near the end of the block.
6 ; CHECK: main
7 ; CHECK: *** Final schedule for BB#2 ***
8 ; CHECK: SU(13)
9 ; CHECK: MADDwwww
10 ; CHECK: SU(4)
11 ; CHECK: ADDwwi_lsl0_s
12 ; CHECK: ********** MI Scheduling **********
13 @main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
14 @main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
15
16 ; Function Attrs: nounwind
17 define i32 @main() #0 {
18 entry:
19 %retval = alloca i32, align 4
20 %x = alloca [8 x i32], align 4
21 %y = alloca [8 x i32], align 4
22 %i = alloca i32, align 4
23 %xx = alloca i32, align 4
24 %yy = alloca i32, align 4
25 store i32 0, i32* %retval
26 %0 = bitcast [8 x i32]* %x to i8*
27 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
28 %1 = bitcast [8 x i32]* %y to i8*
29 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
30 store i32 0, i32* %xx, align 4
31 store i32 0, i32* %yy, align 4
32 store i32 0, i32* %i, align 4
33 br label %for.cond
34
35 for.cond: ; preds = %for.inc, %entry
36 %2 = load i32* %i, align 4
37 %cmp = icmp slt i32 %2, 8
38 br i1 %cmp, label %for.body, label %for.end
39
40 for.body: ; preds = %for.cond
41 %3 = load i32* %i, align 4
42 %idxprom = sext i32 %3 to i64
43 %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
44 %4 = load i32* %arrayidx, align 4
45 %add = add nsw i32 %4, 1
46 store i32 %add, i32* %xx, align 4
47 %5 = load i32* %xx, align 4
48 %add1 = add nsw i32 %5, 12
49 store i32 %add1, i32* %xx, align 4
50 %6 = load i32* %xx, align 4
51 %add2 = add nsw i32 %6, 23
52 store i32 %add2, i32* %xx, align 4
53 %7 = load i32* %xx, align 4
54 %add3 = add nsw i32 %7, 34
55 store i32 %add3, i32* %xx, align 4
56 %8 = load i32* %i, align 4
57 %idxprom4 = sext i32 %8 to i64
58 %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
59 %9 = load i32* %arrayidx5, align 4
60 %10 = load i32* %yy, align 4
61 %mul = mul nsw i32 %10, %9
62 store i32 %mul, i32* %yy, align 4
63 br label %for.inc
64
65 for.inc: ; preds = %for.body
66 %11 = load i32* %i, align 4
67 %inc = add nsw i32 %11, 1
68 store i32 %inc, i32* %i, align 4
69 br label %for.cond
70
71 for.end: ; preds = %for.cond
72 %12 = load i32* %xx, align 4
73 %13 = load i32* %yy, align 4
74 %add6 = add nsw i32 %12, %13
75 ret i32 %add6
76 }
77
78 ; Function Attrs: nounwind
79 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
80
81 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
82 attributes #1 = { nounwind }