llvm.org GIT mirror llvm / 16859aa
MC: Remove MCSubtargetInfo() default constructor Force all creators of `MCSubtargetInfo` to immediately initialize it, merging the default constructor and the initializer into an initializing constructor. Besides cleaning up the code a little, this makes it clear that the initializer is never called again later. Out-of-tree backends need a trivial change: instead of calling: auto *X = new MCSubtargetInfo(); InitXYZMCSubtargetInfo(X, ...); return X; they should call: return createXYZMCSubtargetInfoImpl(...); There's no real functionality change here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241957 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan P. N. Exon Smith 4 years ago
18 changed file(s) with 51 addition(s) and 73 deletion(s). Raw diff Collapse all Expand all
4343 const unsigned *ForwardingPaths; // Forwarding paths
4444 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
4545
46 MCSubtargetInfo() = delete;
47
4648 public:
47 void InitMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
48 ArrayRef PF,
49 ArrayRef PD,
50 const SubtargetInfoKV *ProcSched,
51 const MCWriteProcResEntry *WPR,
52 const MCWriteLatencyEntry *WL,
53 const MCReadAdvanceEntry *RA, const InstrStage *IS,
54 const unsigned *OC, const unsigned *FP);
49 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
50 ArrayRef PF,
51 ArrayRef PD,
52 const SubtargetInfoKV *ProcSched,
53 const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
54 const MCReadAdvanceEntry *RA, const InstrStage *IS,
55 const unsigned *OC, const unsigned *FP);
5556
5657 /// getTargetTriple - Return the target triple string.
5758 const Triple &getTargetTriple() const { return TargetTriple; }
4343 class TargetSubtargetInfo : public MCSubtargetInfo {
4444 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
4545 void operator=(const TargetSubtargetInfo &) = delete;
46 TargetSubtargetInfo() = delete;
4647
4748 protected: // Can only create subclasses...
48 TargetSubtargetInfo();
49 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
50 ArrayRef PF,
51 ArrayRef PD,
52 const SubtargetInfoKV *ProcSched,
53 const MCWriteProcResEntry *WPR,
54 const MCWriteLatencyEntry *WL,
55 const MCReadAdvanceEntry *RA, const InstrStage *IS,
56 const unsigned *OC, const unsigned *FP);
4957
5058 public:
5159 // AntiDepBreakMode - Type of anti-dependence breaking that should
2828 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
2929 }
3030
31 void MCSubtargetInfo::InitMCSubtargetInfo(
31 MCSubtargetInfo::MCSubtargetInfo(
3232 const Triple &TT, StringRef C, StringRef FS,
3333 ArrayRef PF, ArrayRef PD,
3434 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
3535 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
36 const InstrStage *IS, const unsigned *OC, const unsigned *FP) {
37 TargetTriple = TT;
38 CPU = C;
39 ProcFeatures = PF;
40 ProcDesc = PD;
41 ProcSchedModels = ProcSched;
42 WriteProcResTable = WPR;
43 WriteLatencyTable = WL;
44 ReadAdvanceTable = RA;
45
46 Stages = IS;
47 OperandCycles = OC;
48 ForwardingPaths = FP;
49
36 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
37 : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
38 ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
39 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
5040 InitMCProcessorInfo(CPU, FS);
5141 }
5242
4141
4242 static MCSubtargetInfo *
4343 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
44 MCSubtargetInfo *X = new MCSubtargetInfo();
45
4644 if (CPU.empty())
4745 CPU = "generic";
4846
49 InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
50 return X;
47 return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
5148 }
5249
5350 static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
5151
5252 static MCSubtargetInfo *
5353 createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
54 MCSubtargetInfo * X = new MCSubtargetInfo();
55 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
56 return X;
54 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
5755 }
5856
5957 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT,
256256 ArchFS = FS;
257257 }
258258
259 MCSubtargetInfo *X = new MCSubtargetInfo();
260 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
261 return X;
259 return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
262260 }
263261
264262 static MCInstrInfo *createARMMCInstrInfo() {
4747
4848 static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
4949 StringRef CPU, StringRef FS) {
50 MCSubtargetInfo *X = new MCSubtargetInfo();
51 InitBPFMCSubtargetInfo(X, TT, CPU, FS);
52 return X;
50 return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
5351 }
5452
5553 static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
5353
5454 static MCSubtargetInfo *
5555 createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
56 MCSubtargetInfo *X = new MCSubtargetInfo();
57 InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
58 return X;
56 return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
5957 }
6058
6159 namespace {
4444
4545 static MCSubtargetInfo *
4646 createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
47 MCSubtargetInfo *X = new MCSubtargetInfo();
48 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
49 return X;
47 return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
5048 }
5149
5250 static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT,
6767 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
6868 StringRef CPU, StringRef FS) {
6969 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
70 MCSubtargetInfo *X = new MCSubtargetInfo();
71 InitMipsMCSubtargetInfo(X, TT, CPU, FS);
72 return X;
70 return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
7371 }
7472
7573 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
4545
4646 static MCSubtargetInfo *
4747 createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
48 MCSubtargetInfo *X = new MCSubtargetInfo();
49 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
50 return X;
48 return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
5149 }
5250
5351 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT,
6363
6464 static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
6565 StringRef CPU, StringRef FS) {
66 MCSubtargetInfo *X = new MCSubtargetInfo();
67 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
68 return X;
66 return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
6967 }
7068
7169 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
6464
6565 static MCSubtargetInfo *
6666 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
67 MCSubtargetInfo *X = new MCSubtargetInfo();
6867 if (CPU.empty())
6968 CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
70 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
71 return X;
69 return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
7270 }
7371
7472 // Code models. Some only make sense for 64-bit code.
155155
156156 static MCSubtargetInfo *
157157 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
158 MCSubtargetInfo *X = new MCSubtargetInfo();
159 InitSystemZMCSubtargetInfo(X, TT, CPU, FS);
160 return X;
158 return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
161159 }
162160
163161 static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT,
1818 //---------------------------------------------------------------------------
1919 // TargetSubtargetInfo Class
2020 //
21 TargetSubtargetInfo::TargetSubtargetInfo() {}
21 TargetSubtargetInfo::TargetSubtargetInfo(
22 const Triple &TT, StringRef CPU, StringRef FS,
23 ArrayRef PF, ArrayRef PD,
24 const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
25 const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
26 const InstrStage *IS, const unsigned *OC, const unsigned *FP)
27 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
28 }
2229
2330 TargetSubtargetInfo::~TargetSubtargetInfo() {}
2431
8787 if (CPUName.empty())
8888 CPUName = "generic";
8989
90 MCSubtargetInfo *X = new MCSubtargetInfo();
91 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
92 return X;
90 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
9391 }
9492
9593 static MCInstrInfo *createX86MCInstrInfo() {
4747
4848 static MCSubtargetInfo *
4949 createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
50 MCSubtargetInfo *X = new MCSubtargetInfo();
51 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
52 return X;
50 return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
5351 }
5452
5553 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
14341434 #endif
14351435
14361436 // MCInstrInfo initialization routine.
1437 OS << "static inline void Init" << Target
1438 << "MCSubtargetInfo(MCSubtargetInfo *II, "
1437 OS << "static inline MCSubtargetInfo *create" << Target
1438 << "MCSubtargetInfoImpl("
14391439 << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
1440 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
1440 OS << " return new MCSubtargetInfo(TT, CPU, FS, ";
14411441 if (NumFeatures)
14421442 OS << Target << "FeatureKV, ";
14431443 else
15171517
15181518 OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
15191519 << "StringRef FS)\n"
1520 << " : TargetSubtargetInfo() {\n"
1521 << " InitMCSubtargetInfo(TT, CPU, FS, ";
1520 << " : TargetSubtargetInfo(TT, CPU, FS, ";
15221521 if (NumFeatures)
15231522 OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
15241523 else
15271526 OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
15281527 else
15291528 OS << "None, ";
1530 OS << '\n'; OS.indent(22);
1529 OS << '\n'; OS.indent(24);
15311530 OS << Target << "ProcSchedKV, "
15321531 << Target << "WriteProcResTable, "
15331532 << Target << "WriteLatencyTable, "
15341533 << Target << "ReadAdvanceTable, ";
1535 OS << '\n'; OS.indent(22);
1534 OS << '\n'; OS.indent(24);
15361535 if (SchedModels.hasItineraries()) {
15371536 OS << Target << "Stages, "
15381537 << Target << "OperandCycles, "
15391538 << Target << "ForwardingPaths";
15401539 } else
15411540 OS << "0, 0, 0";
1542 OS << ");\n}\n\n";
1541 OS << ") {}\n\n";
15431542
15441543 EmitSchedModelHelpers(ClassName, OS);
15451544