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The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63195 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
3 changed file(s) with 40 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
906906 cvtsi2ss 8($esp), %xmm0
907907 since we know the stack slot is already zext'd.
908908
909 //===---------------------------------------------------------------------===//
910
911 Consider using movlps instead of movsd to implement (scalar_to_vector (loadf64))
912 when code size is critical. movlps is slower than movsd on core2 but it's one
913 byte shorter.
30183018 let AddedComplexity = 20 in {
30193019 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
30203020 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
3021 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3021 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
30223022 MOVLP_shuffle_mask)),
30233023 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3024 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3024 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
30253025 MOVLP_shuffle_mask)),
30263026 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3027 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3027 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
30283028 MOVHP_shuffle_mask)),
30293029 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3030 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3030 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
30313031 MOVHP_shuffle_mask)),
30323032 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
30333033
3034 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3035 (bc_v4i32 (memopv2i64 addr:$src2)),
3034 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
30363035 MOVLP_shuffle_mask)),
30373036 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3038 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3037 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
30393038 MOVLP_shuffle_mask)),
30403039 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3041 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3042 (bc_v4i32 (memopv2i64 addr:$src2)),
3040 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
30433041 MOVHP_shuffle_mask)),
30443042 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3045 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3043 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
30463044 MOVHP_shuffle_mask)),
30473045 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
30483046 }
30493047
30503048 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
30513049 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3052 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3050 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
30533051 MOVLP_shuffle_mask)), addr:$src1),
30543052 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3055 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3053 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
30563054 MOVLP_shuffle_mask)), addr:$src1),
30573055 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3058 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3056 def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
30593057 MOVHP_shuffle_mask)), addr:$src1),
30603058 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3061 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3059 def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
30623060 MOVHP_shuffle_mask)), addr:$src1),
30633061 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
30643062
30653063 def : Pat<(store (v4i32 (vector_shuffle
3066 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3064 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
30673065 MOVLP_shuffle_mask)), addr:$src1),
30683066 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3069 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3067 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
30703068 MOVLP_shuffle_mask)), addr:$src1),
30713069 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
30723070 def : Pat<(store (v4i32 (vector_shuffle
3073 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3071 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
30743072 MOVHP_shuffle_mask)), addr:$src1),
30753073 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3076 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3074 def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
30773075 MOVHP_shuffle_mask)), addr:$src1),
30783076 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
30793077
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movlps
1 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movsd
2 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep movups
3 ; rdar://6523650
4
5 %struct.vector4_t = type { <4 x float> }
6
7 define void @swizzle(i8* nocapture %a, %struct.vector4_t* nocapture %b, %struct.vector4_t* nocapture %c) nounwind {
8 entry:
9 %0 = getelementptr %struct.vector4_t* %b, i32 0, i32 0 ; <<4 x float>*> [#uses=2]
10 %1 = load <4 x float>* %0, align 4 ; <<4 x float>> [#uses=1]
11 %tmp.i = bitcast i8* %a to double* ; [#uses=1]
12 %tmp1.i = load double* %tmp.i ; [#uses=1]
13 %2 = insertelement <2 x double> undef, double %tmp1.i, i32 0 ; <<2 x double>> [#uses=1]
14 %tmp2.i = bitcast <2 x double> %2 to <4 x float> ; <<4 x float>> [#uses=1]
15 %3 = shufflevector <4 x float> %1, <4 x float> %tmp2.i, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x float>> [#uses=1]
16 store <4 x float> %3, <4 x float>* %0, align 4
17 ret void
18 }