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[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336295 91177308-0d34-0410-b5e6-96231b3b80d8 Stefan Pintilie 1 year, 11 months ago
77 changed file(s) with 476 addition(s) and 495 deletion(s). Raw diff Collapse all Expand all
2323 #include "llvm/Analysis/TargetTransformInfo.h"
2424 #include "llvm/CodeGen/Passes.h"
2525 #include "llvm/CodeGen/TargetPassConfig.h"
26 #include "llvm/CodeGen/MachineScheduler.h"
2627 #include "llvm/IR/Attributes.h"
2728 #include "llvm/IR/DataLayout.h"
2829 #include "llvm/IR/Function.h"
302303 class PPCPassConfig : public TargetPassConfig {
303304 public:
304305 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
305 : TargetPassConfig(TM, PM) {}
306 : TargetPassConfig(TM, PM) {
307 // At any optimization level above -O0 we use the Machine Scheduler and not
308 // the default Post RA List Scheduler.
309 if (TM.getOptLevel() != CodeGenOpt::None)
310 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
311 }
306312
307313 PPCTargetMachine &getPPCTargetMachine() const {
308314 return getTM();
1414 ; CHECK-NEXT: lbzx 3, 4, 3
1515 ; CHECK-NEXT: ld 4, .LC1@toc@l(5)
1616 ; CHECK-NEXT: subfic 3, 3, 1
17 ; CHECK-NEXT: ld 4, 0(4)
1718 ; CHECK-NEXT: extsw 3, 3
18 ; CHECK-NEXT: ld 4, 0(4)
1919 ; CHECK-NEXT: sldi 3, 3, 2
2020 ; CHECK-NEXT: lwzx 3, 4, 3
2121 ; CHECK-NEXT: blr
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o - | FileCheck %s
12
23 define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
78 ; CHECK-NEXT: stwu 1, -464(1)
89 ; CHECK-NEXT: lis 3, .LCPI0_0@ha
910 ; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill
11 ; CHECK-NEXT: mfcr 12
12 ; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
1013 ; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill
1114 ; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill
12 ; CHECK-NEXT: lfs 27, .LCPI0_0@l(3)
13 ; CHECK-NEXT: mfcr 12
1415 ; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
1516 ; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
1617 ; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
1718 ; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
19 ; CHECK-NEXT: fcmpu 0, 2, 27
1820 ; CHECK-NEXT: stw 12, 408(1)
21 ; CHECK-NEXT: fcmpu 1, 1, 27
1922 ; CHECK-NEXT: stfd 2, 376(1)
23 ; CHECK-NEXT: crand 20, 6, 0
2024 ; CHECK-NEXT: stfd 1, 384(1)
21 ; CHECK-NEXT: nop
22 ; CHECK-NEXT: fcmpu 0, 2, 27
25 ; CHECK-NEXT: cror 20, 4, 20
2326 ; CHECK-NEXT: lwz 3, 380(1)
2427 ; CHECK-NEXT: lwz 4, 376(1)
2528 ; CHECK-NEXT: lwz 5, 388(1)
2629 ; CHECK-NEXT: lwz 6, 384(1)
27 ; CHECK-NEXT: fcmpu 1, 1, 27
28 ; CHECK-NEXT: crand 20, 6, 0
29 ; CHECK-NEXT: cror 20, 4, 20
3030 ; CHECK-NEXT: stw 3, 396(1)
3131 ; CHECK-NEXT: stw 4, 392(1)
3232 ; CHECK-NEXT: stw 5, 404(1)
4343 ; CHECK-NEXT: lis 3, 15856
4444 ; CHECK-NEXT: stfd 1, 304(1)
4545 ; CHECK-NEXT: stfd 0, 296(1)
46 ; CHECK-NEXT: nop
47 ; CHECK-NEXT: nop
4846 ; CHECK-NEXT: lwz 4, 308(1)
4947 ; CHECK-NEXT: lwz 5, 304(1)
5048 ; CHECK-NEXT: lwz 6, 300(1)
5755 ; CHECK-NEXT: stw 5, 320(1)
5856 ; CHECK-NEXT: stw 6, 316(1)
5957 ; CHECK-NEXT: stw 7, 312(1)
60 ; CHECK-NEXT: nop
6158 ; CHECK-NEXT: lfd 31, 320(1)
6259 ; CHECK-NEXT: lfd 30, 312(1)
6360 ; CHECK-NEXT: lfd 3, 336(1)
6663 ; CHECK-NEXT: fmr 2, 30
6764 ; CHECK-NEXT: bl __gcc_qmul@PLT
6865 ; CHECK-NEXT: stfd 1, 280(1)
66 ; CHECK-NEXT: lis 3, .LCPI0_1@ha
6967 ; CHECK-NEXT: stfd 2, 288(1)
70 ; CHECK-NEXT: lis 3, .LCPI0_1@ha
71 ; CHECK-NEXT: fmr 29, 1
72 ; CHECK-NEXT: fmr 28, 2
73 ; CHECK-NEXT: fcmpu 0, 2, 27
68 ; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
69 ; CHECK-NEXT: lis 3, 16864
7470 ; CHECK-NEXT: lwz 4, 284(1)
7571 ; CHECK-NEXT: lwz 5, 280(1)
7672 ; CHECK-NEXT: lwz 6, 292(1)
7773 ; CHECK-NEXT: lwz 7, 288(1)
78 ; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
79 ; CHECK-NEXT: lis 3, 16864
74 ; CHECK-NEXT: fmr 29, 1
8075 ; CHECK-NEXT: stw 29, 372(1)
8176 ; CHECK-NEXT: stw 3, 368(1)
77 ; CHECK-NEXT: fmr 28, 2
8278 ; CHECK-NEXT: stw 29, 364(1)
8379 ; CHECK-NEXT: stw 29, 360(1)
80 ; CHECK-NEXT: fcmpu 0, 2, 27
8481 ; CHECK-NEXT: stw 4, 356(1)
8582 ; CHECK-NEXT: stw 5, 352(1)
83 ; CHECK-NEXT: fcmpu 1, 1, 0
8684 ; CHECK-NEXT: stw 6, 348(1)
8785 ; CHECK-NEXT: stw 7, 344(1)
88 ; CHECK-NEXT: fcmpu 1, 1, 0
86 ; CHECK-NEXT: crandc 20, 6, 0
8987 ; CHECK-NEXT: lfd 3, 368(1)
9088 ; CHECK-NEXT: lfd 4, 360(1)
9189 ; CHECK-NEXT: lfd 1, 352(1)
9290 ; CHECK-NEXT: lfd 2, 344(1)
93 ; CHECK-NEXT: crandc 20, 6, 0
9491 ; CHECK-NEXT: cror 8, 5, 20
9592 ; CHECK-NEXT: bl __gcc_qsub@PLT
9693 ; CHECK-NEXT: mffs 0
107104 ; CHECK-NEXT: fctiwz 1, 2
108105 ; CHECK-NEXT: stfd 0, 160(1)
109106 ; CHECK-NEXT: stfd 1, 152(1)
110 ; CHECK-NEXT: nop
111107 ; CHECK-NEXT: lwz 3, 164(1)
112108 ; CHECK-NEXT: lwz 4, 156(1)
113109 ; CHECK-NEXT: addis 3, 3, -32768
118114 ; CHECK-NEXT: .LBB0_4: # %bb1
119115 ; CHECK-NEXT: addi 30, 3, 0
120116 ; CHECK-NEXT: .LBB0_5: # %bb1
117 ; CHECK-NEXT: li 4, 0
121118 ; CHECK-NEXT: mr 3, 30
122 ; CHECK-NEXT: li 4, 0
123119 ; CHECK-NEXT: bl __floatditf@PLT
124120 ; CHECK-NEXT: stfd 1, 208(1)
121 ; CHECK-NEXT: lis 3, 17392
125122 ; CHECK-NEXT: stfd 2, 200(1)
126 ; CHECK-NEXT: lis 3, 17392
127123 ; CHECK-NEXT: fmr 28, 1
128 ; CHECK-NEXT: fmr 29, 2
129 ; CHECK-NEXT: cmpwi 2, 30, 0
130124 ; CHECK-NEXT: lwz 4, 212(1)
131125 ; CHECK-NEXT: lwz 5, 208(1)
132126 ; CHECK-NEXT: lwz 6, 204(1)
133127 ; CHECK-NEXT: lwz 7, 200(1)
128 ; CHECK-NEXT: fmr 29, 2
134129 ; CHECK-NEXT: stw 29, 244(1)
135130 ; CHECK-NEXT: stw 3, 240(1)
131 ; CHECK-NEXT: cmpwi 2, 30, 0
136132 ; CHECK-NEXT: stw 29, 236(1)
137133 ; CHECK-NEXT: stw 29, 232(1)
138134 ; CHECK-NEXT: stw 4, 228(1)
139135 ; CHECK-NEXT: stw 5, 224(1)
140136 ; CHECK-NEXT: stw 6, 220(1)
141137 ; CHECK-NEXT: stw 7, 216(1)
142 ; CHECK-NEXT: nop
143138 ; CHECK-NEXT: lfd 3, 240(1)
144139 ; CHECK-NEXT: lfd 4, 232(1)
145140 ; CHECK-NEXT: lfd 1, 224(1)
156151 ; CHECK-NEXT: .LBB0_9: # %bb1
157152 ; CHECK-NEXT: stfd 2, 192(1)
158153 ; CHECK-NEXT: fmr 1, 31
159 ; CHECK-NEXT: fmr 2, 30
160 ; CHECK-NEXT: nop
161 ; CHECK-NEXT: nop
162154 ; CHECK-NEXT: lwz 3, 188(1)
163155 ; CHECK-NEXT: lwz 4, 184(1)
164156 ; CHECK-NEXT: lwz 5, 196(1)
165157 ; CHECK-NEXT: lwz 6, 192(1)
158 ; CHECK-NEXT: fmr 2, 30
166159 ; CHECK-NEXT: stw 3, 260(1)
167160 ; CHECK-NEXT: stw 4, 256(1)
168161 ; CHECK-NEXT: stw 5, 252(1)
171164 ; CHECK-NEXT: lfd 4, 248(1)
172165 ; CHECK-NEXT: bl __gcc_qsub@PLT
173166 ; CHECK-NEXT: stfd 2, 176(1)
167 ; CHECK-NEXT: fcmpu 0, 2, 27
174168 ; CHECK-NEXT: stfd 1, 168(1)
175169 ; CHECK-NEXT: fcmpu 1, 1, 27
176 ; CHECK-NEXT: fcmpu 0, 2, 27
177170 ; CHECK-NEXT: lwz 3, 180(1)
178171 ; CHECK-NEXT: lwz 4, 176(1)
179172 ; CHECK-NEXT: lwz 5, 172(1)
180173 ; CHECK-NEXT: lwz 6, 168(1)
181174 ; CHECK-NEXT: crandc 20, 6, 0
182 ; CHECK-NEXT: cror 21, 5, 7
183 ; CHECK-NEXT: cror 20, 21, 20
184175 ; CHECK-NEXT: stw 3, 268(1)
185176 ; CHECK-NEXT: stw 4, 264(1)
177 ; CHECK-NEXT: cror 21, 5, 7
186178 ; CHECK-NEXT: stw 5, 276(1)
187179 ; CHECK-NEXT: stw 6, 272(1)
180 ; CHECK-NEXT: cror 20, 21, 20
188181 ; CHECK-NEXT: lfd 30, 264(1)
189182 ; CHECK-NEXT: lfd 31, 272(1)
190183 ; CHECK-NEXT: bc 12, 20, .LBB0_13
191184 ; CHECK-NEXT: # %bb.10: # %bb2
192185 ; CHECK-NEXT: fneg 29, 31
193186 ; CHECK-NEXT: fneg 28, 30
187 ; CHECK-NEXT: stfd 29, 48(1)
194188 ; CHECK-NEXT: li 29, 0
189 ; CHECK-NEXT: stfd 28, 40(1)
195190 ; CHECK-NEXT: lis 3, 16864
196 ; CHECK-NEXT: stfd 29, 48(1)
197 ; CHECK-NEXT: stfd 28, 40(1)
198 ; CHECK-NEXT: nop
199191 ; CHECK-NEXT: lwz 4, 52(1)
200192 ; CHECK-NEXT: lwz 5, 48(1)
201193 ; CHECK-NEXT: lwz 6, 44(1)
208200 ; CHECK-NEXT: stw 5, 64(1)
209201 ; CHECK-NEXT: stw 6, 60(1)
210202 ; CHECK-NEXT: stw 7, 56(1)
211 ; CHECK-NEXT: nop
212203 ; CHECK-NEXT: lfd 3, 80(1)
213204 ; CHECK-NEXT: lfd 4, 72(1)
214205 ; CHECK-NEXT: lfd 1, 64(1)
215206 ; CHECK-NEXT: lfd 2, 56(1)
216207 ; CHECK-NEXT: bl __gcc_qsub@PLT
217208 ; CHECK-NEXT: lis 3, .LCPI0_2@ha
209 ; CHECK-NEXT: lfs 0, .LCPI0_2@l(3)
218210 ; CHECK-NEXT: lis 4, .LCPI0_3@ha
219 ; CHECK-NEXT: lfs 0, .LCPI0_2@l(3)
220 ; CHECK-NEXT: mffs 11
221 ; CHECK-NEXT: mtfsb1 31
222211 ; CHECK-NEXT: lfs 3, .LCPI0_3@l(4)
223 ; CHECK-NEXT: mtfsb0 30
224212 ; CHECK-NEXT: fcmpu 0, 30, 0
213 ; CHECK-NEXT: mffs 0
214 ; CHECK-NEXT: mtfsb1 31
225215 ; CHECK-NEXT: fcmpu 1, 31, 3
216 ; CHECK-NEXT: crandc 20, 6, 1
217 ; CHECK-NEXT: mtfsb0 30
218 ; CHECK-NEXT: cror 20, 4, 20
226219 ; CHECK-NEXT: fadd 1, 2, 1
227 ; CHECK-NEXT: crandc 20, 6, 1
228 ; CHECK-NEXT: mtfsf 1, 11
229 ; CHECK-NEXT: cror 20, 4, 20
230 ; CHECK-NEXT: mffs 0
231 ; CHECK-NEXT: mtfsb1 31
232 ; CHECK-NEXT: mtfsb0 30
233 ; CHECK-NEXT: fadd 12, 28, 29
220 ; CHECK-NEXT: mtfsf 1, 0
221 ; CHECK-NEXT: mffs 0
222 ; CHECK-NEXT: mtfsb1 31
223 ; CHECK-NEXT: mtfsb0 30
224 ; CHECK-NEXT: fadd 2, 28, 29
234225 ; CHECK-NEXT: mtfsf 1, 0
235226 ; CHECK-NEXT: fctiwz 0, 1
236 ; CHECK-NEXT: fctiwz 13, 12
227 ; CHECK-NEXT: fctiwz 1, 2
237228 ; CHECK-NEXT: stfd 0, 32(1)
238 ; CHECK-NEXT: stfd 13, 24(1)
239 ; CHECK-NEXT: nop
229 ; CHECK-NEXT: stfd 1, 24(1)
240230 ; CHECK-NEXT: lwz 3, 36(1)
241231 ; CHECK-NEXT: lwz 4, 28(1)
242232 ; CHECK-NEXT: addis 3, 3, -32768
250240 ; CHECK-NEXT: b .LBB0_16
251241 ; CHECK-NEXT: .LBB0_13: # %bb3
252242 ; CHECK-NEXT: stfd 31, 112(1)
243 ; CHECK-NEXT: li 3, 0
253244 ; CHECK-NEXT: stfd 30, 104(1)
254 ; CHECK-NEXT: li 3, 0
255245 ; CHECK-NEXT: lis 4, 16864
256246 ; CHECK-NEXT: lwz 5, 116(1)
257247 ; CHECK-NEXT: lwz 6, 112(1)
265255 ; CHECK-NEXT: stw 6, 128(1)
266256 ; CHECK-NEXT: stw 7, 124(1)
267257 ; CHECK-NEXT: stw 8, 120(1)
268 ; CHECK-NEXT: nop
269258 ; CHECK-NEXT: lfd 3, 144(1)
270259 ; CHECK-NEXT: lfd 4, 136(1)
271260 ; CHECK-NEXT: lfd 1, 128(1)
272261 ; CHECK-NEXT: lfd 2, 120(1)
273262 ; CHECK-NEXT: bl __gcc_qsub@PLT
274263 ; CHECK-NEXT: lis 3, .LCPI0_0@ha
264 ; CHECK-NEXT: lfs 0, .LCPI0_0@l(3)
275265 ; CHECK-NEXT: lis 4, .LCPI0_1@ha
276 ; CHECK-NEXT: lfs 0, .LCPI0_0@l(3)
277 ; CHECK-NEXT: mffs 11
278 ; CHECK-NEXT: mtfsb1 31
279266 ; CHECK-NEXT: lfs 3, .LCPI0_1@l(4)
280 ; CHECK-NEXT: mtfsb0 30
281267 ; CHECK-NEXT: fcmpu 0, 30, 0
268 ; CHECK-NEXT: mffs 0
269 ; CHECK-NEXT: mtfsb1 31
282270 ; CHECK-NEXT: fcmpu 1, 31, 3
271 ; CHECK-NEXT: crandc 20, 6, 0
272 ; CHECK-NEXT: mtfsb0 30
273 ; CHECK-NEXT: cror 20, 5, 20
283274 ; CHECK-NEXT: fadd 1, 2, 1
284 ; CHECK-NEXT: crandc 20, 6, 0
285 ; CHECK-NEXT: mtfsf 1, 11
286 ; CHECK-NEXT: cror 20, 5, 20
287 ; CHECK-NEXT: mffs 0
288 ; CHECK-NEXT: mtfsb1 31
289 ; CHECK-NEXT: mtfsb0 30
290 ; CHECK-NEXT: fadd 12, 30, 31
275 ; CHECK-NEXT: mtfsf 1, 0
276 ; CHECK-NEXT: mffs 0
277 ; CHECK-NEXT: mtfsb1 31
278 ; CHECK-NEXT: mtfsb0 30
279 ; CHECK-NEXT: fadd 2, 30, 31
291280 ; CHECK-NEXT: mtfsf 1, 0
292281 ; CHECK-NEXT: fctiwz 0, 1
293 ; CHECK-NEXT: fctiwz 13, 12
282 ; CHECK-NEXT: fctiwz 1, 2
294283 ; CHECK-NEXT: stfd 0, 96(1)
295 ; CHECK-NEXT: stfd 13, 88(1)
296 ; CHECK-NEXT: nop
284 ; CHECK-NEXT: stfd 1, 88(1)
297285 ; CHECK-NEXT: lwz 3, 100(1)
298286 ; CHECK-NEXT: lwz 4, 92(1)
299287 ; CHECK-NEXT: addis 3, 3, -32768
307295 ; CHECK-NEXT: lwz 12, 408(1)
308296 ; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
309297 ; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
298 ; CHECK-NEXT: mtcrf 32, 12 # cr2
310299 ; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload
311300 ; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload
312301 ; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload
313302 ; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload
314303 ; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload
315304 ; CHECK-NEXT: lwz 0, 468(1)
316 ; CHECK-NEXT: mtcrf 32, 12 # cr2
317305 ; CHECK-NEXT: addi 1, 1, 464
318306 ; CHECK-NEXT: mtlr 0
319307 ; CHECK-NEXT: blr
77 ; EH_SjLj_Setup.
88
99 ; CHECK: li 3, 1
10 ; CHECK-NEXT: cmplwi 3, 0
10 ; CHECK: cmplwi 3, 0
1111
1212 define void @h() nounwind {
1313 %1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8
1919
2020 ; PPC32-FP: _f1:
2121 ; PPC32-FP: lis r0, -1
22 ; PPC32-FP: ori r0, r0, 32736
2223 ; PPC32-FP: stw r31, -4(r1)
23 ; PPC32-FP: ori r0, r0, 32736
2424 ; PPC32-FP: stwux r1, r1, r0
2525 ; PPC32-FP: mr r31, r1
2626 ; PPC32-FP: addi r3, r31, 32
4040
4141 ; PPC64-FP: _f1:
4242 ; PPC64-FP: lis r0, -1
43 ; PPC64-FP: ori r0, r0, 32704
4344 ; PPC64-FP: std r31, -8(r1)
44 ; PPC64-FP: ori r0, r0, 32704
4545 ; PPC64-FP: stdux r1, r1, r0
4646 ; PPC64-FP: mr r31, r1
4747 ; PPC64-FP: addi r3, r31, 60
2323
2424 ;; CHECK-LABEL: f:
2525 ;; CHECK: lwzu
26 ;; CHECK: stwu
2627 ;; CHECK-NEXT: lwz
2728 ;; CHECK-NEXT: lwz
2829 ;; CHECK-NEXT: lwz
29 ;; CHECK-NEXT: stwu
3030 ;; CHECK-NEXT: stw
3131 ;; CHECK-NEXT: stw
3232 ;; CHECK-NEXT: stw
1010 define signext i32 @main() {
1111 ; CHECK-LABEL: main:
1212 ; CHECK: li 3, -32477
13 ; CHECK: lis 12, 0
1413 ; CHECK: li 6, 234
1514 ; CHECK: sth 3, 46(1)
16 ; CHECK: ori 4, 12, 33059
15 ; CHECK: lis 3, 0
16 ; CHECK: ori 4, 3, 33059
1717 ; CHECK: sync
1818 ; CHECK: .LBB0_1: # %L.entry
1919 ; CHECK: lharx 3, 0, 5
3131 ; CHECK: cmplwi 3, 234
3232 ;
3333 ; CHECK-P7-LABEL: main:
34 ; CHECK-P7: li 3, -32477
3435 ; CHECK-P7: lis 4, 0
3536 ; CHECK-P7: li 7, 0
36 ; CHECK-P7: li 3, -32477
37 ; CHECK-P7: li 5, 234
3738 ; CHECK-P7: sth 3, 46(1)
38 ; CHECK-P7: li 5, 234
3939 ; CHECK-P7: ori 4, 4, 33059
4040 ; CHECK-P7: rlwinm 3, 6, 3, 27, 27
4141 ; CHECK-P7: ori 7, 7, 65535
4242 ; CHECK-P7: sync
4343 ; CHECK-P7: slw 8, 5, 3
44 ; CHECK-P7: slw 9, 4, 3
45 ; CHECK-P7: rldicr 4, 6, 0, 61
4446 ; CHECK-P7: slw 5, 7, 3
45 ; CHECK-P7: slw 9, 4, 3
4647 ; CHECK-P7: and 7, 8, 5
47 ; CHECK-P7: rldicr 4, 6, 0, 61
4848 ; CHECK-P7: and 8, 9, 5
4949 ; CHECK-P7: .LBB0_1: # %L.entry
5050 ; CHECK-P7: lwarx 9, 0, 4
2626 ; FIXME: We don't need to do these stores/loads at all.
2727 ; CHECK-DAG: std 3, -24(1)
2828 ; CHECK-DAG: stb 4, -16(1)
29 ; CHECK: ori 2, 2, 0
3029 ; CHECK-DAG: lbz [[REG1:[0-9]+]], -16(1)
3130 ; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)
3231 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG1]], 32
3434 ; PPC64LE-LABEL: test3:
3535 ; PPC64LE: # %bb.0:
3636 ; PPC64LE-NEXT: sync
37 ; PPC64LE-NEXT: ori 2, 2, 0
3837 ; PPC64LE-NEXT: lbz 3, 0(3)
3938 ; PPC64LE-NEXT: cmpd 7, 3, 3
4039 ; PPC64LE-NEXT: bne- 7, .+4
7877 ; PPC64LE-LABEL: test7:
7978 ; PPC64LE: # %bb.0:
8079 ; PPC64LE-NEXT: sync
81 ; PPC64LE-NEXT: ori 2, 2, 0
8280 ; PPC64LE-NEXT: lhz 3, 0(3)
8381 ; PPC64LE-NEXT: cmpd 7, 3, 3
8482 ; PPC64LE-NEXT: bne- 7, .+4
122120 ; PPC64LE-LABEL: test11:
123121 ; PPC64LE: # %bb.0:
124122 ; PPC64LE-NEXT: sync
125 ; PPC64LE-NEXT: ori 2, 2, 0
126123 ; PPC64LE-NEXT: lwz 3, 0(3)
127124 ; PPC64LE-NEXT: cmpd 7, 3, 3
128125 ; PPC64LE-NEXT: bne- 7, .+4
166163 ; PPC64LE-LABEL: test15:
167164 ; PPC64LE: # %bb.0:
168165 ; PPC64LE-NEXT: sync
169 ; PPC64LE-NEXT: ori 2, 2, 0
170166 ; PPC64LE-NEXT: ld 3, 0(3)
171167 ; PPC64LE-NEXT: cmpd 7, 3, 3
172168 ; PPC64LE-NEXT: bne- 7, .+4
2929 ; COLDCC: std 8, -24(1)
3030 ; COLDCC: std 9, -32(1)
3131 ; COLDCC: std 10, -40(1)
32 ; COLDCC: ld 10, -40(1)
3233 ; COLDCC: ld 9, -32(1)
3334 ; COLDCC: ld 8, -24(1)
3435 ; COLDCC: ld 7, -16(1)
35 ; COLDCC: ld 10, -40(1)
3636 ; COLDCC: ld 6, -8(1)
3737 %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
3838 %mul = mul nsw i32 %a, 3
28612861 %11 = LI8 280
28622862 %12 = LDX %0, killed %11 :: (load 8 from %ir.arrayidx3, !tbaa !10)
28632863 ; CHECK: LD 280, %0
2864 ; CHECK-LATE: ld 12, 280(3)
2864 ; CHECK-LATE: ld 3, 280(3)
28652865 %13 = ADD8 killed %12, killed %7
28662866 $x3 = COPY %13
28672867 BLR8 implicit $lr8, implicit $rm, implicit $x3
7878 ; CHECK: cmpwi r7, 0
7979 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
8080 ; CHECK: ori r3, r4, 0
81 ; CHECK-NEXT: ori r12, r6, 0
81 ; CHECK-NEXT: ori r4, r6, 0
8282 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
8383 ; CHECK-NEXT: [[TRUE]]
8484 ; CHECK-NEXT: addi r3, r7, 0
85 ; CHECK-NEXT: addi r12, r5, 0
85 ; CHECK-NEXT: addi r4, r5, 0
8686 ; CHECK-NEXT: [[SUCCESSOR]]
87 ; CHECK-NEXT: add r3, r3, r12
87 ; CHECK-NEXT: add r3, r3, r4
8888 ; CHECK-NEXT: extsw r3, r3
8989 ; CHECK-NEXT: blr
9090 }
103103 ; CHECK: cmpwi cr0, r7, 0
104104 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
105105 ; CHECK: ori r3, r4, 0
106 ; CHECK-NEXT: ori r12, r6, 0
106 ; CHECK-NEXT: ori r4, r6, 0
107107 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
108108 ; CHECK-NEXT: [[TRUE]]
109 ; CHECK-NEXT: addi r12, r5, 0
109 ; CHECK-NEXT: addi r4, r5, 0
110110 ; CHECK-NEXT: [[SUCCESSOR]]
111 ; CHECK-NEXT: add r3, r3, r12
111 ; CHECK-NEXT: add r3, r3, r4
112112 ; CHECK-NEXT: extsw r3, r3
113113 ; CHECK-NEXT: blr
114114 }
1313 ; CHECK-LABEL: bitcast_fabs:
1414 ; CHECK: ; %bb.0:
1515 ; CHECK-NEXT: stfs f1, -8(r1)
16 ; CHECK-NEXT: nop
17 ; CHECK-NEXT: nop
18 ; CHECK-NEXT: lwz r2, -8(r1)
16 ; CHECK: lwz r2, -8(r1)
1917 ; CHECK-NEXT: clrlwi r2, r2, 1
2018 ; CHECK-NEXT: stw r2, -4(r1)
2119 ; CHECK-NEXT: lfs f1, -4(r1)
153153 ; This is the minimum FMF needed for this transform - the FMA allows reassociation.
154154
155155 ; FMFDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
156 ; FMFDEBUG: fmul reassoc {{t[0-9]+}},
156 ; FMFDEBUG: fmul reassoc {{t[0-9]+}},
157157 ; FMFDEBUG: Type-legalized selection DAG: %bb.0 'fmul_fma_reassoc1:'
158158
159159 ; GLOBALDEBUG-LABEL: Optimized lowered selection DAG: %bb.0 'fmul_fma_reassoc1:'
286286
287287 define float @sqrt_afn(float %x) {
288288 ; FMF-LABEL: sqrt_afn:
289 ; FMF: # %bb.0:
290 ; FMF-NEXT: xxlxor 0, 0, 0
291 ; FMF-NEXT: fcmpu 0, 1, 0
292 ; FMF-NEXT: beq 0, .LBB10_2
293 ; FMF-NEXT: # %bb.1:
294 ; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha
295 ; FMF-NEXT: xsrsqrtesp 3, 1
296 ; FMF-NEXT: addi 3, 3, .LCPI10_0@toc@l
297 ; FMF-NEXT: lfsx 0, 0, 3
298 ; FMF-NEXT: xsmulsp 2, 1, 0
299 ; FMF-NEXT: xsmulsp 4, 3, 3
300 ; FMF-NEXT: xssubsp 2, 2, 1
301 ; FMF-NEXT: xsmulsp 2, 2, 4
302 ; FMF-NEXT: xssubsp 0, 0, 2
303 ; FMF-NEXT: xsmulsp 0, 3, 0
304 ; FMF-NEXT: xsmulsp 0, 0, 1
305 ; FMF-NEXT: .LBB10_2:
306 ; FMF-NEXT: fmr 1, 0
307 ; FMF-NEXT: blr
289 ; FMF: # %bb.0:
290 ; FMF-NEXT: xxlxor 0, 0, 0
291 ; FMF-NEXT: fcmpu 0, 1, 0
292 ; FMF-NEXT: beq 0, .LBB10_2
293 ; FMF-NEXT: # %bb.1:
294 ; FMF-NEXT: addis 3, 2, .LCPI10_0@toc@ha
295 ; FMF-NEXT: xsrsqrtesp 3, 1
296 ; FMF-NEXT: addi 3, 3, .LCPI10_0@toc@l
297 ; FMF-NEXT: lfsx 0, 0, 3
298 ; FMF-NEXT: xsmulsp 2, 1, 0
299 ; FMF-NEXT: xsmulsp 4, 3, 3
300 ; FMF-NEXT: xssubsp 2, 2, 1
301 ; FMF-NEXT: xsmulsp 2, 2, 4
302 ; FMF-NEXT: xssubsp 0, 0, 2
303 ; FMF-NEXT: xsmulsp 0, 3, 0
304 ; FMF-NEXT: xsmulsp 0, 0, 1
305 ; FMF-NEXT: .LBB10_2:
306 ; FMF-NEXT: fmr 1, 0
307 ; FMF-NEXT: blr
308308 ;
309309 ; GLOBAL-LABEL: sqrt_afn:
310310 ; GLOBAL: # %bb.0:
313313 ; GLOBAL-NEXT: beq 0, .LBB10_2
314314 ; GLOBAL-NEXT: # %bb.1:
315315 ; GLOBAL-NEXT: xsrsqrtesp 2, 1
316 ; GLOBAL-NEXT: fneg 0, 1
316317 ; GLOBAL-NEXT: addis 3, 2, .LCPI10_0@toc@ha
317 ; GLOBAL-NEXT: fneg 0, 1
318318 ; GLOBAL-NEXT: fmr 4, 1
319319 ; GLOBAL-NEXT: addi 3, 3, .LCPI10_0@toc@l
320320 ; GLOBAL-NEXT: lfsx 3, 0, 3
342342
343343 define float @sqrt_fast(float %x) {
344344 ; FMF-LABEL: sqrt_fast:
345 ; FMF: # %bb.0:
346 ; FMF-NEXT: xxlxor 0, 0, 0
347 ; FMF-NEXT: fcmpu 0, 1, 0
348 ; FMF-NEXT: beq 0, .LBB11_2
349 ; FMF-NEXT: # %bb.1:
350 ; FMF-NEXT: xsrsqrtesp 2, 1
351 ; FMF-NEXT: addis 3, 2, .LCPI11_0@toc@ha
352 ; FMF-NEXT: fneg 0, 1
353 ; FMF-NEXT: fmr 4, 1
354 ; FMF-NEXT: addi 3, 3, .LCPI11_0@toc@l
355 ; FMF-NEXT: lfsx 3, 0, 3
356 ; FMF-NEXT: xsmaddasp 4, 0, 3
357 ; FMF-NEXT: xsmulsp 0, 2, 2
358 ; FMF-NEXT: xsmaddasp 3, 4, 0
359 ; FMF-NEXT: xsmulsp 0, 2, 3
360 ; FMF-NEXT: xsmulsp 0, 0, 1
361 ; FMF-NEXT: .LBB11_2:
362 ; FMF-NEXT: fmr 1, 0
363 ; FMF-NEXT: blr
345 ; FMF: # %bb.0:
346 ; FMF-NEXT: xxlxor 0, 0, 0
347 ; FMF-NEXT: fcmpu 0, 1, 0
348 ; FMF-NEXT: beq 0, .LBB11_2
349 ; FMF-NEXT: # %bb.1:
350 ; FMF-NEXT: xsrsqrtesp 2, 1
351 ; FMF-NEXT: fneg 0, 1
352 ; FMF-NEXT: addis 3, 2, .LCPI11_0@toc@ha
353 ; FMF-NEXT: fmr 4, 1
354 ; FMF-NEXT: addi 3, 3, .LCPI11_0@toc@l
355 ; FMF-NEXT: lfsx 3, 0, 3
356 ; FMF-NEXT: xsmaddasp 4, 0, 3
357 ; FMF-NEXT: xsmulsp 0, 2, 2
358 ; FMF-NEXT: xsmaddasp 3, 4, 0
359 ; FMF-NEXT: xsmulsp 0, 2, 3
360 ; FMF-NEXT: xsmulsp 0, 0, 1
361 ; FMF-NEXT: .LBB11_2:
362 ; FMF-NEXT: fmr 1, 0
363 ; FMF-NEXT: blr
364364 ;
365365 ; GLOBAL-LABEL: sqrt_fast:
366366 ; GLOBAL: # %bb.0:
369369 ; GLOBAL-NEXT: beq 0, .LBB11_2
370370 ; GLOBAL-NEXT: # %bb.1:
371371 ; GLOBAL-NEXT: xsrsqrtesp 2, 1
372 ; GLOBAL-NEXT: fneg 0, 1
372373 ; GLOBAL-NEXT: addis 3, 2, .LCPI11_0@toc@ha
373 ; GLOBAL-NEXT: fneg 0, 1
374374 ; GLOBAL-NEXT: fmr 4, 1
375375 ; GLOBAL-NEXT: addi 3, 3, .LCPI11_0@toc@l
376376 ; GLOBAL-NEXT: lfsx 3, 0, 3
2727
2828 ; PPC32-DAG: stfd 1, 24(1)
2929 ; PPC32-DAG: stfd 2, 16(1)
30 ; PPC32: nop
3130 ; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
3231 ; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
3332 ; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
6968
7069 ; PPC32-DAG: stfd 1, 24(1)
7170 ; PPC32-DAG: stfd 2, 16(1)
72 ; PPC32: nop
7371 ; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
7472 ; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
7573 ; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
8987 ; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
9088 ; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
9189 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
90 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
91 ; PPC64-NOT: BARRIER
9292 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
93 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
9493 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
95 ; PPC64-NOT: BARRIER
9694 ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
9795 ; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
9896 ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
102100 ; PPC64-P8-LABEL: test_copysign:
103101 ; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
104102 ; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
103 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
104 ; PPC64-P8-NOT: BARRIER
105105 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
106 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
107106 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
108 ; PPC64-P8-NOT: BARRIER
109107 ; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
110108 ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
111109 ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
112110 ; PPC64-P8: blr
113111
114112 ; PPC32: stfd 1, [[STACK:[0-9]+]](1)
115 ; PPC32: nop
116113 ; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
117114 ; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
118115 ; PPC32-NOT: BARRIER
88 ; CHECK-LABEL: neg_ext_op1_extra_use:
99 ; CHECK: # %bb.0:
1010 ; CHECK-NEXT: xsadddp 0, 2, 1
11 ; CHECK-NEXT: fneg 13, 1
12 ; CHECK-NEXT: xsdivdp 1, 13, 0
11 ; CHECK-NEXT: fneg 1, 1
12 ; CHECK-NEXT: xsdivdp 1, 1, 0
1313 ; CHECK-NEXT: blr
1414 %t1 = fsub float -0.0, %x
1515 %t2 = fpext float %t1 to double
1818 ; CHECK: isel 3, [[REG2]], [[REG1]],
1919 ; CHECK: blr
2020
21 ; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
21 ; CHECK-NO-ISEL: bclr 12, 0, 0
2222 ; CHECK-NO-ISEL: ori 3, 5, 0
23 ; CHECK-NO-ISEL-NEXT: blr
24 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
25 ; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
2623 ; CHECK-NO-ISEL-NEXT: blr
2724 }
2825
4340 ; CHECK: isel 3, [[REG2]], [[REG1]],
4441 ; CHECK: blr
4542
46 ; CHECK-NO-ISEL: bc 12, 0, [[TRUE:.LBB[0-9]+]]
43 ; CHECK-NO-ISEL: bclr 12, 0, 0
4744 ; CHECK-NO-ISEL: ori 3, 5, 0
48 ; CHECK-NO-ISEL-NEXT: blr
49 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
50 ; CHECK-NO-ISEL-NEXT: addi 3, 12, 0
5145 ; CHECK-NO-ISEL-NEXT: blr
5246 }
5347
55
66 ; CHECK-LABEL: @test
77
8 ; CHECK: addis 4, 4, .LCPI
9 ; CHECK-NEXT: addis 5, 5, .LCPI
810 ; CHECK: andi. {{[0-9]+}}, 3, 1
9 ; CHECK-NEXT: addis 4, 4, .LCPI
10 ; CHECK-NEXT: addis 5, 5, .LCPI
1111 ; CHECK-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
1212 ; CHECK: ori 3, 4, 0
1313 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
2020 ; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
2121 ; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
2222 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
23 ; CHECK-NO-ISEL: ori [[REG3:[0-9]+]], 3, 0
24 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
23 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
2524 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
26 ; CHECK-NO-ISEL-NEXT: addi [[REG3]], [[REG2]], 0
25 ; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0
2726 ; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
28 ; CHECK-NO-ISEL: std [[REG3]], -{{[0-9]+}}(1)
27 ; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1)
2928 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
3029
3130
1919 define linkonce_odr void @ZN6snappyDecompressor_(%"class.snappy::SnappyDecompressor"* %this, %"class.snappy::SnappyIOVecWriter"* %writer) {
2020 ; CHECK-LABEL: ZN6snappyDecompressor_:
2121 ; CHECK: # %bb.0: # %entry
22 ; CHECK: addis 23, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
23 ; CHECK-DAG: addi 25, 23, _ZN6snappy8internalL8wordmaskE@toc@l
22 ; CHECK: addis 3, 2, _ZN6snappy8internalL8wordmaskE@toc@ha
23 ; CHECK-DAG: addi 25, 3, _ZN6snappy8internalL8wordmaskE@toc@l
2424 ; CHECK-DAG: addis 5, 2, _ZN6snappy8internalL10char_tableE@toc@ha
2525 ; CHECK-DAG: addi 24, 5, _ZN6snappy8internalL10char_tableE@toc@l
2626 ; CHECK: b .LBB0_2
6767 define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
6868 ; CHECK-LABEL: reassociate_adds5:
6969 ; CHECK: # %bb.0:
70 ; CHECK: fadds [[REG12:[0-9]+]], 5, 6
71 ; CHECK: fadds [[REG0:[0-9]+]], 1, 2
72 ; CHECK: fadds [[REG11:[0-9]+]], 3, 4
70 ; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 6
71 ; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 2
72 ; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 4
7373 ; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7
74 ; CHECK: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
75 ; CHECK: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
74 ; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
75 ; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
7676 ; CHECK: fadds 1, [[REG2]], 8
7777 ; CHECK-NEXT: blr
7878
106106 ; CHECK-NEXT: beq 0, .LBB3_3
107107 ; CHECK-NEXT: .LBB3_2: # %res_block
108108 ; CHECK-NEXT: cmpld 3, 4
109 ; CHECK-NEXT: li 11, 1
110 ; CHECK-NEXT: li 12, -1
111 ; CHECK-NEXT: isel 5, 12, 11, 0
109 ; CHECK-NEXT: li 3, 1
110 ; CHECK-NEXT: li 4, -1
111 ; CHECK-NEXT: isel 5, 4, 3, 0
112112 ; CHECK-NEXT: .LBB3_3: # %endblock
113113 ; CHECK-NEXT: extsw 3, 5
114114 ; CHECK-NEXT: neg 3, 3
142142 ; CHECK-NEXT: beq 0, .LBB4_3
143143 ; CHECK-NEXT: .LBB4_2: # %res_block
144144 ; CHECK-NEXT: cmpld 3, 4
145 ; CHECK-NEXT: li 11, 1
146 ; CHECK-NEXT: li 12, -1
147 ; CHECK-NEXT: isel 5, 12, 11, 0
145 ; CHECK-NEXT: li 3, 1
146 ; CHECK-NEXT: li 4, -1
147 ; CHECK-NEXT: isel 5, 4, 3, 0
148148 ; CHECK-NEXT: .LBB4_3: # %endblock
149149 ; CHECK-NEXT: srwi 3, 5, 31
150150 ; CHECK-NEXT: xori 3, 3, 1
171171 define signext i32 @equalityFoldOneConstant(i8* %X) {
172172 ; CHECK-LABEL: equalityFoldOneConstant:
173173 ; CHECK: # %bb.0:
174 ; CHECK-NEXT: ld 4, 0(3)
174175 ; CHECK-NEXT: li 5, 1
175 ; CHECK-NEXT: ld 4, 0(3)
176176 ; CHECK-NEXT: sldi 5, 5, 32
177177 ; CHECK-NEXT: cmpld 4, 5
178178 ; CHECK-NEXT: bne 0, .LBB6_2
2727 ; CHECK-NO-ISEL-LABEL: @foo
2828 ; CHECK: isel
2929 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
30 ; CHECK-NO-ISEL: ori 7, 12, 0
31 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
30 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
3231 ; CHECK-NO-ISEL: [[TRUE]]
33 ; CHECK-NO-ISEL-NEXT: addi 7, 11, 0
32 ; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, {{[0-9]+}}, 0
3433 ; CHECK: addi
3534 ; CHECK: isel
3635 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
3736 ; CHECK-NO-ISEL: ori 10, 11, 0
3837 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
3938 ; CHECK-NO-ISEL: [[TRUE]]
40 ; CHECK-NO-ISEL-NEXT: addi 10, 12, 0
4139 ; CHECK: blr
4240
4341 attributes #0 = { nounwind }
238238 ; Make sure the optimization fails to fire if the symbol is aligned, but the offset is not.
239239 ; CHECK-LABEL: test_misalign
240240 ; CHECK: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v@toc@ha
241 ; CHECK: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l
242 ; CHECK: li [[OFFSET_REG:[0-9]+]], 1
241 ; CHECK-DAG: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l
242 ; CHECK-DAG: li [[OFFSET_REG:[0-9]+]], 1
243243 ; CHECK: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]]
244244 ; CHECK: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
245245 ; CHECK: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]]
104104 ret ppc_fp128 %0
105105 }
106106 ; CHECK: convert_to:
107 ; CHECK: std 3, [[OFF1:.*]](1)
108 ; CHECK: std 4, [[OFF2:.*]](1)
109 ; CHECK: ori 2, 2, 0
107 ; CHECK-DAG: std 3, [[OFF1:.*]](1)
108 ; CHECK-DAG: std 4, [[OFF2:.*]](1)
110109 ; CHECK: lfd 1, [[OFF1]](1)
111110 ; CHECK: lfd 2, [[OFF2]](1)
112111 ; CHECK: blr
121120 ; CHECK: convert_to2:
122121 ; CHECK: std 3, [[OFF1:.*]](1)
123122 ; CHECK: std 5, [[OFF2:.*]](1)
124 ; CHECK: ori 2, 2, 0
125123 ; CHECK: lfd 1, [[OFF1]](1)
126124 ; CHECK: lfd 2, [[OFF2]](1)
127125 ; CHECK: blr
99 ret <4 x float> %6
1010
1111 ; CHECK: xxsldwi
12 ; CHECK-NEXT: vmrghw
13 ; CHECK-NEXT: vmrglw
12 ; CHECK-DAG: vmrghw
13 ; CHECK-DAG: vmrglw
1414 ; CHECK-NEXT: xxsldwi
1515 ; CHECK-NEXT: xxsldwi
1616 ; CHECK-NEXT: xxsldwi
88 ; CHECK-NEXT: lis 5, 21845
99 ; CHECK-NEXT: slwi 6, 3, 1
1010 ; CHECK-NEXT: srwi 3, 3, 1
11 ; CHECK-NEXT: lis 7, -13108
12 ; CHECK-NEXT: lis 8, 13107
1311 ; CHECK-NEXT: ori 4, 4, 43690
1412 ; CHECK-NEXT: ori 5, 5, 21845
15 ; CHECK-NEXT: lis 10, -3856
16 ; CHECK-NEXT: lis 11, 3855
13 ; CHECK-NEXT: and 4, 6, 4
1714 ; CHECK-NEXT: and 3, 3, 5
15 ; CHECK-NEXT: lis 5, 13107
16 ; CHECK-NEXT: or 3, 3, 4
17 ; CHECK-NEXT: lis 4, -13108
18 ; CHECK-NEXT: ori 5, 5, 13107
19 ; CHECK-NEXT: slwi 6, 3, 2
20 ; CHECK-NEXT: ori 4, 4, 52428
21 ; CHECK-NEXT: srwi 3, 3, 2
1822 ; CHECK-NEXT: and 4, 6, 4
19 ; CHECK-NEXT: ori 5, 8, 13107
23 ; CHECK-NEXT: and 3, 3, 5
24 ; CHECK-NEXT: lis 5, 3855
2025 ; CHECK-NEXT: or 3, 3, 4
21 ; CHECK-NEXT: ori 4, 7, 52428
22 ; CHECK-NEXT: slwi 9, 3, 2
23 ; CHECK-NEXT: srwi 3, 3, 2
24 ; CHECK-NEXT: and 3, 3, 5
25 ; CHECK-NEXT: and 4, 9, 4
26 ; CHECK-NEXT: ori 5, 11, 3855
27 ; CHECK-NEXT: or 3, 3, 4
28 ; CHECK-NEXT: ori 4, 10, 61680
29 ; CHECK-NEXT: slwi 12, 3, 4
26 ; CHECK-NEXT: lis 4, -3856
27 ; CHECK-NEXT: ori 5, 5, 3855
28 ; CHECK-NEXT: slwi 6, 3, 4
29 ; CHECK-NEXT: ori 4, 4, 61680
3030 ; CHECK-NEXT: srwi 3, 3, 4
31 ; CHECK-NEXT: and 4, 12, 4
31 ; CHECK-NEXT: and 4, 6, 4
3232 ; CHECK-NEXT: and 3, 3, 5
3333 ; CHECK-NEXT: or 3, 3, 4
3434 ; CHECK-NEXT: rotlwi 4, 3, 24
8484 ; CHECK-NEXT: oris 5, 5, 21845
8585 ; CHECK-NEXT: ori 4, 4, 43690
8686 ; CHECK-NEXT: ori 5, 5, 21845
87 ; CHECK-NEXT: and 4, 8, 4
8788 ; CHECK-NEXT: and 3, 3, 5
8889 ; CHECK-NEXT: sldi 5, 6, 32
8990 ; CHECK-NEXT: sldi 6, 7, 32
90 ; CHECK-NEXT: and 4, 8, 4
9191 ; CHECK-NEXT: lis 7, 3855
9292 ; CHECK-NEXT: or 3, 3, 4
93 ; CHECK-NEXT: oris 9, 5, 52428
94 ; CHECK-NEXT: oris 10, 6, 13107
93 ; CHECK-NEXT: oris 4, 5, 52428
94 ; CHECK-NEXT: oris 5, 6, 13107
9595 ; CHECK-NEXT: lis 6, -3856
9696 ; CHECK-NEXT: ori 7, 7, 3855
9797 ; CHECK-NEXT: sldi 8, 3, 2
98 ; CHECK-NEXT: ori 4, 9, 52428
98 ; CHECK-NEXT: ori 4, 4, 52428
9999 ; CHECK-NEXT: rldicl 3, 3, 62, 2
100 ; CHECK-NEXT: ori 5, 10, 13107
100 ; CHECK-NEXT: ori 5, 5, 13107
101101 ; CHECK-NEXT: ori 6, 6, 61680
102 ; CHECK-NEXT: and 4, 8, 4
102103 ; CHECK-NEXT: and 3, 3, 5
103104 ; CHECK-NEXT: sldi 5, 6, 32
104 ; CHECK-NEXT: and 4, 8, 4
105105 ; CHECK-NEXT: sldi 6, 7, 32
106106 ; CHECK-NEXT: or 3, 3, 4
107 ; CHECK-NEXT: oris 11, 5, 61680
108 ; CHECK-NEXT: oris 12, 6, 3855
107 ; CHECK-NEXT: oris 4, 5, 61680
108 ; CHECK-NEXT: oris 5, 6, 3855
109109 ; CHECK-NEXT: sldi 6, 3, 4
110 ; CHECK-NEXT: ori 4, 11, 61680
110 ; CHECK-NEXT: ori 4, 4, 61680
111111 ; CHECK-NEXT: rldicl 3, 3, 60, 4
112 ; CHECK-NEXT: ori 5, 12, 3855
112 ; CHECK-NEXT: ori 5, 5, 3855
113113 ; CHECK-NEXT: and 4, 6, 4
114114 ; CHECK-NEXT: and 3, 3, 5
115115 ; CHECK-NEXT: or 3, 3, 4
116 ; CHECK-NEXT: rldicl 4, 3, 32, 32
116117 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
117 ; CHECK-NEXT: rldicl 4, 3, 32, 32
118118 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
119119 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
120 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
120121 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
121 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
122122 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
123123 ; CHECK-NEXT: sldi 3, 5, 32
124124 ; CHECK-NEXT: or 3, 3, 6
1717
1818 ; CHECK: lfs [[REG1:[0-9]+]], 0(4)
1919 ; CHECK: stfs [[REG1]], 0(3)
20 ; CHECK: ori 2, 2, 0
2120 ; CHECK: lfs [[REG2:[0-9]+]], 0(5)
2221 ; CHECK: stfs [[REG2]], 0(4)
23 ; CHECK: ori 2, 2, 0
2422 ; CHECK: lfs [[REG3:[0-9]+]], 0(3)
2523 ; CHECK: stfs [[REG3]], 0(6)
2624 ; CHECK: blr
1313
1414 ; CHECK-LABEL: @foo
1515 ; CHECK: qvfrsqrte
16 ; CHECK: qvfmul
16 ; CHECK-DAG: qvfmul
1717 ; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
1818 ; an qvfmadd instead of a qvfnmsub
19 ; CHECK: qvfmadd
20 ; CHECK: qvfmadd
19 ; CHECK-DAG: qvfmadd
20 ; CHECK-DAG: qvfmadd
2121 ; CHECK: qvfmul
2222 ; CHECK: qvfmul
2323 ; CHECK: qvfmadd
4040
4141 ; CHECK-LABEL: @foof
4242 ; CHECK: qvfrsqrtes
43 ; CHECK: qvfmuls
43 ; CHECK-DAG: qvfmuls
4444 ; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
4545 ; an qvfmadd instead of a qvfnmsubs
46 ; CHECK: qvfmadds
47 ; CHECK: qvfmadds
46 ; CHECK-DAG: qvfmadds
47 ; CHECK-DAG: qvfmadds
4848 ; CHECK: qvfmuls
4949 ; CHECK: qvfmul
5050 ; CHECK: blr
6464
6565 ; CHECK-LABEL: @food
6666 ; CHECK: qvfrsqrte
67 ; CHECK: qvfmul
67 ; CHECK-DAG: qvfmul
6868 ; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
6969 ; an qvfmadd instead of a qvfnmsub
70 ; CHECK: qvfmadd
71 ; CHECK: qvfmadd
70 ; CHECK-DAG: qvfmadd
71 ; CHECK-DAG: qvfmadd
7272 ; CHECK: qvfmul
7373 ; CHECK: qvfmul
7474 ; CHECK: qvfmadd
9191
9292 ; CHECK-LABEL: @goo
9393 ; CHECK: qvfrsqrtes
94 ; CHECK: qvfmuls
94 ; CHECK-DAG: qvfmuls
9595 ; FIXME: We're currently loading two constants here (1.5 and -1.5), and using
9696 ; an qvfmadd instead of a qvfnmsubs
97 ; CHECK: qvfmadds
98 ; CHECK: qvfmadds
97 ; CHECK-DAG: qvfmadds
98 ; CHECK-DAG: qvfmadds
9999 ; CHECK: qvfmuls
100100 ; CHECK: qvfmuls
101101 ; CHECK: blr
55 ; CHECK: stwu 1, -32(1)
66 ; CHECK: stw 31, 28(1)
77 ; CHECK: mr 31, 1
8 ; CHECK: stw 30, 24(1)
9 ; CHECK: mfcr [[CR:[0-9]+]]
8 ; CHECK-DAG: stw 30, 24(1)
9 ; CHECK-DAG: mfcr [[CR:[0-9]+]]
1010 ; CHECK: stw [[CR]], 20(31)
1111
1212 target datalayout = "E-m:e-p:32:32-i64:64-n32"
2020 ; CHECK-LABEL: testMultipleAccess:
2121 ; CHECK: # %bb.0: # %entry
2222 ; CHECK-NEXT: lwz 4, 8(3)
23 ; CHECK-NEXT: lwz 12, 12(3)
24 ; CHECK-NEXT: add 3, 12, 4
23 ; CHECK-NEXT: lwz 3, 12(3)
24 ; CHECK-NEXT: add 3, 3, 4
2525 ; CHECK-NEXT: mtvsrwa 0, 3
2626 ; CHECK-NEXT: xscvsxdsp 1, 0
2727 ; CHECK-NEXT: blr
694694 define i8 @sel_constants_shl_constant(i1 %cond) {
695695 ; ISEL-LABEL: sel_constants_shl_constant:
696696 ; ISEL: # %bb.0:
697 ; ISEL-NEXT: lis 4, 2047
697698 ; ISEL-NEXT: lis 5, 511
698 ; ISEL-NEXT: lis 4, 2047
699699 ; ISEL-NEXT: andi. 3, 3, 1
700700 ; ISEL-NEXT: ori 3, 4, 65535
701 ; ISEL-NEXT: ori 12, 5, 65535
701 ; ISEL-NEXT: ori 4, 5, 65535
702702 ; ISEL-NEXT: sldi 3, 3, 5
703 ; ISEL-NEXT: sldi 4, 12, 7
703 ; ISEL-NEXT: sldi 4, 4, 7
704704 ; ISEL-NEXT: isel 3, 4, 3, 1
705705 ; ISEL-NEXT: blr
706706 ;
707707 ; NO_ISEL-LABEL: sel_constants_shl_constant:
708708 ; NO_ISEL: # %bb.0:
709 ; NO_ISEL-NEXT: lis 4, 2047
709710 ; NO_ISEL-NEXT: lis 5, 511
710 ; NO_ISEL-NEXT: lis 4, 2047
711711 ; NO_ISEL-NEXT: andi. 3, 3, 1
712712 ; NO_ISEL-NEXT: ori 3, 4, 65535
713 ; NO_ISEL-NEXT: ori 12, 5, 65535
713 ; NO_ISEL-NEXT: ori 4, 5, 65535
714714 ; NO_ISEL-NEXT: sldi 3, 3, 5
715 ; NO_ISEL-NEXT: sldi 4, 12, 7
715 ; NO_ISEL-NEXT: sldi 4, 4, 7
716716 ; NO_ISEL-NEXT: bc 12, 1, .LBB36_1
717717 ; NO_ISEL-NEXT: blr
718718 ; NO_ISEL-NEXT: .LBB36_1:
8585 ; CHECK-NEXT: li 5, -1
8686 ; CHECK-NEXT: and 3, 3, 4
8787 ; CHECK-NEXT: xor 3, 3, 5
88 ; CHECK-NEXT: cntlzw 3, 3
88 ; CHECK-NEXT: cntlzw 3, 3
8989 ; CHECK-NEXT: srwi 3, 3, 5
9090 ; CHECK-NEXT: xori 3, 3, 1
9191 ; CHECK-NEXT: blr
468468 ; CHECK-LABEL: and_eq_vec:
469469 ; CHECK: # %bb.0:
470470 ; CHECK-NEXT: vcmpequw 2, 2, 3
471 ; CHECK-NEXT: vcmpequw 19, 4, 5
472 ; CHECK-NEXT: xxland 34, 34, 51
471 ; CHECK-NEXT: vcmpequw 3, 4, 5
472 ; CHECK-NEXT: xxland 34, 34, 35
473473 ; CHECK-NEXT: blr
474474 %cmp1 = icmp eq <4 x i32> %a, %b
475475 %cmp2 = icmp eq <4 x i32> %c, %d
2525 ; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
2626 ; CHECK-DAG: cmpwi [[R1]], 1
2727 ; CHECK-DAG: srad 4, 4, 5
28 ; CHECK: isel 3, [[R5]], [[R4]], 0
28 ; CHECK-DAG: isel 3, [[R5]], [[R4]], 0
2929 ; CHECK: blr
3030 define i128 @ashr(i128 %x, i128 %y) {
3131 %r = ashr i128 %x, %y
4343
4444 ; CHECK-LABEL: @bar
4545 ; CHECK: li 4, 2
46 ; CHECK: stw 4, 12(3)
47 ; CHECK: sth 4, 10(3)
48 ; CHECK: std 4, 0(3)
49 ; CHECK: stb 4, 8(3)
46 ; CHECK-DAG: stw 4, 12(3)
47 ; CHECK-DAG: sth 4, 10(3)
48 ; CHECK-DAG: std 4, 0(3)
49 ; CHECK-DAG: stb 4, 8(3)
5050 }
5151
5252 ; Function Attrs: norecurse nounwind
1111 ; CHECK: xxspltd
1212 ; CHECK-NEXT: xxspltd
1313 ; CHECK-NEXT: xvmuldp
14 ; CHECK-NEXT: xvmuldp
15 ; CHECK-NEXT: xvsubdp
16 ; CHECK-NEXT: xvadddp
17 ; CHECK-NEXT: xxswapd
18 ; CHECK-NEXT: xxpermdi
19 ; CHECK-NEXT: xvsubdp
20 ; CHECK-NEXT: xxswapd
14 ; CHECK-DAG: xvmuldp
15 ; CHECK-DAG: xvsubdp
16 ; CHECK-DAG: xvadddp
17 ; CHECK-DAG: xxswapd
18 ; CHECK-DAG: xxpermdi
19 ; CHECK-DAG: xvsubdp
20 ; CHECK: xxswapd
2121 ; CHECK-NEXT: stxvd2x
22 ; CHECK-NEXT: blr
22 ; CHECK: blr
2323
2424 ; Function Attrs: noinline
2525 define void @zg(i8* %.G0011_640.0, i8* %.G0012_642.0, <2 x double>* %JJ, <2 x double>* %.ka0000_391, double %.unpack, double %.unpack66) #0 {
88 ; CHECK-NEXT: lis 5, 21845
99 ; CHECK-NEXT: slwi 6, 3, 1
1010 ; CHECK-NEXT: srwi 3, 3, 1
11 ; CHECK-NEXT: lis 7, -13108
12 ; CHECK-NEXT: lis 8, 13107
1311 ; CHECK-NEXT: ori 4, 4, 43690
1412 ; CHECK-NEXT: ori 5, 5, 21845
15 ; CHECK-NEXT: lis 10, -3856
16 ; CHECK-NEXT: lis 11, 3855
13 ; CHECK-NEXT: and 4, 6, 4
1714 ; CHECK-NEXT: and 3, 3, 5
15 ; CHECK-NEXT: lis 5, 13107
16 ; CHECK-NEXT: or 3, 3, 4
17 ; CHECK-NEXT: lis 4, -13108
18 ; CHECK-NEXT: ori 5, 5, 13107
19 ; CHECK-NEXT: slwi 6, 3, 2
20 ; CHECK-NEXT: ori 4, 4, 52428
21 ; CHECK-NEXT: srwi 3, 3, 2
1822 ; CHECK-NEXT: and 4, 6, 4
19 ; CHECK-NEXT: ori 5, 8, 13107
23 ; CHECK-NEXT: and 3, 3, 5
24 ; CHECK-NEXT: lis 5, 3855
2025 ; CHECK-NEXT: or 3, 3, 4
21 ; CHECK-NEXT: ori 4, 7, 52428
22 ; CHECK-NEXT: slwi 9, 3, 2
23 ; CHECK-NEXT: srwi 3, 3, 2
24 ; CHECK-NEXT: and 3, 3, 5
25 ; CHECK-NEXT: and 4, 9, 4
26 ; CHECK-NEXT: ori 5, 11, 3855
27 ; CHECK-NEXT: or 3, 3, 4
28 ; CHECK-NEXT: ori 4, 10, 61680
29 ; CHECK-NEXT: slwi 12, 3, 4
26 ; CHECK-NEXT: lis 4, -3856
27 ; CHECK-NEXT: ori 5, 5, 3855
28 ; CHECK-NEXT: slwi 6, 3, 4
29 ; CHECK-NEXT: ori 4, 4, 61680
3030 ; CHECK-NEXT: srwi 3, 3, 4
31 ; CHECK-NEXT: and 4, 12, 4
31 ; CHECK-NEXT: and 4, 6, 4
3232 ; CHECK-NEXT: and 3, 3, 5
3333 ; CHECK-NEXT: or 3, 3, 4
3434 ; CHECK-NEXT: rotlwi 4, 3, 24
6060 ; CHECK-NEXT: oris 5, 5, 21845
6161 ; CHECK-NEXT: ori 4, 4, 43690
6262 ; CHECK-NEXT: ori 5, 5, 21845
63 ; CHECK-NEXT: and 4, 8, 4
6364 ; CHECK-NEXT: and 3, 3, 5
6465 ; CHECK-NEXT: sldi 5, 6, 32
6566 ; CHECK-NEXT: sldi 6, 7, 32
66 ; CHECK-NEXT: and 4, 8, 4
6767 ; CHECK-NEXT: lis 7, 3855
6868 ; CHECK-NEXT: or 3, 3, 4
69 ; CHECK-NEXT: oris 9, 5, 52428
70 ; CHECK-NEXT: oris 10, 6, 13107
69 ; CHECK-NEXT: oris 4, 5, 52428
70 ; CHECK-NEXT: oris 5, 6, 13107
7171 ; CHECK-NEXT: lis 6, -3856
7272 ; CHECK-NEXT: ori 7, 7, 3855
7373 ; CHECK-NEXT: sldi 8, 3, 2
74 ; CHECK-NEXT: ori 4, 9, 52428
74 ; CHECK-NEXT: ori 4, 4, 52428
7575 ; CHECK-NEXT: rldicl 3, 3, 62, 2
76 ; CHECK-NEXT: ori 5, 10, 13107
76 ; CHECK-NEXT: ori 5, 5, 13107
7777 ; CHECK-NEXT: ori 6, 6, 61680
78 ; CHECK-NEXT: and 4, 8, 4
7879 ; CHECK-NEXT: and 3, 3, 5
7980 ; CHECK-NEXT: sldi 5, 6, 32
80 ; CHECK-NEXT: and 4, 8, 4
8181 ; CHECK-NEXT: sldi 6, 7, 32
8282 ; CHECK-NEXT: or 3, 3, 4
83 ; CHECK-NEXT: oris 11, 5, 61680
84 ; CHECK-NEXT: oris 12, 6, 3855
83 ; CHECK-NEXT: oris 4, 5, 61680
84 ; CHECK-NEXT: oris 5, 6, 3855
8585 ; CHECK-NEXT: sldi 6, 3, 4
86 ; CHECK-NEXT: ori 4, 11, 61680
86 ; CHECK-NEXT: ori 4, 4, 61680
8787 ; CHECK-NEXT: rldicl 3, 3, 60, 4
88 ; CHECK-NEXT: ori 5, 12, 3855
88 ; CHECK-NEXT: ori 5, 5, 3855
8989 ; CHECK-NEXT: and 4, 6, 4
9090 ; CHECK-NEXT: and 3, 3, 5
9191 ; CHECK-NEXT: or 3, 3, 4
92 ; CHECK-NEXT: rldicl 4, 3, 32, 32
9293 ; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
93 ; CHECK-NEXT: rldicl 4, 3, 32, 32
9494 ; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
9595 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
96 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
9697 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
97 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
9898 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
9999 ; CHECK-NEXT: sldi 3, 5, 32
100100 ; CHECK-NEXT: or 3, 3, 6
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
76 ; CHECK-NEXT: stb r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i8 %a, %b
8686 define void @test_ieqsc_sext_store(i8 signext %a, i8 signext %b) {
8787 ; CHECK-LABEL: test_ieqsc_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stw r3, 0(r12)
76 ; CHECK-NEXT: stw r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i32 %a, %b
8686 define void @test_ieqsi_sext_store(i32 signext %a, i32 signext %b) {
8787 ; CHECK-LABEL: test_ieqsi_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
6868 ; CHECK: # %bb.0: # %entry
6969 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7070 ; CHECK-NEXT: xor r3, r3, r4
71 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
71 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7272 ; CHECK-NEXT: cntlzd r3, r3
7373 ; CHECK-NEXT: rldicl r3, r3, 58, 63
74 ; CHECK-NEXT: std r3, 0(r12)
74 ; CHECK-NEXT: std r3, 0(r4)
7575 ; CHECK-NEXT: blr
7676 entry:
7777 %cmp = icmp eq i64 %a, %b
8686 ; CHECK: # %bb.0: # %entry
8787 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8888 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
89 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9090 ; CHECK-NEXT: addic r3, r3, -1
9191 ; CHECK-NEXT: subfe r3, r3, r3
92 ; CHECK-NEXT: std r3, 0(r12)
92 ; CHECK-NEXT: std r3, 0(r4)
9393 ; CHECK-NEXT: blr
9494 entry:
9595 %cmp = icmp eq i64 %a, %b
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: sth r3, 0(r12)
76 ; CHECK-NEXT: sth r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i16 %a, %b
8686 define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
8787 ; CHECK-LABEL: test_ieqss_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
76 ; CHECK-NEXT: stb r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i8 %a, %b
8686 define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
8787 ; CHECK-LABEL: test_iequc_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stw r3, 0(r12)
76 ; CHECK-NEXT: stw r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i32 %a, %b
8686 define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
8787 ; CHECK-LABEL: test_iequi_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
6868 ; CHECK: # %bb.0: # %entry
6969 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7070 ; CHECK-NEXT: xor r3, r3, r4
71 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
71 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7272 ; CHECK-NEXT: cntlzd r3, r3
7373 ; CHECK-NEXT: rldicl r3, r3, 58, 63
74 ; CHECK-NEXT: std r3, 0(r12)
74 ; CHECK-NEXT: std r3, 0(r4)
7575 ; CHECK-NEXT: blr
7676 entry:
7777 %cmp = icmp eq i64 %a, %b
8686 ; CHECK: # %bb.0: # %entry
8787 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8888 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
89 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9090 ; CHECK-NEXT: addic r3, r3, -1
9191 ; CHECK-NEXT: subfe r3, r3, r3
92 ; CHECK-NEXT: std r3, 0(r12)
92 ; CHECK-NEXT: std r3, 0(r4)
9393 ; CHECK-NEXT: blr
9494 entry:
9595 %cmp = icmp eq i64 %a, %b
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: sth r3, 0(r12)
76 ; CHECK-NEXT: sth r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i16 %a, %b
8686 define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
8787 ; CHECK-LABEL: test_iequs_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
43 ; CHECK-NEXT: stb r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i8 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
60 ; CHECK-NEXT: stb r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i8 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i32 0, align 4
88
99 define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
43 ; CHECK-NEXT: stw r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i32 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
60 ; CHECK-NEXT: stw r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i32 %a, %b
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
43 ; CHECK-NEXT: sth r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i16 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
60 ; CHECK-NEXT: sth r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i16 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i8 0, align 1
88
99 define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
43 ; CHECK-NEXT: stb r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sle i8 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
60 ; CHECK-NEXT: stb r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sle i8 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i32 0, align 4
88
99 define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
43 ; CHECK-NEXT: stw r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sle i32 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
60 ; CHECK-NEXT: stw r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sle i32 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i64 0, align 8
88
99 define signext i32 @test_ilesll(i64 %a, i64 %b) {
1111 ; CHECK: # %bb.0: # %entry
1212 ; CHECK-NEXT: sradi r5, r4, 63
1313 ; CHECK-NEXT: rldicl r6, r3, 1, 63
14 ; CHECK-NEXT: subfc r12, r3, r4
14 ; CHECK-NEXT: subfc r3, r3, r4
1515 ; CHECK-NEXT: adde r3, r5, r6
1616 ; CHECK-NEXT: blr
1717 entry:
2525 ; CHECK: # %bb.0: # %entry
2626 ; CHECK-NEXT: sradi r5, r4, 63
2727 ; CHECK-NEXT: rldicl r6, r3, 1, 63
28 ; CHECK-NEXT: subfc r12, r3, r4
28 ; CHECK-NEXT: subfc r3, r3, r4
2929 ; CHECK-NEXT: adde r3, r5, r6
3030 ; CHECK-NEXT: neg r3, r3
3131 ; CHECK-NEXT: blr
6464 define void @test_ilesll_store(i64 %a, i64 %b) {
6565 ; CHECK-LABEL: test_ilesll_store:
6666 ; CHECK: # %bb.0: # %entry
67 ; CHECK: sradi r6, r4, 63
68 ; CHECK: subfc r4, r3, r4
69 ; CHECK: rldicl r3, r3, 1, 63
70 ; CHECK: adde r3, r6, r3
71 ; CHECK: std r3,
67 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
68 ; CHECK-NEXT: sradi r6, r4, 63
69 ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
70 ; CHECK-NEXT: subfc r4, r3, r4
71 ; CHECK-NEXT: rldicl r3, r3, 1, 63
72 ; CHECK-NEXT: adde r3, r6, r3
73 ; CHECK-NEXT: std r3, 0(r5)
7274 ; CHECK-NEXT: blr
7375 entry:
7476 %cmp = icmp sle i64 %a, %b
8082 define void @test_ilesll_sext_store(i64 %a, i64 %b) {
8183 ; CHECK-LABEL: test_ilesll_sext_store:
8284 ; CHECK: # %bb.0: # %entry
83 ; CHECK: sradi r6, r4, 63
84 ; CHECK-DAG: rldicl r3, r3, 1, 63
85 ; CHECK-DAG: subfc r4, r3, r4
86 ; CHECK: adde r3, r6, r3
87 ; CHECK: neg r3, r3
88 ; CHECK: std r3,
85 ; CHECK-NEXT: sradi r6, r4, 63
86 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
87 ; CHECK-NEXT: subfc r4, r3, r4
88 ; CHECK-NEXT: rldicl r3, r3, 1, 63
89 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
90 ; CHECK-NEXT: adde r3, r6, r3
91 ; CHECK-NEXT: neg r3, r3
92 ; CHECK-NEXT: std r3, 0(r4)
8993 ; CHECK-NEXT: blr
9094 entry:
9195 %cmp = icmp sle i64 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i16 0, align 2
88
99 define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r4, r3
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
43 ; CHECK-NEXT: sth r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sle i16 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r4, r3
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
60 ; CHECK-NEXT: sth r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sle i16 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i64 0, align 8
99
6262 ; CHECK: # %bb.0: # %entry
6363 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6464 ; CHECK-NEXT: xor r3, r3, r4
65 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
65 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
6666 ; CHECK-NEXT: addic r5, r3, -1
6767 ; CHECK-NEXT: subfe r3, r5, r3
68 ; CHECK-NEXT: std r3, 0(r12)
68 ; CHECK-NEXT: std r3, 0(r4)
6969 ; CHECK-NEXT: blr
7070 entry:
7171 %cmp = icmp ne i64 %a, %b
7979 ; CHECK: # %bb.0: # %entry
8080 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8181 ; CHECK-NEXT: xor r3, r3, r4
82 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
82 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8383 ; CHECK-NEXT: subfic r3, r3, 0
8484 ; CHECK-NEXT: subfe r3, r3, r3
85 ; CHECK-NEXT: std r3, 0(r12)
85 ; CHECK-NEXT: std r3, 0(r4)
8686 ; CHECK-NEXT: blr
8787 entry:
8888 %cmp = icmp ne i64 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i8 0, align 1
88
99 define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
6565 define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
6666 ; CHECK-LABEL: test_ineuc_store:
6767 ; CHECK: # %bb.0: # %entry
68 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6869 ; CHECK-NEXT: xor r3, r3, r4
69 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7070 ; CHECK-NEXT: cntlzw r3, r3
7171 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7272 ; CHECK-NEXT: srwi r3, r3, 5
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i64 0, align 8
99
6262 ; CHECK: # %bb.0: # %entry
6363 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6464 ; CHECK-NEXT: xor r3, r3, r4
65 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
65 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
6666 ; CHECK-NEXT: addic r5, r3, -1
6767 ; CHECK-NEXT: subfe r3, r5, r3
68 ; CHECK-NEXT: std r3, 0(r12)
68 ; CHECK-NEXT: std r3, 0(r4)
6969 ; CHECK-NEXT: blr
7070 entry:
7171 %cmp = icmp ne i64 %a, %b
7979 ; CHECK: # %bb.0: # %entry
8080 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8181 ; CHECK-NEXT: xor r3, r3, r4
82 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
82 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8383 ; CHECK-NEXT: subfic r3, r3, 0
8484 ; CHECK-NEXT: subfe r3, r3, r3
85 ; CHECK-NEXT: std r3, 0(r12)
85 ; CHECK-NEXT: std r3, 0(r4)
8686 ; CHECK-NEXT: blr
8787 entry:
8888 %cmp = icmp ne i64 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i16 0, align 2
99
6666 define void @test_ineus_store(i16 zeroext %a, i16 zeroext %b) {
6767 ; CHECK-LABEL: test_ineus_store:
6868 ; CHECK: # %bb.0: # %entry
69 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6970 ; CHECK-NEXT: xor r3, r3, r4
70 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: cntlzw r3, r3
7272 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: srwi r3, r3, 5
7070 ; CHECK: # %bb.0: # %entry
7171 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7272 ; CHECK-NEXT: xor r3, r3, r4
73 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
73 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7474 ; CHECK-NEXT: cntlzw r3, r3
7575 ; CHECK-NEXT: srwi r3, r3, 5
76 ; CHECK-NEXT: stb r3, 0(r12)
76 ; CHECK-NEXT: stb r3, 0(r4)
7777 ; CHECK-NEXT: blr
7878 entry:
7979 %cmp = icmp eq i8 %a, %b
8686 define void @test_lleqsc_sext_store(i8 signext %a, i8 signext %b) {
8787 ; CHECK-LABEL: test_lleqsc_sext_store:
8888 ; CHECK: # %bb.0: # %entry
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8990 ; CHECK-NEXT: xor r3, r3, r4
90 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9191 ; CHECK-NEXT: cntlzw r3, r3
9292 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9393 ; CHECK-NEXT: srwi r3, r3, 5
6969 ; CHECK: # %bb.0: # %entry
7070 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: cntlzw r3, r3
7474 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stw r3, 0(r12)
75 ; CHECK-NEXT: stw r3, 0(r4)
7676 ; CHECK-NEXT: blr
7777 entry:
7878 %cmp = icmp eq i32 %a, %b
8585 define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
8686 ; CHECK-LABEL: test_lleqsi_sext_store:
8787 ; CHECK: # %bb.0: # %entry
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8889 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9090 ; CHECK-NEXT: cntlzw r3, r3
9191 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9292 ; CHECK-NEXT: srwi r3, r3, 5
6767 ; CHECK: # %bb.0: # %entry
6868 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6969 ; CHECK-NEXT: xor r3, r3, r4
70 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
70 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7171 ; CHECK-NEXT: cntlzd r3, r3
7272 ; CHECK-NEXT: rldicl r3, r3, 58, 63
73 ; CHECK-NEXT: std r3, 0(r12)
73 ; CHECK-NEXT: std r3, 0(r4)
7474 ; CHECK-NEXT: blr
7575 entry:
7676 %cmp = icmp eq i64 %a, %b
8585 ; CHECK: # %bb.0: # %entry
8686 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8787 ; CHECK-NEXT: xor r3, r3, r4
88 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
88 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8989 ; CHECK-NEXT: addic r3, r3, -1
9090 ; CHECK-NEXT: subfe r3, r3, r3
91 ; CHECK-NEXT: std r3, 0(r12)
91 ; CHECK-NEXT: std r3, 0(r4)
9292 ; CHECK-NEXT: blr
9393 entry:
9494 %cmp = icmp eq i64 %a, %b
6969 ; CHECK: # %bb.0: # %entry
7070 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: cntlzw r3, r3
7474 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: sth r3, 0(r12)
75 ; CHECK-NEXT: sth r3, 0(r4)
7676 ; CHECK-NEXT: blr
7777 entry:
7878 %cmp = icmp eq i16 %a, %b
8585 define void @test_lleqss_sext_store(i16 signext %a, i16 signext %b) {
8686 ; CHECK-LABEL: test_lleqss_sext_store:
8787 ; CHECK: # %bb.0: # %entry
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8889 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9090 ; CHECK-NEXT: cntlzw r3, r3
9191 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9292 ; CHECK-NEXT: srwi r3, r3, 5
6969 ; CHECK: # %bb.0: # %entry
7070 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: cntlzw r3, r3
7474 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stb r3, 0(r12)
75 ; CHECK-NEXT: stb r3, 0(r4)
7676 ; CHECK-NEXT: blr
7777 entry:
7878 %cmp = icmp eq i8 %a, %b
8585 define void @test_llequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
8686 ; CHECK-LABEL: test_llequc_sext_store:
8787 ; CHECK: # %bb.0: # %entry
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8889 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9090 ; CHECK-NEXT: cntlzw r3, r3
9191 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9292 ; CHECK-NEXT: srwi r3, r3, 5
6969 ; CHECK: # %bb.0: # %entry
7070 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: cntlzw r3, r3
7474 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: stw r3, 0(r12)
75 ; CHECK-NEXT: stw r3, 0(r4)
7676 ; CHECK-NEXT: blr
7777 entry:
7878 %cmp = icmp eq i32 %a, %b
8585 define void @test_llequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
8686 ; CHECK-LABEL: test_llequi_sext_store:
8787 ; CHECK: # %bb.0: # %entry
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8889 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9090 ; CHECK-NEXT: cntlzw r3, r3
9191 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9292 ; CHECK-NEXT: srwi r3, r3, 5
6767 ; CHECK: # %bb.0: # %entry
6868 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6969 ; CHECK-NEXT: xor r3, r3, r4
70 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
70 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7171 ; CHECK-NEXT: cntlzd r3, r3
7272 ; CHECK-NEXT: rldicl r3, r3, 58, 63
73 ; CHECK-NEXT: std r3, 0(r12)
73 ; CHECK-NEXT: std r3, 0(r4)
7474 ; CHECK-NEXT: blr
7575 entry:
7676 %cmp = icmp eq i64 %a, %b
8585 ; CHECK: # %bb.0: # %entry
8686 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8787 ; CHECK-NEXT: xor r3, r3, r4
88 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
88 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8989 ; CHECK-NEXT: addic r3, r3, -1
9090 ; CHECK-NEXT: subfe r3, r3, r3
91 ; CHECK-NEXT: std r3, 0(r12)
91 ; CHECK-NEXT: std r3, 0(r4)
9292 ; CHECK-NEXT: blr
9393 entry:
9494 %cmp = icmp eq i64 %a, %b
6969 ; CHECK: # %bb.0: # %entry
7070 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
7171 ; CHECK-NEXT: xor r3, r3, r4
72 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
72 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
7373 ; CHECK-NEXT: cntlzw r3, r3
7474 ; CHECK-NEXT: srwi r3, r3, 5
75 ; CHECK-NEXT: sth r3, 0(r12)
75 ; CHECK-NEXT: sth r3, 0(r4)
7676 ; CHECK-NEXT: blr
7777 entry:
7878 %cmp = icmp eq i16 %a, %b
8585 define void @test_llequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
8686 ; CHECK-LABEL: test_llequs_sext_store:
8787 ; CHECK: # %bb.0: # %entry
88 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8889 ; CHECK-NEXT: xor r3, r3, r4
89 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
9090 ; CHECK-NEXT: cntlzw r3, r3
9191 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
9292 ; CHECK-NEXT: srwi r3, r3, 5
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i8 0, align 1
88
99 define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stb r3, 0(r12)
43 ; CHECK-NEXT: stb r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i8 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stb r3, 0(r12)
60 ; CHECK-NEXT: stb r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i8 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i32 0, align 4
88
99 define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: stw r3, 0(r12)
43 ; CHECK-NEXT: stw r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i32 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: stw r3, 0(r12)
60 ; CHECK-NEXT: stw r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i32 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i16 0, align 2
88
99 define i64 @test_llgess(i16 signext %a, i16 signext %b) {
3737 ; CHECK: # %bb.0: # %entry
3838 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
3939 ; CHECK-NEXT: sub r3, r3, r4
40 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
40 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4141 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4242 ; CHECK-NEXT: xori r3, r3, 1
43 ; CHECK-NEXT: sth r3, 0(r12)
43 ; CHECK-NEXT: sth r3, 0(r4)
4444 ; CHECK-NEXT: blr
4545 entry:
4646 %cmp = icmp sge i16 %a, %b
5454 ; CHECK: # %bb.0: # %entry
5555 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5656 ; CHECK-NEXT: sub r3, r3, r4
57 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
57 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5858 ; CHECK-NEXT: rldicl r3, r3, 1, 63
5959 ; CHECK-NEXT: addi r3, r3, -1
60 ; CHECK-NEXT: sth r3, 0(r12)
60 ; CHECK-NEXT: sth r3, 0(r4)
6161 ; CHECK-NEXT: blr
6262 entry:
6363 %cmp = icmp sge i16 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i8 0, align 1
99
3838 ; CHECK: # %bb.0: # %entry
3939 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
4040 ; CHECK-NEXT: sub r3, r4, r3
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4242 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4343 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: stb r3, 0(r12)
44 ; CHECK-NEXT: stb r3, 0(r4)
4545 ; CHECK-NEXT: blr
4646 entry:
4747 %cmp = icmp sle i8 %a, %b
5555 ; CHECK: # %bb.0: # %entry
5656 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5757 ; CHECK-NEXT: sub r3, r4, r3
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5959 ; CHECK-NEXT: rldicl r3, r3, 1, 63
6060 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: stb r3, 0(r12)
61 ; CHECK-NEXT: stb r3, 0(r4)
6262 ; CHECK-NEXT: blr
6363 entry:
6464 %cmp = icmp sle i8 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i32 0, align 4
99
3838 ; CHECK: # %bb.0: # %entry
3939 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
4040 ; CHECK-NEXT: sub r3, r4, r3
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4242 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4343 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: stw r3, 0(r12)
44 ; CHECK-NEXT: stw r3, 0(r4)
4545 ; CHECK-NEXT: blr
4646 entry:
4747 %cmp = icmp sle i32 %a, %b
5555 ; CHECK: # %bb.0: # %entry
5656 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5757 ; CHECK-NEXT: sub r3, r4, r3
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5959 ; CHECK-NEXT: rldicl r3, r3, 1, 63
6060 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: stw r3, 0(r12)
61 ; CHECK-NEXT: stw r3, 0(r4)
6262 ; CHECK-NEXT: blr
6363 entry:
6464 %cmp = icmp sle i32 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77 @glob = common local_unnamed_addr global i64 0, align 8
88
99 ; Function Attrs: norecurse nounwind readnone
1212 ; CHECK: # %bb.0: # %entry
1313 ; CHECK-NEXT: sradi r5, r4, 63
1414 ; CHECK-NEXT: rldicl r6, r3, 1, 63
15 ; CHECK-NEXT: subfc r12, r3, r4
15 ; CHECK-NEXT: subfc r3, r3, r4
1616 ; CHECK-NEXT: adde r3, r5, r6
1717 ; CHECK-NEXT: blr
1818 entry:
2727 ; CHECK: # %bb.0: # %entry
2828 ; CHECK-NEXT: sradi r5, r4, 63
2929 ; CHECK-NEXT: rldicl r6, r3, 1, 63
30 ; CHECK-NEXT: subfc r12, r3, r4
30 ; CHECK-NEXT: subfc r3, r3, r4
3131 ; CHECK-NEXT: adde r3, r5, r6
3232 ; CHECK-NEXT: neg r3, r3
3333 ; CHECK-NEXT: blr
6969 define void @test_lllesll_store(i64 %a, i64 %b) {
7070 ; CHECK-LABEL: test_lllesll_store:
7171 ; CHECK: # %bb.0: # %entry
72 ; CHECK: sradi r6, r4, 63
73 ; CHECK: subfc r4, r3, r4
74 ; CHECK: rldicl r3, r3, 1, 63
75 ; CHECK: adde r3, r6, r3
76 ; CHECK: std r3,
72 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
73 ; CHECK-NEXT: sradi r6, r4, 63
74 ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
75 ; CHECK-NEXT: subfc r4, r3, r4
76 ; CHECK-NEXT: rldicl r3, r3, 1, 63
77 ; CHECK-NEXT: adde r3, r6, r3
78 ; CHECK-NEXT: std r3, 0(r5)
7779 ; CHECK-NEXT: blr
7880 entry:
7981 %cmp = icmp sle i64 %a, %b
8688 define void @test_lllesll_sext_store(i64 %a, i64 %b) {
8789 ; CHECK-LABEL: test_lllesll_sext_store:
8890 ; CHECK: # %bb.0: # %entry
89 ; CHECK: sradi r6, r4, 63
90 ; CHECK-DAG: rldicl r3, r3, 1, 63
91 ; CHECK-DAG: subfc r4, r3, r4
92 ; CHECK: adde r3, r6, r3
93 ; CHECK: neg r3, r3
94 ; CHECK: std r3, 0(r4)
91 ; CHECK-NEXT: sradi r6, r4, 63
92 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
93 ; CHECK-NEXT: subfc r4, r3, r4
94 ; CHECK-NEXT: rldicl r3, r3, 1, 63
95 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
96 ; CHECK-NEXT: adde r3, r6, r3
97 ; CHECK-NEXT: neg r3, r3
98 ; CHECK-NEXT: std r3, 0(r4)
9599 ; CHECK-NEXT: blr
96100 entry:
97101 %cmp = icmp sle i64 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i16 0, align 2
99
3838 ; CHECK: # %bb.0: # %entry
3939 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
4040 ; CHECK-NEXT: sub r3, r4, r3
41 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
41 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
4242 ; CHECK-NEXT: rldicl r3, r3, 1, 63
4343 ; CHECK-NEXT: xori r3, r3, 1
44 ; CHECK-NEXT: sth r3, 0(r12)
44 ; CHECK-NEXT: sth r3, 0(r4)
4545 ; CHECK-NEXT: blr
4646 entry:
4747 %cmp = icmp sle i16 %a, %b
5555 ; CHECK: # %bb.0: # %entry
5656 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
5757 ; CHECK-NEXT: sub r3, r4, r3
58 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
58 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
5959 ; CHECK-NEXT: rldicl r3, r3, 1, 63
6060 ; CHECK-NEXT: addi r3, r3, -1
61 ; CHECK-NEXT: sth r3, 0(r12)
61 ; CHECK-NEXT: sth r3, 0(r4)
6262 ; CHECK-NEXT: blr
6363 entry:
6464 %cmp = icmp sle i16 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i64 0, align 8
99
6262 ; CHECK: # %bb.0: # %entry
6363 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6464 ; CHECK-NEXT: xor r3, r3, r4
65 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
65 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
6666 ; CHECK-NEXT: addic r5, r3, -1
6767 ; CHECK-NEXT: subfe r3, r5, r3
68 ; CHECK-NEXT: std r3, 0(r12)
68 ; CHECK-NEXT: std r3, 0(r4)
6969 ; CHECK-NEXT: blr
7070 entry:
7171 %cmp = icmp ne i64 %a, %b
7979 ; CHECK: # %bb.0: # %entry
8080 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8181 ; CHECK-NEXT: xor r3, r3, r4
82 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
82 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8383 ; CHECK-NEXT: subfic r3, r3, 0
8484 ; CHECK-NEXT: subfe r3, r3, r3
85 ; CHECK-NEXT: std r3, 0(r12)
85 ; CHECK-NEXT: std r3, 0(r4)
8686 ; CHECK-NEXT: blr
8787 entry:
8888 %cmp = icmp ne i64 %a, %b
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
12 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
23 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
34 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
45 ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
56 ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
77
88 @glob = common local_unnamed_addr global i64 0, align 8
99
6262 ; CHECK: # %bb.0: # %entry
6363 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
6464 ; CHECK-NEXT: xor r3, r3, r4
65 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
65 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
6666 ; CHECK-NEXT: addic r5, r3, -1
6767 ; CHECK-NEXT: subfe r3, r5, r3
68 ; CHECK-NEXT: std r3, 0(r12)
68 ; CHECK-NEXT: std r3, 0(r4)
6969 ; CHECK-NEXT: blr
7070 entry:
7171 %cmp = icmp ne i64 %a, %b
7979 ; CHECK: # %bb.0: # %entry
8080 ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
8181 ; CHECK-NEXT: xor r3, r3, r4
82 ; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
82 ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
8383 ; CHECK-NEXT: subfic r3, r3, 0
8484 ; CHECK-NEXT: subfe r3, r3, r3
85 ; CHECK-NEXT: std r3, 0(r12)
85 ; CHECK-NEXT: std r3, 0(r4)
8686 ; CHECK-NEXT: blr
8787 entry:
8888 %cmp = icmp ne i64 %a, %b
2727 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
2828 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
2929 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
30 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
31 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
30 ; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
31 ; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
3232 ; CHECK: blr
3333 }
3434
5858 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
5959 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
6060 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
61 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
62 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
61 ; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
62 ; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
6363 ; CHECK: blr
6464 }
6565
8989 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
9090 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
9191 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
92 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
93 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
92 ; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
93 ; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
9494 ; CHECK: blr
9595 }
9696
142142 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
143143 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
144144 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
145 ; CHECK-DAG: vperm 3, [[REG5]], [[REG4]], [[REG3]]
146 ; CHECK-DAG: vperm 2, [[REG6]], [[REG5]], [[REG3]]
145 ; CHECK-DAG: vperm 3, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
146 ; CHECK-DAG: vperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
147147 ; CHECK: blr
148148 }
149149
327327 ; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 3, [[REG2]]
328328 ; CHECK-DAG: qvlpclsx [[REG5:[0-5]+]], 0, 3
329329 ; CHECK-DAG: qvlfsx [[REG6:[0-9]+]], 0, 3
330 ; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
331 ; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
330 ; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
331 ; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
332332 ; CHECK: blr
333333 }
334334
358358 ; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 3, [[REG2]]
359359 ; CHECK-DAG: qvlpcldx [[REG5:[0-5]+]], 0, 3
360360 ; CHECK-DAG: qvlfdx [[REG6:[0-9]+]], 0, 3
361 ; CHECK-DAG: qvfperm 2, [[REG4]], [[REG3]], [[REG5]]
362 ; CHECK-DAG: qvfperm 1, [[REG6]], [[REG4]], [[REG5]]
361 ; CHECK-DAG: qvfperm 2, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
362 ; CHECK-DAG: qvfperm 1, {{[0-9]+}}, {{[0-9]+}}, [[REG5]]
363363 ; CHECK: blr
364364 }
365365
1515 ; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
1616 ; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
1717 ; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l
18 ; CHECK-NEXT: lvx 18, 0, 3
19 ; CHECK-NEXT: lvx 19, 0, 4
2018 ; CHECK-NEXT: vsubuwm 3, 4, 3
19 ; CHECK-NEXT: lvx 4, 0, 4
2120 ; CHECK-NEXT: vslw 2, 2, 3
2221 ; CHECK-NEXT: vsraw 2, 2, 3
23 ; CHECK-NEXT: xxsel 34, 51, 50, 34
22 ; CHECK-NEXT: lvx 3, 0, 3
23 ; CHECK-NEXT: xxsel 34, 36, 35, 34
2424 ; CHECK-NEXT: blr
2525 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
2626 ret <4 x i32> %add
3434 ; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha
3535 ; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
3636 ; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l
37 ; CHECK-NEXT: lvx 19, 0, 3
37 ; CHECK-NEXT: lvx 3, 0, 3
3838 ; CHECK-NEXT: lvx 4, 0, 4
39 ; CHECK-NEXT: xxsel 34, 36, 51, 34
39 ; CHECK-NEXT: xxsel 34, 36, 35, 34
4040 ; CHECK-NEXT: blr
4141 %cond = icmp eq <4 x i32> %x, %y
4242 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
4949 ; CHECK-NEXT: vspltisw 3, 1
5050 ; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
5151 ; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
52 ; CHECK-NEXT: lvx 19, 0, 3
5352 ; CHECK-NEXT: xxland 34, 34, 35
54 ; CHECK-NEXT: vadduwm 2, 2, 19
53 ; CHECK-NEXT: lvx 3, 0, 3
54 ; CHECK-NEXT: vadduwm 2, 2, 3
5555 ; CHECK-NEXT: blr
5656 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
5757 ret <4 x i32> %add
6363 ; CHECK-NEXT: vcmpequw 2, 2, 3
6464 ; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha
6565 ; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l
66 ; CHECK-NEXT: lvx 19, 0, 3
67 ; CHECK-NEXT: vsubuwm 2, 19, 2
66 ; CHECK-NEXT: lvx 3, 0, 3
67 ; CHECK-NEXT: vsubuwm 2, 3, 2
6868 ; CHECK-NEXT: blr
6969 %cond = icmp eq <4 x i32> %x, %y
7070 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
7878 ; CHECK-NEXT: vspltisw 4, 15
7979 ; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
8080 ; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
81 ; CHECK-NEXT: lvx 19, 0, 3
8281 ; CHECK-NEXT: vsubuwm 3, 4, 3
8382 ; CHECK-NEXT: vslw 2, 2, 3
8483 ; CHECK-NEXT: vsraw 2, 2, 3
85 ; CHECK-NEXT: vadduwm 2, 2, 19
84 ; CHECK-NEXT: lvx 3, 0, 3
85 ; CHECK-NEXT: vadduwm 2, 2, 3
8686 ; CHECK-NEXT: blr
8787 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
8888 ret <4 x i32> %add
9494 ; CHECK-NEXT: vcmpequw 2, 2, 3
9595 ; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
9696 ; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
97 ; CHECK-NEXT: lvx 19, 0, 3
98 ; CHECK-NEXT: vadduwm 2, 2, 19
97 ; CHECK-NEXT: lvx 3, 0, 3
98 ; CHECK-NEXT: vadduwm 2, 2, 3
9999 ; CHECK-NEXT: blr
100100 %cond = icmp eq <4 x i32> %x, %y
101101 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
162162 ; CHECK-LABEL: cmp_sel_1_or_0_vec:
163163 ; CHECK: # %bb.0:
164164 ; CHECK-NEXT: vcmpequw 2, 2, 3
165 ; CHECK-NEXT: vspltisw 19, 1
166 ; CHECK-NEXT: xxland 34, 34, 51
165 ; CHECK-NEXT: vspltisw 3, 1
166 ; CHECK-NEXT: xxland 34, 34, 35
167167 ; CHECK-NEXT: blr
168168 %cond = icmp eq <4 x i32> %x, %y
169169 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
184184 ; CHECK-LABEL: cmp_sel_0_or_1_vec:
185185 ; CHECK: # %bb.0:
186186 ; CHECK-NEXT: vcmpequw 2, 2, 3
187 ; CHECK-NEXT: vspltisw 19, 1
187 ; CHECK-NEXT: vspltisw 3, 1
188188 ; CHECK-NEXT: xxlnor 0, 34, 34
189 ; CHECK-NEXT: xxland 34, 0, 51
189 ; CHECK-NEXT: xxland 34, 0, 35
190190 ; CHECK-NEXT: blr
191191 %cond = icmp eq <4 x i32> %x, %y
192192 %add = select <4 x i1> %cond, <4 x i32> , <4 x i32>
11361136 ret <2 x i32> %i
11371137
11381138 ; CHECK-REG-LABEL: @test80
1139 ; CHECK-REG: stw 3, -16(1)
1140 ; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
1139 ; CHECK-REG-DAG: stw 3, -16(1)
1140 ; CHECK-REG-DAG: addi [[R1:[0-9]+]], 1, -16
11411141 ; CHECK-REG: addis [[R2:[0-9]+]]
1142 ; CHECK-REG: addi [[R2]], [[R2]]
1142 ; CHECK-REG-DAG: addi [[R2]], [[R2]]
11431143 ; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
11441144 ; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
11451145 ; CHECK-REG: xxspltw 34, [[VS1]], 0
33 define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) {
44
55 ; CHECK-LABEL: testSpill:
6 ; CHECK: li 11, 80
7 ; CHECK: li 12, 96
8 ; CHECK: li 3, 48
9 ; CHECK: li 10, 64
10 ; CHECK: stxvd2x 62, 1, 11 # 16-byte Folded Spill
11 ; CHECK: stxvd2x 63, 1, 12 # 16-byte Folded Spill
12 ; CHECK: stxvd2x 60, 1, 3 # 16-byte Folded Spill
13 ; CHECK: stxvd2x 61, 1, 10 # 16-byte Folded Spill
14 ; CHECK: li 9, 96
15 ; CHECK: li 10, 80
16 ; CHECK: li 11, 64
17 ; CHECK: li 12, 48
18 ; CHECK: lxvd2x 63, 1, 9 # 16-byte Folded Reload
19 ; CHECK: lxvd2x 62, 1, 10 # 16-byte Folded Reload
20 ; CHECK: lxvd2x 61, 1, 11 # 16-byte Folded Reload
21 ; CHECK: lxvd2x 60, 1, 12 # 16-byte Folded Reload
6 ; CHECK-DAG: li [[REG48:[0-9]+]], 48
7 ; CHECK-DAG: li [[REG64:[0-9]+]], 64
8 ; CHECK-DAG: li [[REG80:[0-9]+]], 80
9 ; CHECK-DAG: li [[REG96:[0-9]+]], 96
10 ; CHECK-DAG: stxvd2x 60, 1, [[REG48]] # 16-byte Folded Spill
11 ; CHECK-DAG: stxvd2x 61, 1, [[REG64]] # 16-byte Folded Spill
12 ; CHECK-DAG: stxvd2x 62, 1, [[REG80]] # 16-byte Folded Spill
13 ; CHECK-DAG: stxvd2x 63, 1, [[REG96]] # 16-byte Folded Spill
14 ; CHECK: .LBB0_3
15 ; CHECK-DAG: li [[REG96_LD:[0-9]+]], 96
16 ; CHECK-DAG: li [[REG80_LD:[0-9]+]], 80
17 ; CHECK-DAG: li [[REG64_LD:[0-9]+]], 64
18 ; CHECK-DAG: li [[REG48_LD:[0-9]+]], 48
19 ; CHECK-DAG: lxvd2x 63, 1, [[REG96_LD]] # 16-byte Folded Reload
20 ; CHECK-DAG: lxvd2x 62, 1, [[REG80_LD]] # 16-byte Folded Reload
21 ; CHECK-DAG: lxvd2x 61, 1, [[REG64_LD]] # 16-byte Folded Reload
22 ; CHECK-DAG: lxvd2x 60, 1, [[REG48_LD]] # 16-byte Folded Reload
2223 ; CHECK: mtlr 0
2324 ; CHECK-NEXT: blr
2425 ;
2526 ; CHECK-PWR9-LABEL: testSpill:
26 ; CHECK-PWR9: stxv 62, 64(1) # 16-byte Folded Spill
27 ; CHECK-PWR9: stxv 63, 80(1) # 16-byte Folded Spill
28 ; CHECK-PWR9: stxv 60, 32(1) # 16-byte Folded Spill
29 ; CHECK-PWR9: stxv 61, 48(1) # 16-byte Folded Spill
30 ; CHECK-PWR9: lxv 63, 80(1) # 16-byte Folded Reload
31 ; CHECK-PWR9: lxv 62, 64(1) # 16-byte Folded Reload
32 ; CHECK-PWR9: lxv 61, 48(1) # 16-byte Folded Reload
33 ; CHECK-PWR9: lxv 60, 32(1) # 16-byte Folded Reload
27 ; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill
28 ; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill
29 ; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill
30 ; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill
31 ; CHECK-PWR9-NOT: NOT
32 ; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload
33 ; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload
34 ; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload
35 ; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload
3436 ; CHECK-PWR9: mtlr 0
3537 ; CHECK-PWR9-NEXT: blr
3638