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SSARegMap -- the mapping between SSARegisters and their RegisterClasses, which imply types of SSA Registers. This is on a per-function basis, so the MachineFunction contains the SSARegMap, and has accessor functions to it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4774 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 17 years ago
2 changed file(s) with 53 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
99 #define LLVM_CODEGEN_MACHINEFUNCTION_H
1010
1111 #include "llvm/CodeGen/MachineBasicBlock.h"
12 #include "llvm/CodeGen/SSARegMap.h"
1213 #include "llvm/Annotation.h"
1314 #include "Support/HashExtras.h"
1415 #include "Support/hash_set"
4546 bool compiledAsLeaf;
4647 bool spillsAreaFrozen;
4748 bool automaticVarsAreaFrozen;
49
50 // Keeping track of mapping from SSA values to registers
51 SSARegMap *SSARegMapping;
4852
4953 public:
5054 MachineFunction(const Function *Fn, const TargetMachine& target);
8589 static void destruct(const Function *F);
8690 static MachineFunction& get(const Function *F);
8791
92 // Getting and storing SSARegMap information
93 const TargetRegisterClass* getRegClass(unsigned Reg) {
94 return SSARegMapping->getRegClass(Reg);
95 }
96 void addRegMap(unsigned Reg, const TargetRegisterClass *RegClass) {
97 SSARegMapping->addRegMap(Reg, RegClass);
98 }
99 void clearSSARegMap() { delete SSARegMapping; }
100
88101 // Provide accessors for the MachineBasicBlock list...
89102 typedef iplist BasicBlockListType;
90103 typedef BasicBlockListType::iterator iterator;
0 //===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
1 //
2 // Map register numbers to register classes that are correctly sized (typed) to
3 // hold the information. Assists register allocation. Contained by
4 // MachineFunction, should be deleted by register allocator when it is no
5 // longer needed.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_CODEGEN_SSAREGMAP_H
10 #define LLVM_CODEGEN_SSAREGMAP_H
11
12 #include "llvm/Target/MRegisterInfo.h"
13
14 class TargetRegisterClass;
15
16 class SSARegMap {
17 std::vector RegClassMap;
18
19 unsigned rescale(unsigned Reg) {
20 return Reg - MRegisterInfo::FirstVirtualRegister;
21 }
22
23 public:
24 SSARegMap() {}
25
26 const TargetRegisterClass* getRegClass(unsigned Reg) {
27 unsigned actualReg = rescale(Reg);
28 assert(actualReg < RegClassMap.size() && "Register out of bounds");
29 return RegClassMap[actualReg];
30 }
31
32 void addRegMap(unsigned Reg, const TargetRegisterClass* RegClass) {
33 assert(rescale(Reg) == RegClassMap.size() &&
34 "Register mapping not added in sequential order!");
35 RegClassMap.push_back(RegClass);
36 }
37 };
38
39 #endif