llvm.org GIT mirror llvm / 15f17a7
Avoid creating invalid sub/add instructions on the prolog/epilog patch by Lauro git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32577 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 13 years ago
2 changed file(s) with 105 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
3434 return NoFramePointerElim || MFI->hasVarSizedObjects();
3535 }
3636
37 #define ROTATE32L(x, n) (((x) << (n)) | ((x) >> (32 - (n))))
38
39 #define ROTATE32R(x, n) (((x) >> (n)) | ((x) << (32 - (n))))
40
41 // finds the end position of largest sequence of zeros in binary representation
42 // of 'immediate'.
43 static int findLargestZeroSequence(unsigned immediate){
44 int max_zero_pos;
45 int max_zero_length = 0;
46 int zero_pos;
47 int zero_length;
48 int pos = 0;
49 int end_pos;
50
51 while ((immediate & 0x3) == 0) {
52 immediate = ROTATE32R(immediate, 2);
53 pos+=2;
54 }
55 end_pos = pos+32;
56
57 while (pos
58 while ((immediate & 0x3) != 0) {
59 immediate = ROTATE32R(immediate, 2);
60 pos+=2;
61 }
62 zero_pos = pos;
63 while ((immediate & 0x3) == 0) {
64 immediate = ROTATE32R(immediate, 2);
65 pos+=2;
66 }
67 zero_length = pos - zero_pos;
68 if (zero_length > max_zero_length){
69 max_zero_length = zero_length;
70 max_zero_pos = zero_pos % 32;
71 }
72
73 }
74
75 return (max_zero_pos + max_zero_length) % 32;
76 }
77
78 static void splitInstructionWithImmediate(MachineBasicBlock &BB,
79 MachineBasicBlock::iterator I,
80 const TargetInstrDescriptor &TID,
81 unsigned DestReg,
82 unsigned OrigReg,
83 unsigned immediate){
84
85 if (immediate == 0){
86 BuildMI(BB, I, TID, DestReg).addReg(OrigReg).addImm(0)
87 .addImm(0).addImm(ARMShift::LSL);
88 return;
89 }
90
91 int start_pos = findLargestZeroSequence(immediate);
92 unsigned immediate_tmp = ROTATE32R(immediate, start_pos);
93
94 int pos = 0;
95 while (pos < 32){
96 while(((immediate_tmp&0x3) == 0)&&(pos<32)){
97 immediate_tmp = ROTATE32R(immediate_tmp,2);
98 pos+=2;
99 }
100 if (pos < 32){
101 BuildMI(BB, I, TID, DestReg).addReg(OrigReg)
102 .addImm(ROTATE32L(immediate_tmp&0xFF, (start_pos + pos) % 32 ))
103 .addImm(0).addImm(ARMShift::LSL);
104 immediate_tmp = ROTATE32R(immediate_tmp,8);
105 pos+=8;
106 }
107 }
108
109 }
110
37111 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
38112 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
39113 TII(tii) {
109183
110184 if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
111185 // sub sp, sp, amount
112 BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
113 .addImm(0).addImm(ARMShift::LSL);
186 splitInstructionWithImmediate(MBB, I, TII.get(ARM::SUB), ARM::R13,
187 ARM::R13, Amount);
114188 } else {
115189 // add sp, sp, amount
116190 assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
117 BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
118 .addImm(0).addImm(ARMShift::LSL);
191 splitInstructionWithImmediate(MBB, I, TII.get(ARM::ADD), ARM::R13,
192 ARM::R13, Amount);
119193 }
120194 }
121195 }
155229 // Insert a set of r12 with the full address
156230 // r12 = r13 + offset
157231 MachineBasicBlock *MBB2 = MI.getParent();
158 BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
159 .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
232 splitInstructionWithImmediate(*MBB2, II, TII.get(ARM::ADD), ARM::R12,
233 BaseRegister, Offset);
160234
161235 // Replace the FrameIndex with r12
162236 MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
191265 MFI->setStackSize(NumBytes);
192266
193267 //sub sp, sp, #NumBytes
194 BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
195 .addImm(0).addImm(ARMShift::LSL);
268 splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::SUB), ARM::R13,
269 ARM::R13, NumBytes);
270
196271
197272 if (HasFP) {
198273 BuildMI(MBB, MBBI, TII.get(ARM::STR))
218293 }
219294
220295 //add sp, sp, #NumBytes
221 BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
222 .addImm(0).addImm(ARMShift::LSL);
296 splitInstructionWithImmediate(MBB, MBBI, TII.get(ARM::ADD), ARM::R13,
297 ARM::R13, NumBytes);
298
223299 }
224300
225301 unsigned ARMRegisterInfo::getRARegister() const {
0 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
1 ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | not grep "805306384"
2
3
4 int %main() {
5 entry:
6 %retval = alloca int, align 4 ; [#uses=2]
7 %tmp = alloca int, align 4 ; [#uses=2]
8 %a = alloca [805306369 x sbyte], align 16 ; <[805306369 x sbyte]*> [#uses=0]
9 "alloca point" = bitcast int 0 to int ; [#uses=0]
10 store int 0, int* %tmp
11 %tmp = load int* %tmp ; [#uses=1]
12 store int %tmp, int* %retval
13 br label %return
14
15 return: ; preds = %entry
16 %retval = load int* %retval ; [#uses=1]
17 ret int %retval
18 }