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Merging r213915: ------------------------------------------------------------------------ r213915 | wschmidt | 2014-07-24 18:55:55 -0700 (Thu, 24 Jul 2014) | 21 lines [PATCH][PPC64LE] Correct little-endian usage of vmrgh* and vmrgl*. Because the PowerPC vmrgh* and vmrgl* instructions have a built-in big-endian bias, it is necessary to swap their inputs in little-endian mode when using them to implement a vector shuffle. This was previously missed in the vector LE implementation. There was already logic to distinguish between unary and "normal" vmrg* vector shuffles, so this patch extends that logic to use a third option: "swapped" vmrg* vector shuffles that are used for little endian in place of the "normal" ones. I've updated the vec-shuffle-le.ll test to check for the expected register ordering on the generated instructions. This bug was discovered when testing the LE and ELFv2 patches for safety if they were backported to 3.4. A different vectorization decision was made in 3.4 than on mainline trunk, and that exposed the problem. I've verified this fix takes care of that issue. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@213961 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 5 years ago
7 changed file(s) with 131 addition(s) and 71 deletion(s). Raw diff Collapse all Expand all
3131 dnl Initialize autoconf and define the package name, version number and
3232 dnl address for reporting bugs.
3333
34 AC_INIT([LLVM],[3.5.0svn],[http://llvm.org/bugs/])
34 AC_INIT([LLVM],[3.5.0],[http://llvm.org/bugs/])
3535
3636 LLVM_VERSION_MAJOR=3
3737 LLVM_VERSION_MINOR=5
3838 LLVM_VERSION_PATCH=0
39 LLVM_VERSION_SUFFIX=svn
39 LLVM_VERSION_SUFFIX=
4040
4141 AC_DEFINE_UNQUOTED([LLVM_VERSION_MAJOR], $LLVM_VERSION_MAJOR, [Major version of the LLVM API])
4242 AC_DEFINE_UNQUOTED([LLVM_VERSION_MINOR], $LLVM_VERSION_MINOR, [Minor version of the LLVM API])
0 #! /bin/sh
11 # Guess values for system-dependent variables and create Makefiles.
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561561 PACKAGE_NAME='LLVM'
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563 PACKAGE_VERSION='3.5.0svn'
564 PACKAGE_STRING='LLVM 3.5.0svn'
563 PACKAGE_VERSION='3.5.0'
564 PACKAGE_STRING='LLVM 3.5.0'
565565 PACKAGE_BUGREPORT='http://llvm.org/bugs/'
566566
567567 ac_unique_file="lib/IR/Module.cpp"
13251325 # Omit some internal or obsolete options to make the list less imposing.
13261326 # This message is too long to be a string in the A/UX 3.1 sh.
13271327 cat <<_ACEOF
1328 \`configure' configures LLVM 3.5.0svn to adapt to many kinds of systems.
1328 \`configure' configures LLVM 3.5.0 to adapt to many kinds of systems.
13291329
13301330 Usage: $0 [OPTION]... [VAR=VALUE]...
13311331
13911391
13921392 if test -n "$ac_init_help"; then
13931393 case $ac_init_help in
1394 short | recursive ) echo "Configuration of LLVM 3.5.0svn:";;
1394 short | recursive ) echo "Configuration of LLVM 3.5.0:";;
13951395 esac
13961396 cat <<\_ACEOF
13971397
15641564 test -n "$ac_init_help" && exit $ac_status
15651565 if $ac_init_version; then
15661566 cat <<\_ACEOF
1567 LLVM configure 3.5.0svn
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1940 LLVM_VERSION_SUFFIX=svn
1940 LLVM_VERSION_SUFFIX=
19411941
19421942
19431943 cat >>confdefs.h <<_ACEOF
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1986019860 # values after options handling.
1986119861 ac_log="
19862 This file was extended by LLVM $as_me 3.5.0svn, which was
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1986519865 CONFIG_FILES = $CONFIG_FILES
1991219912 _ACEOF
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19915 LLVM config.status 3.5.0svn
19915 LLVM config.status 3.5.0
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33
44 .. contents::
55 :local:
6
7 .. warning::
8 These are in-progress notes for the upcoming LLVM 3.5 release. You may
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10 /ReleaseNotes.html>`_.
116
127
138 Introduction
918918
919919 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
920920 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
921 /// The ShuffleKind distinguishes between big-endian merges with two
922 /// different inputs (0), either-endian merges with two identical inputs (1),
923 /// and little-endian merges with two different inputs (2). For the latter,
924 /// the input operands are swapped (see PPCInstrAltivec.td).
921925 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
922 bool isUnary, SelectionDAG &DAG) {
926 unsigned ShuffleKind, SelectionDAG &DAG) {
923927 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
924 if (!isUnary)
928 if (ShuffleKind == 1) // unary
929 return isVMerge(N, UnitSize, 0, 0);
930 else if (ShuffleKind == 2) // swapped
925931 return isVMerge(N, UnitSize, 0, 16);
926 return isVMerge(N, UnitSize, 0, 0);
932 else
933 return false;
927934 } else {
928 if (!isUnary)
935 if (ShuffleKind == 1) // unary
936 return isVMerge(N, UnitSize, 8, 8);
937 else if (ShuffleKind == 0) // normal
929938 return isVMerge(N, UnitSize, 8, 24);
930 return isVMerge(N, UnitSize, 8, 8);
939 else
940 return false;
931941 }
932942 }
933943
934944 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
935945 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
946 /// The ShuffleKind distinguishes between big-endian merges with two
947 /// different inputs (0), either-endian merges with two identical inputs (1),
948 /// and little-endian merges with two different inputs (2). For the latter,
949 /// the input operands are swapped (see PPCInstrAltivec.td).
936950 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
937 bool isUnary, SelectionDAG &DAG) {
951 unsigned ShuffleKind, SelectionDAG &DAG) {
938952 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
939 if (!isUnary)
953 if (ShuffleKind == 1) // unary
954 return isVMerge(N, UnitSize, 8, 8);
955 else if (ShuffleKind == 2) // swapped
940956 return isVMerge(N, UnitSize, 8, 24);
941 return isVMerge(N, UnitSize, 8, 8);
957 else
958 return false;
942959 } else {
943 if (!isUnary)
960 if (ShuffleKind == 1) // unary
961 return isVMerge(N, UnitSize, 0, 0);
962 else if (ShuffleKind == 0) // normal
944963 return isVMerge(N, UnitSize, 0, 16);
945 return isVMerge(N, UnitSize, 0, 0);
964 else
965 return false;
946966 }
947967 }
948968
60136033 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
60146034 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
60156035 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6016 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
6017 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
6018 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
6019 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
6020 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
6021 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
6036 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6037 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6038 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6039 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6040 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6041 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
60226042 return Op;
60236043 }
60246044 }
60266046 // Altivec has a variety of "shuffle immediates" that take two vector inputs
60276047 // and produce a fixed permutation. If any of these match, do not lower to
60286048 // VPERM.
6049 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
60296050 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
60306051 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
60316052 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6032 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
6033 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
6034 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
6035 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
6036 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
6037 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
6053 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6054 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6055 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6056 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6057 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6058 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
60386059 return Op;
60396060
60406061 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
307307 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
308308 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
309309 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
310 bool isUnary, SelectionDAG &DAG);
310 unsigned ShuffleKind, SelectionDAG &DAG);
311311
312312 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
313313 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
314314 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
315 bool isUnary, SelectionDAG &DAG);
315 unsigned ShuffleKind, SelectionDAG &DAG);
316316
317317 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
318318 /// amount, otherwise return -1.
4343
4444 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
4545 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
46 return PPC::isVMRGLShuffleMask(cast(N), 1, false,
47 *CurDAG);
46 return PPC::isVMRGLShuffleMask(cast(N), 1, 0, *CurDAG);
4847 }]>;
4948 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
5049 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
51 return PPC::isVMRGLShuffleMask(cast(N), 2, false,
52 *CurDAG);
50 return PPC::isVMRGLShuffleMask(cast(N), 2, 0, *CurDAG);
5351 }]>;
5452 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
5553 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
56 return PPC::isVMRGLShuffleMask(cast(N), 4, false,
57 *CurDAG);
54 return PPC::isVMRGLShuffleMask(cast(N), 4, 0, *CurDAG);
5855 }]>;
5956 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
6057 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
61 return PPC::isVMRGHShuffleMask(cast(N), 1, false,
62 *CurDAG);
58 return PPC::isVMRGHShuffleMask(cast(N), 1, 0, *CurDAG);
6359 }]>;
6460 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
6561 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
66 return PPC::isVMRGHShuffleMask(cast(N), 2, false,
67 *CurDAG);
62 return PPC::isVMRGHShuffleMask(cast(N), 2, 0, *CurDAG);
6863 }]>;
6964 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
7065 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
71 return PPC::isVMRGHShuffleMask(cast(N), 4, false,
72 *CurDAG);
66 return PPC::isVMRGHShuffleMask(cast(N), 4, 0, *CurDAG);
7367 }]>;
7468
7569
7670 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
7771 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
78 return PPC::isVMRGLShuffleMask(cast(N), 1, true,
79 *CurDAG);
72 return PPC::isVMRGLShuffleMask(cast(N), 1, 1, *CurDAG);
8073 }]>;
8174 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
8275 (vector_shuffle node:$lhs, node:$rhs), [{
83 return PPC::isVMRGLShuffleMask(cast(N), 2, true,
84 *CurDAG);
76 return PPC::isVMRGLShuffleMask(cast(N), 2, 1, *CurDAG);
8577 }]>;
8678 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
8779 (vector_shuffle node:$lhs, node:$rhs), [{
88 return PPC::isVMRGLShuffleMask(cast(N), 4, true,
89 *CurDAG);
80 return PPC::isVMRGLShuffleMask(cast(N), 4, 1, *CurDAG);
9081 }]>;
9182 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
9283 (vector_shuffle node:$lhs, node:$rhs), [{
93 return PPC::isVMRGHShuffleMask(cast(N), 1, true,
94 *CurDAG);
84 return PPC::isVMRGHShuffleMask(cast(N), 1, 1, *CurDAG);
9585 }]>;
9686 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
9787 (vector_shuffle node:$lhs, node:$rhs), [{
98 return PPC::isVMRGHShuffleMask(cast(N), 2, true,
99 *CurDAG);
88 return PPC::isVMRGHShuffleMask(cast(N), 2, 1, *CurDAG);
10089 }]>;
10190 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
10291 (vector_shuffle node:$lhs, node:$rhs), [{
103 return PPC::isVMRGHShuffleMask(cast(N), 4, true,
104 *CurDAG);
92 return PPC::isVMRGHShuffleMask(cast(N), 4, 1, *CurDAG);
93 }]>;
94
95
96 // These fragments are provided for little-endian, where the inputs must be
97 // swapped for correct semantics.
98 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
99 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
100 return PPC::isVMRGLShuffleMask(cast(N), 1, 2, *CurDAG);
101 }]>;
102 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
103 (vector_shuffle node:$lhs, node:$rhs), [{
104 return PPC::isVMRGLShuffleMask(cast(N), 2, 2, *CurDAG);
105 }]>;
106 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
107 (vector_shuffle node:$lhs, node:$rhs), [{
108 return PPC::isVMRGLShuffleMask(cast(N), 4, 2, *CurDAG);
109 }]>;
110 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
111 (vector_shuffle node:$lhs, node:$rhs), [{
112 return PPC::isVMRGHShuffleMask(cast(N), 1, 2, *CurDAG);
113 }]>;
114 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
115 (vector_shuffle node:$lhs, node:$rhs), [{
116 return PPC::isVMRGHShuffleMask(cast(N), 2, 2, *CurDAG);
117 }]>;
118 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
119 (vector_shuffle node:$lhs, node:$rhs), [{
120 return PPC::isVMRGHShuffleMask(cast(N), 4, 2, *CurDAG);
105121 }]>;
106122
107123
802818 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
803819 (VMRGHW $vA, $vA)>;
804820
821 // Match vmrg*(y,x), i.e., swapped operands. These fragments
822 // are matched for little-endian, where the inputs must be
823 // swapped for correct semantics.
824 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
825 (VMRGLB $vB, $vA)>;
826 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
827 (VMRGLH $vB, $vA)>;
828 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
829 (VMRGLW $vB, $vA)>;
830 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
831 (VMRGHB $vB, $vA)>;
832 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
833 (VMRGHH $vB, $vA)>;
834 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
835 (VMRGHW $vB, $vA)>;
836
805837 // Logical Operations
806838 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
807839
4747 %tmp = load <16 x i8>* %A
4848 %tmp2 = load <16 x i8>* %B
4949 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
50 ; CHECK: vmrglb
50 ; CHECK: lvx [[REG1:[0-9]+]]
51 ; CHECK: lvx [[REG2:[0-9]+]]
52 ; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
5153 store <16 x i8> %tmp3, <16 x i8>* %A
5254 ret void
5355 }
6870 %tmp = load <16 x i8>* %A
6971 %tmp2 = load <16 x i8>* %B
7072 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
71 ; CHECK: vmrghb
73 ; CHECK: lvx [[REG1:[0-9]+]]
74 ; CHECK: lvx [[REG2:[0-9]+]]
75 ; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
7276 store <16 x i8> %tmp3, <16 x i8>* %A
7377 ret void
7478 }
8993 %tmp = load <16 x i8>* %A
9094 %tmp2 = load <16 x i8>* %B
9195 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
92 ; CHECK: vmrglh
96 ; CHECK: lvx [[REG1:[0-9]+]]
97 ; CHECK: lvx [[REG2:[0-9]+]]
98 ; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
9399 store <16 x i8> %tmp3, <16 x i8>* %A
94100 ret void
95101 }
110116 %tmp = load <16 x i8>* %A
111117 %tmp2 = load <16 x i8>* %B
112118 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
113 ; CHECK: vmrghh
119 ; CHECK: lvx [[REG1:[0-9]+]]
120 ; CHECK: lvx [[REG2:[0-9]+]]
121 ; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
114122 store <16 x i8> %tmp3, <16 x i8>* %A
115123 ret void
116124 }
131139 %tmp = load <16 x i8>* %A
132140 %tmp2 = load <16 x i8>* %B
133141 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
134 ; CHECK: vmrglw
142 ; CHECK: lvx [[REG1:[0-9]+]]
143 ; CHECK: lvx [[REG2:[0-9]+]]
144 ; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
135145 store <16 x i8> %tmp3, <16 x i8>* %A
136146 ret void
137147 }
152162 %tmp = load <16 x i8>* %A
153163 %tmp2 = load <16 x i8>* %B
154164 %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32>
155 ; CHECK: vmrghw
165 ; CHECK: lvx [[REG1:[0-9]+]]
166 ; CHECK: lvx [[REG2:[0-9]+]]
167 ; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
156168 store <16 x i8> %tmp3, <16 x i8>* %A
157169 ret void
158170 }