llvm.org GIT mirror llvm / 159e7f4
[PowerPC] Lower VSELECT using xxsel when VSX is available With VSX there is a real vector select instruction, and so we should use it. Note that VSELECT will still scalarize for v2f64 because the corresponding SetCC result type (v2i64) is not currently a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204801 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
3 changed file(s) with 99 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
830830 case ISD::SETONE:
831831 case ISD::SETUNE: {
832832 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
833 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp);
833 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLNOR :
834 PPC::VNOR,
835 VecVT, VCmp, VCmp);
834836 }
835837 case ISD::SETLT:
836838 case ISD::SETOLT:
852854 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
853855 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget.hasVSX());
854856 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
855 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ);
857 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLOR :
858 PPC::VOR,
859 VecVT, VCmpGT, VCmpEQ);
856860 }
857861 }
858862 case ISD::SETLE:
861865 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
862866 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget.hasVSX());
863867 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
864 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ);
868 return CurDAG->SelectNodeTo(N, PPCSubTarget.hasVSX() ? PPC::XXLOR :
869 PPC::VOR,
870 VecVT, VCmpLE, VCmpEQ);
865871 }
866872 default:
867873 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
13221328 getI32Imm(BROpc) };
13231329 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
13241330 }
1331 case ISD::VSELECT:
1332 if (PPCSubTarget.hasVSX()) {
1333 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
1334 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops, 3);
1335 }
1336
1337 break;
13251338 case PPCISD::BDNZ:
13261339 case PPCISD::BDZ: {
13271340 bool IsPPC64 = PPCSubTarget.isPPC64();
548548
549549 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
550550 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
551
552 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
553 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
551557
552558 // Share the Altivec comparison restrictions.
553559 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
197197 ; CHECK: blr
198198 }
199199
200 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
201 entry:
202 %m = icmp eq <4 x i32> %c, %d
203 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
204 ret <4 x i32> %v
205
206 ; CHECK-LABEL: @test20
207 ; CHECK: vcmpequw {{[0-9]+}}, 4, 5
208 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
209 ; CHECK: blr
210 }
211
212 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
213 entry:
214 %m = fcmp oeq <4 x float> %c, %d
215 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
216 ret <4 x float> %v
217
218 ; CHECK-LABEL: @test21
219 ; CHECK: xvcmpeqsp [[V1:[0-9]+]], 36, 37
220 ; CHECK: xxsel 34, 35, 34, [[V1]]
221 ; CHECK: blr
222 }
223
224 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
225 entry:
226 %m = fcmp ueq <4 x float> %c, %d
227 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
228 ret <4 x float> %v
229
230 ; CHECK-LABEL: @test22
231 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
232 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
233 ; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
234 ; CHECK-DAG: xxlnor
235 ; CHECK-DAG: xxlnor
236 ; CHECK-DAG: xxlor
237 ; CHECK-DAG: xxlor
238 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
239 ; CHECK: blr
240 }
241
242 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
243 entry:
244 %m = icmp eq <8 x i16> %c, %d
245 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
246 ret <8 x i16> %v
247
248 ; CHECK-LABEL: @test23
249 ; CHECK: vcmpequh {{[0-9]+}}, 4, 5
250 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
251 ; CHECK: blr
252 }
253
254 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
255 entry:
256 %m = icmp eq <16 x i8> %c, %d
257 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
258 ret <16 x i8> %v
259
260 ; CHECK-LABEL: @test24
261 ; CHECK: vcmpequb {{[0-9]+}}, 4, 5
262 ; CHECK: xxsel 34, 35, 34, {{[0-9]+}}
263 ; CHECK: blr
264 }
265
266 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
267 entry:
268 %m = fcmp oeq <2 x double> %c, %d
269 %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
270 ret <2 x double> %v
271
272 ; CHECK-LABEL: @test25
273 ; FIXME: This currently is scalarized because v2i64 is not a legal type.
274 ; CHECK: blr
275 }
276