llvm.org GIT mirror llvm / 1566e71
AMDGPU/SI: Use .hsatext section instead of .text for HSA Reviewers: arsenm, grosbach, rafael Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248619 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
20 changed file(s) with 258 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
0 //===-- AMDGPUHSATargetObjectFile.cpp - AMDGPU Object Files ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "AMDGPUHSATargetObjectFile.h"
10 #include "Utils/AMDGPUBaseInfo.h"
11 #include "llvm/MC/MCContext.h"
12 #include "llvm/MC/MCSectionELF.h"
13 #include "llvm/Support/ELF.h"
14
15 using namespace llvm;
16
17 void AMDGPUHSATargetObjectFile::Initialize(MCContext &Ctx,
18 const TargetMachine &TM){
19 TargetLoweringObjectFileELF::Initialize(Ctx, TM);
20 InitializeELF(TM.Options.UseInitArray);
21
22 TextSection = AMDGPU::getHSATextSection(Ctx);
23
24 }
25
26 MCSection *AMDGPUHSATargetObjectFile::SelectSectionForGlobal(
27 const GlobalValue *GV, SectionKind Kind,
28 Mangler &Mang,
29 const TargetMachine &TM) const {
30 if (Kind.isText() && !GV->hasComdat())
31 return getTextSection();
32
33 return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang, TM);
34 }
0 //===-- AMDGPUHSATargetObjectFile.h - AMDGPU HSA Object Info ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// \brief This file declares the AMDGPU-specific subclass of
11 /// TargetLoweringObjectFile use for targeting the HSA-runtime.
12 ///
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUHSATARGETOBJECTFILE_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUHSATARGETOBJECTFILE_H
17
18 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
19 #include "llvm/Target/TargetMachine.h"
20
21 namespace llvm {
22
23 class AMDGPUHSATargetObjectFile final : public TargetLoweringObjectFileELF {
24 public:
25 void Initialize(MCContext &Ctx, const TargetMachine &TM);
26
27 MCSection *SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
28 Mangler &Mang,
29 const TargetMachine &TM) const override;
30 };
31
32 } // end namespace llvm
33
34 #endif
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPUHSATargetObjectFile.h"
1617 #include "AMDGPU.h"
1718 #include "AMDGPUTargetTransformInfo.h"
1819 #include "R600ISelLowering.h"
4243 RegisterTargetMachine Y(TheGCNTarget);
4344 }
4445
46 static std::unique_ptr createTLOF(const Triple &TT) {
47 if (TT.getOS() == Triple::AMDHSA)
48 return make_unique();
49
50 return make_unique();
51 }
52
4553 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
4654 return new ScheduleDAGMILive(C, make_unique());
4755 }
7179 CodeGenOpt::Level OptLevel)
7280 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
7381 OptLevel),
74 TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this),
82 TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this),
7583 IntrinsicInfo() {
7684 setRequiresStructuredCFG(true);
7785 initAsmInfo();
7886 }
7987
80 AMDGPUTargetMachine::~AMDGPUTargetMachine() {
81 delete TLOF;
82 }
88 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
8389
8490 //===----------------------------------------------------------------------===//
8591 // R600 Target Machine (R600 -> Cayman)
3131 private:
3232
3333 protected:
34 TargetLoweringObjectFile *TLOF;
34 std::unique_ptr TLOF;
3535 AMDGPUSubtarget Subtarget;
3636 AMDGPUIntrinsicInfo IntrinsicInfo;
3737
5151 TargetIRAnalysis getTargetIRAnalysis() override;
5252
5353 TargetLoweringObjectFile *getObjFileLowering() const override {
54 return TLOF;
54 return TLOF.get();
5555 }
5656 };
5757
343343 bool ParseDirectiveHSACodeObjectISA();
344344 bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
345345 bool ParseDirectiveAMDKernelCodeT();
346 bool ParseSectionDirectiveHSAText();
346347
347348 public:
348349 AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
902903 return false;
903904 }
904905
906 bool AMDGPUAsmParser::ParseSectionDirectiveHSAText() {
907 getParser().getStreamer().SwitchSection(
908 AMDGPU::getHSATextSection(getContext()));
909 return false;
910 }
911
905912 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
906913 StringRef IDVal = DirectiveID.getString();
907914
913920
914921 if (IDVal == ".amd_kernel_code_t")
915922 return ParseDirectiveAMDKernelCodeT();
923
924 if (IDVal == ".hsatext" || IDVal == ".text")
925 return ParseSectionDirectiveHSAText();
916926
917927 return true;
918928 }
1616 AMDGPUAlwaysInlinePass.cpp
1717 AMDGPUAsmPrinter.cpp
1818 AMDGPUFrameLowering.cpp
19 AMDGPUHSATargetObjectFile.cpp
1920 AMDGPUIntrinsicInfo.cpp
2021 AMDGPUISelDAGToDAG.cpp
2122 AMDGPUMCInstLower.cpp
0 //===-------- AMDGPUELFStreamer.cpp - ELF Object Output -------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "AMDGPUELFStreamer.h"
10 #include "Utils/AMDGPUBaseInfo.h"
11
12 using namespace llvm;
13
14 void AMDGPUELFStreamer::InitSections(bool NoExecStack) {
15 // Start with the .hsatext section by default.
16 SwitchSection(AMDGPU::getHSATextSection(getContext()));
17 }
18
19 MCELFStreamer *llvm::createAMDGPUELFStreamer(MCContext &Context,
20 MCAsmBackend &MAB,
21 raw_pwrite_stream &OS,
22 MCCodeEmitter *Emitter,
23 bool RelaxAll) {
24 return new AMDGPUELFStreamer(Context, MAB, OS, Emitter);
25 }
0 //===-------- AMDGPUELFStreamer.h - ELF Object Output ---------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This is a custom MCELFStreamer which allows us to insert some hooks before
10 // emitting data into an actual object file.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H
15 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H
16
17 #include "llvm/MC/MCELFStreamer.h"
18
19 namespace llvm {
20 class MCAsmBackend;
21 class MCCodeEmitter;
22 class MCContext;
23 class MCSubtargetInfo;
24
25 class AMDGPUELFStreamer : public MCELFStreamer {
26 public:
27 AMDGPUELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS,
28 MCCodeEmitter *Emitter)
29 : MCELFStreamer(Context, MAB, OS, Emitter) { }
30
31 virtual void InitSections(bool NoExecStac) override;
32 };
33
34 MCELFStreamer *createAMDGPUELFStreamer(MCContext &Context, MCAsmBackend &MAB,
35 raw_pwrite_stream &OS,
36 MCCodeEmitter *Emitter, bool RelaxAll);
37 } // namespace llvm.
38
39 #endif
4040 //===--- Dwarf Emission Directives -----------------------------------===//
4141 SupportsDebugInformation = true;
4242 }
43
44 bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
45 return SectionName == ".hsatext" ||
46 MCAsmInfo::shouldOmitSectionDirective(SectionName);
47 }
2626 class AMDGPUMCAsmInfo : public MCAsmInfoELF {
2727 public:
2828 explicit AMDGPUMCAsmInfo(const Triple &TT);
29 bool shouldOmitSectionDirective(StringRef SectionName) const override;
2930 };
3031 } // namespace llvm
3132 #endif
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "AMDGPUMCTargetDesc.h"
15 #include "AMDGPUELFStreamer.h"
1516 #include "AMDGPUMCAsmInfo.h"
1617 #include "AMDGPUTargetStreamer.h"
1718 #include "InstPrinter/AMDGPUInstPrinter.h"
8485 return new AMDGPUTargetELFStreamer(S);
8586 }
8687
88 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
89 MCAsmBackend &MAB, raw_pwrite_stream &OS,
90 MCCodeEmitter *Emitter, bool RelaxAll) {
91 if (T.getOS() == Triple::AMDHSA)
92 return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
93
94 return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
95 }
96
8797 extern "C" void LLVMInitializeAMDGPUTargetMC() {
8898 for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
8999 RegisterMCAsmInfo X(*T);
94104 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
95105 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
96106 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
107 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
97108 }
98109
99110 // R600 specific registration
1212
1313 #include "AMDGPUTargetStreamer.h"
1414 #include "SIDefines.h"
15 #include "Utils/AMDGPUBaseInfo.h"
1516 #include "llvm/ADT/Twine.h"
1617 #include "llvm/MC/MCContext.h"
1718 #include "llvm/MC/MCELFStreamer.h"
290291
291292 MCStreamer &OS = getStreamer();
292293 OS.PushSection();
293 OS.SwitchSection(OS.getContext().getObjectFileInfo()->getTextSection());
294 // The MCObjectFileInfo that is available to the assembler is a generic
295 // implementation and not AMDGPUHSATargetObjectFile, so we can't use
296 // MCObjectFileInfo::getTextSection() here for fetching the HSATextSection.
297 OS.SwitchSection(AMDGPU::getHSATextSection(OS.getContext()));
294298 OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
295299 OS.PopSection();
296300 }
11 add_llvm_library(LLVMAMDGPUDesc
22 AMDGPUAsmBackend.cpp
33 AMDGPUELFObjectWriter.cpp
4 AMDGPUELFStreamer.cpp
45 AMDGPUMCCodeEmitter.cpp
56 AMDGPUMCTargetDesc.cpp
67 AMDGPUMCAsmInfo.cpp
1818 type = Library
1919 name = AMDGPUDesc
2020 parent = AMDGPU
21 required_libraries = MC AMDGPUAsmPrinter AMDGPUInfo Support
21 required_libraries = MC AMDGPUAsmPrinter AMDGPUInfo AMDGPUUtils Support
2222 add_to_library_groups = AMDGPU
66 //
77 //===----------------------------------------------------------------------===//
88 #include "AMDGPUBaseInfo.h"
9 #include "llvm/MC/MCContext.h"
10 #include "llvm/MC/MCSectionELF.h"
911 #include "llvm/MC/SubtargetFeature.h"
1012
1113 #define GET_SUBTARGETINFO_ENUM
5557 Header.private_segment_alignment = 4;
5658 }
5759
60 MCSection *getHSATextSection(MCContext &Ctx) {
61 return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
62 ELF::SHF_ALLOC | ELF::SHF_WRITE |
63 ELF::SHF_EXECINSTR |
64 ELF::SHF_AMDGPU_HSA_AGENT |
65 ELF::SHF_AMDGPU_HSA_CODE);
66 }
67
5868 } // End namespace AMDGPU
5969 } // End namespace llvm
1414 namespace llvm {
1515
1616 class FeatureBitset;
17 class MCContext;
18 class MCSection;
1719
1820 namespace AMDGPU {
1921
2628 IsaVersion getIsaVersion(const FeatureBitset &Features);
2729 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
2830 const FeatureBitset &Features);
31 MCSection *getHSATextSection(MCContext &Ctx);
2932
3033 } // end namespace AMDGPU
3134 } // end namespace llvm
1818 type = Library
1919 name = AMDGPUUtils
2020 parent = AMDGPU
21 required_libraries = Support
21 required_libraries = MC Support
2222 add_to_library_groups = AMDGPU
44
55 ; The SHT_NOTE section contains the output from the .hsa_code_object_*
66 ; directives.
7
8 ; ELF: Section {
9 ; ELF: Name: .hsatext
10 ; ELF: Type: SHT_PROGBITS (0x1)
11 ; ELF: Flags [ (0xC00007)
12 ; ELF: SHF_ALLOC (0x2)
13 ; ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
14 ; ELF: SHF_AMDGPU_HSA_CODE (0x400000)
15 ; ELF: SHF_EXECINSTR (0x4)
16 ; ELF: SHF_WRITE (0x1)
17 ; ELF: }
718
819 ; ELF: SHT_NOTE
920 ; ELF: 0000: 04000000 08000000 01000000 414D4400
1526 ; HSA: .hsa_code_object_version 1,0
1627 ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
1728 ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
29
30 ; HSA: .hsatext
1831
1932 ; HSA: {{^}}simple:
2033 ; HSA: .amd_kernel_code_t
0 // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
1 // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF
2
3 // For compatibility reasons we treat convert .text sections to .hsatext
4
5 // ELF: Section {
6
7 // We want to avoid emitting an empty .text section.
8 // ELF-NOT: Name: .text
9
10 // ELF: Name: .hsatext
11 // ELF: Type: SHT_PROGBITS (0x1)
12 // ELF: Flags [ (0xC00007)
13 // ELF: SHF_ALLOC (0x2)
14 // ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
15 // ELF: SHF_AMDGPU_HSA_CODE (0x400000)
16 // ELF: SHF_EXECINSTR (0x4)
17 // ELF: SHF_WRITE (0x1)
18 // ELF: Size: 260
19 // ELF: }
20
21 .hsa_code_object_version 1,0
22 // ASM: .hsa_code_object_version 1,0
23
24 .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
25 // ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
26
27 .text
28 // ASM: .hsatext
29
30 .amd_kernel_code_t
31 .end_amd_kernel_code_t
32
33 s_endpgm
0 // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
11 // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF
2
3 // ELF: Section {
4 // ELF: Name: .hsatext
5 // ELF: Type: SHT_PROGBITS (0x1)
6 // ELF: Flags [ (0xC00007)
7 // ELF: SHF_ALLOC (0x2)
8 // ELF: SHF_AMDGPU_HSA_AGENT (0x800000)
9 // ELF: SHF_AMDGPU_HSA_CODE (0x400000)
10 // ELF: SHF_EXECINSTR (0x4)
11 // ELF: SHF_WRITE (0x1)
12 // ELF: }
213
314 // ELF: SHT_NOTE
415 // ELF: 0000: 04000000 08000000 01000000 414D4400
1324 .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
1425 // ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
1526
16 .text
27 .hsatext
28 // ASM: .hsatext
29
1730 amd_kernel_code_t_test_all:
1831 ; Test all amd_kernel_code_t members with non-default values.
1932 .amd_kernel_code_t