llvm.org GIT mirror llvm / 1536863
AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI Summary: These register has different encodings on CI and VI, so we add pseudo FLAT_SCRACTH registers to be used before MC, and subtarget specific registers to be used by the MC layer. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15661 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256178 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
6 changed file(s) with 86 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
6060 MCOp = MCOperand::createImm(MO.getImm());
6161 break;
6262 case MachineOperand::MO_Register:
63 MCOp = MCOperand::createReg(MO.getReg());
63 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
6464 break;
6565 case MachineOperand::MO_MachineBasicBlock:
6666 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
8484 unsigned RegNo;
8585 int Modifiers;
8686 const MCRegisterInfo *TRI;
87 const MCSubtargetInfo *STI;
8788 bool IsForcedVOP3;
8889 };
8990
103104 }
104105
105106 void addRegOperands(MCInst &Inst, unsigned N) const {
106 Inst.addOperand(MCOperand::createReg(getReg()));
107 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), *Reg.STI)));
107108 }
108109
109110 void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
298299 static std::unique_ptr CreateReg(unsigned RegNo, SMLoc S,
299300 SMLoc E,
300301 const MCRegisterInfo *TRI,
302 const MCSubtargetInfo *STI,
301303 bool ForceVOP3) {
302304 auto Op = llvm::make_unique(Register);
303305 Op->Reg.RegNo = RegNo;
304306 Op->Reg.TRI = TRI;
307 Op->Reg.STI = STI;
305308 Op->Reg.Modifiers = -1;
306309 Op->Reg.IsForcedVOP3 = ForceVOP3;
307310 Op->StartLoc = S;
332335 unsigned ForcedEncodingSize;
333336
334337 bool isSI() const {
335 return STI->getFeatureBits()[AMDGPU::FeatureSouthernIslands];
338 return AMDGPU::isSI(getSTI());
336339 }
337340
338341 bool isCI() const {
339 return STI->getFeatureBits()[AMDGPU::FeatureSeaIslands];
342 return AMDGPU::isCI(getSTI());
340343 }
341344
342345 bool isVI() const {
343 return getSTI().getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
346 return AMDGPU::isVI(getSTI());
344347 }
345348
346349 bool hasSGPR102_SGPR103() const {
11771180
11781181
11791182 Operands.push_back(AMDGPUOperand::CreateReg(
1180 RegNo, S, E, getContext().getRegisterInfo(),
1183 RegNo, S, E, getContext().getRegisterInfo(), &getSTI(),
11811184 isForcedVOP3()));
11821185
11831186 if (HasModifiers || Modifiers) {
4343 def SCC : SIReg<"scc", 253>;
4444 def M0 : SIReg <"m0", 124>;
4545
46 def FLAT_SCR_LO : SIReg<"flat_scratch_lo", 104>; // Offset in units of 256-bytes.
47 def FLAT_SCR_HI : SIReg<"flat_scratch_hi", 105>; // Size is the per-thread scratch size, in bytes.
48
49 // Pair to indicate location of scratch space for flat accesses.
50 def FLAT_SCR : RegisterWithSubRegs <"flat_scratch", [FLAT_SCR_LO, FLAT_SCR_HI]>,
51 DwarfRegAlias> {
46 multiclass FLAT_SCR_LOHI_m ci_e, bits<16> vi_e> {
47 def _ci : SIReg;
48 def _vi : SIReg;
49 def "" : SIReg<"", 0>;
50 }
51
52 class FlatReg encoding> :
53 RegisterWithSubRegs<"flat_scratch", [lo, hi]>,
54 DwarfRegAlias {
5255 let Namespace = "AMDGPU";
5356 let SubRegIndices = [sub0, sub1];
54 let HWEncoding = 104;
55 }
57 let HWEncoding = encoding;
58 }
59
60 defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
61 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
62
63 def FLAT_SCR_ci : FlatReg;
64 def FLAT_SCR_vi : FlatReg;
65 def FLAT_SCR : FlatReg;
5666
5767 // SGPR registers
5868 foreach Index = 0-103 in {
1212 #include "llvm/IR/GlobalValue.h"
1313 #include "llvm/MC/MCContext.h"
1414 #include "llvm/MC/MCSectionELF.h"
15 #include "llvm/MC/MCSubtargetInfo.h"
1516 #include "llvm/MC/SubtargetFeature.h"
1617
1718 #define GET_SUBTARGETINFO_ENUM
1819 #include "AMDGPUGenSubtargetInfo.inc"
1920 #undef GET_SUBTARGETINFO_ENUM
21
22 #define GET_REGINFO_ENUM
23 #include "AMDGPUGenRegisterInfo.inc"
24 #undef GET_REGINFO_ENUM
2025
2126 namespace llvm {
2227 namespace AMDGPU {
116121 return ShaderType;
117122 }
118123
124 bool isSI(const MCSubtargetInfo &STI) {
125 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
126 }
127
128 bool isCI(const MCSubtargetInfo &STI) {
129 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
130 }
131
132 bool isVI(const MCSubtargetInfo &STI) {
133 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
134 }
135
136 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
137
138 switch(Reg) {
139 default: break;
140 case AMDGPU::FLAT_SCR:
141 assert(!isSI(STI));
142 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
143
144 case AMDGPU::FLAT_SCR_LO:
145 assert(!isSI(STI));
146 return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
147
148 case AMDGPU::FLAT_SCR_HI:
149 assert(!isSI(STI));
150 return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
151 }
152 return Reg;
153 }
154
119155 } // End namespace AMDGPU
120156 } // End namespace llvm
1818 class GlobalValue;
1919 class MCContext;
2020 class MCSection;
21 class MCSubtargetInfo;
2122
2223 namespace AMDGPU {
2324
4445
4546 unsigned getShaderType(const Function &F);
4647
48 bool isSI(const MCSubtargetInfo &STI);
49 bool isCI(const MCSubtargetInfo &STI);
50 bool isVI(const MCSubtargetInfo &STI);
51
52 /// If \p Reg is a pseudo reg, return the correct hardware register given
53 /// \p STI otherwise return \p Reg.
54 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
55
4756 } // end namespace AMDGPU
4857 } // end namespace llvm
4958
None // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=CI %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SI -check-prefix=GCN %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
3
4 // Add a different RUN line for the failing checks, because when stderr and stdout are mixed the
5 // order things are printed is not deterministic.
6 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
7 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
38
49 s_mov_b64 flat_scratch, -1
510 // SI: error: invalid operand for instruction
6 // CI-NOT: error
7 // VI-NOT: error
11 // CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
12 // VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
813
914 s_mov_b32 flat_scratch_lo, -1
1015 // SI: error: invalid operand for instruction
11 // CI-NOT: error
12 // VI-NOT: error
16 // CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
17 // VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
1318
1419 s_mov_b32 flat_scratch_hi, -1
1520 // SI: error: invalid operand for instruction
16 // CI-NOT: error
17 // VI-NOT: error
21 // CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
22 // VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
1823
1924
2025 s_mov_b64 flat_scratch_lo, -1