llvm.org GIT mirror llvm / 150ff17
[TableGen] Allow DAG isel patterns to override default operands. When a Tablegen instruction description uses `OperandWithDefaultOps`, isel patterns for that instruction don't have to fill in the default value for the operand in question. But the flip side is that they actually //can't// override the defaults even if they want to. This will be very inconvenient for the Arm backend, when we start wanting to write isel patterns that generate the many MVE predicated vector instructions, in the form with predication actually enabled. So this small Tablegen fix makes it possible to write an isel pattern either with or without values for a defaulted operand, and have the default values filled in only if they are not overridden. If all the defaulted operands come at the end of the instruction's operand list, there's a natural way to match them up to the arguments supplied in the pattern: consume pattern arguments until you run out, then fill in any missing instruction operands with their default values. But if defaulted and non-defaulted operands are interleaved, it's less clear what to do. This does happen in existing targets (the first example I came across was KILLGT, in the AMDGPU/R600 backend), and of course they expect the previous behaviour (that the default for those operands is used and a pattern argument is not consumed), so for backwards compatibility I've stuck with that. Reviewers: nhaehnle, hfinkel, dmgreen Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365114 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham a month ago
4 changed file(s) with 150 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
0 // RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
1 // RUN: FileCheck --check-prefix=ADD %s < %t
2 // RUN: FileCheck --check-prefix=ADDINT %s < %t
3 // RUN: FileCheck --check-prefix=SUB %s < %t
4 // RUN: FileCheck --check-prefix=MULINT %s < %t
5
6 include "llvm/Target/Target.td"
7
8 def TestInstrInfo : InstrInfo;
9 def TestTarget : Target {
10 let InstructionSet = TestInstrInfo;
11 }
12
13 class TestEncoding : Instruction {
14 field bits<32> Inst;
15 }
16
17 class TestReg : Register<"R"#index, []> {
18 let HWEncoding{15-4} = 0;
19 let HWEncoding{3-0} = !cast>(index);
20 }
21 foreach i = 0-15 in
22 def "R"#i : TestReg;
23
24 def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
25
26 def IntOperand: Operand;
27 def OptionalIntOperand: OperandWithDefaultOps;
28
29 class RRI Opcode> : TestEncoding {
30 dag OutOperandList = (outs Reg:$dest);
31 dag InOperandList = (ins Reg:$src1, Reg:$src2, OptionalIntOperand:$imm);
32 string AsmString = Mnemonic # " $dest1, $src1, $src2, #$imm";
33 string AsmVariantName = "";
34 field bits<4> dest;
35 field bits<4> src1;
36 field bits<4> src2;
37 field bits<16> imm;
38 let Inst{31-28} = Opcode;
39 let Inst{27-24} = dest;
40 let Inst{23-20} = src1;
41 let Inst{19-16} = src2;
42 let Inst{15-0} = imm;
43 }
44
45 def AddRRI : RRI<"add", 0b0001>;
46
47 // I define one of these intrinsics with IntrNoMem and the other
48 // without it, so that they'll match different top-level DAG opcodes
49 // (INTRINSIC_WO_CHAIN and INTRINSIC_W_CHAIN), which makes the
50 // FileCheck-herding easier, because every case I want to detect
51 // should show up as a separate top-level switch element.
52 def int_addplus1 : Intrinsic<
53 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
54 def int_mul3 : Intrinsic<
55 [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>;
56
57 def AddPat : Pat<(add i32:$x, i32:$y),
58 (AddRRI Reg:$x, Reg:$y)>;
59 def Add1Pat : Pat<(int_addplus1 i32:$x, i32:$y),
60 (AddRRI Reg:$x, Reg:$y, (i32 1))>;
61
62 def SubRRI : RRI<"sub", 0b0010> {
63 let Pattern = [(set Reg:$dest, (sub Reg:$src1, Reg:$src2))];
64 }
65
66 def MulRRI : RRI<"mul", 0b0011> {
67 let Pattern = [(set Reg:$dest, (int_mul3 Reg:$src1, Reg:$src2, i32:$imm))];
68 }
69
70 def MulIRR : RRI<"mul2", 0b0100> {
71 let InOperandList = (ins OptionalIntOperand:$imm, Reg:$src1, Reg:$src2);
72 }
73 def MulIRRPat : Pat<(mul i32:$x, i32:$y), (MulIRR Reg:$x, Reg:$y)>;
74
75 // ADD: SwitchOpcode{{.*}}TARGET_VAL(ISD::ADD)
76 // ADD-NEXT: OPC_RecordChild0
77 // ADD-NEXT: OPC_RecordChild1
78 // ADD-NEXT: OPC_EmitInteger, MVT::i32, 0
79 // ADD-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
80
81 // ADDINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_WO_CHAIN)
82 // ADDINT-NEXT: OPC_CheckChild0Integer
83 // ADDINT-NEXT: OPC_RecordChild1
84 // ADDINT-NEXT: OPC_RecordChild2
85 // ADDINT-NEXT: OPC_EmitInteger, MVT::i32, 1
86 // ADDINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::AddRRI)
87
88 // SUB: SwitchOpcode{{.*}}TARGET_VAL(ISD::SUB)
89 // SUB-NEXT: OPC_RecordChild0
90 // SUB-NEXT: OPC_RecordChild1
91 // SUB-NEXT: OPC_EmitInteger, MVT::i32, 0
92 // SUB-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::SubRRI)
93
94 // MULINT: SwitchOpcode{{.*}}TARGET_VAL(ISD::INTRINSIC_W_CHAIN)
95 // MULINT-NEXT: OPC_RecordNode
96 // MULINT-NEXT: OPC_CheckChild1Integer
97 // MULINT-NEXT: OPC_RecordChild2
98 // MULINT-NEXT: OPC_RecordChild3
99 // MULINT-NEXT: OPC_RecordChild4
100 // MULINT-NEXT: OPC_EmitMergeInputChains
101 // MULINT-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
102
103 // MUL: SwitchOpcode{{.*}}TARGET_VAL(ISD::MUL)
104 // MUL-NEXT: OPC_EmitInteger, MVT::i32, 0
105 // MUL-NEXT: OPC_RecordChild0
106 // MUL-NEXT: OPC_RecordChild1
107 // MUL-NEXT: OPC_MorphNodeTo1, TARGET_VAL(::MulRRI)
24362436 }
24372437 }
24382438
2439 // If one or more operands with a default value appear at the end of the
2440 // formal operand list for an instruction, we allow them to be overridden
2441 // by optional operands provided in the pattern.
2442 //
2443 // But if an operand B without a default appears at any point after an
2444 // operand A with a default, then we don't allow A to be overridden,
2445 // because there would be no way to specify whether the next operand in
2446 // the pattern was intended to override A or skip it.
2447 unsigned NonOverridableOperands = Inst.getNumOperands();
2448 while (NonOverridableOperands > 0 &&
2449 CDP.operandHasDefault(Inst.getOperand(NonOverridableOperands-1)))
2450 --NonOverridableOperands;
2451
24392452 unsigned ChildNo = 0;
24402453 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) {
24412454 Record *OperandNode = Inst.getOperand(i);
24422455
2443 // If the instruction expects a predicate or optional def operand, we
2444 // codegen this by setting the operand to it's default value if it has a
2445 // non-empty DefaultOps field.
2446 if (OperandNode->isSubClassOf("OperandWithDefaultOps") &&
2447 !CDP.getDefaultOperand(OperandNode).DefaultOps.empty())
2456 // If the operand has a default value, do we use it? We must use the
2457 // default if we've run out of children of the pattern DAG to consume,
2458 // or if the operand is followed by a non-defaulted one.
2459 if (CDP.operandHasDefault(OperandNode) &&
2460 (i < NonOverridableOperands || ChildNo >= getNumChildren()))
24482461 continue;
24492462
2450 // Verify that we didn't run out of provided operands.
2463 // If we have run out of child nodes and there _isn't_ a default
2464 // value we can use for the next operand, give an error.
24512465 if (ChildNo >= getNumChildren()) {
24522466 emitTooFewOperandsError(TP, getOperator()->getName(), getNumChildren());
24532467 return false;
12811281
12821282 unsigned allocateScope() { return ++NumScopes; }
12831283
1284 bool operandHasDefault(Record *Op) const {
1285 return Op->isSubClassOf("OperandWithDefaultOps") &&
1286 !getDefaultOperand(Op).DefaultOps.empty();
1287 }
1288
12841289 private:
12851290 void ParseNodeInfo();
12861291 void ParseNodeTransforms();
793793 // 'execute always' values. Match up the node operands to the instruction
794794 // operands to do this.
795795 unsigned ChildNo = 0;
796
797 // Similarly to the code in TreePatternNode::ApplyTypeConstraints, count the
798 // number of operands at the end of the list which have default values.
799 // Those can come from the pattern if it provides enough arguments, or be
800 // filled in with the default if the pattern hasn't provided them. But any
801 // operand with a default value _before_ the last mandatory one will be
802 // filled in with their defaults unconditionally.
803 unsigned NonOverridableOperands = NumFixedOperands;
804 while (NonOverridableOperands > NumResults &&
805 CGP.operandHasDefault(II.Operands[NonOverridableOperands-1].Rec))
806 --NonOverridableOperands;
807
796808 for (unsigned InstOpNo = NumResults, e = NumFixedOperands;
797809 InstOpNo != e; ++InstOpNo) {
798810 // Determine what to emit for this operand.
799811 Record *OperandNode = II.Operands[InstOpNo].Rec;
800 if (OperandNode->isSubClassOf("OperandWithDefaultOps") &&
801 !CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
802 // This is a predicate or optional def operand; emit the
803 // 'default ops' operands.
812 if (CGP.operandHasDefault(OperandNode) &&
813 (InstOpNo < NonOverridableOperands || ChildNo >= N->getNumChildren())) {
814 // This is a predicate or optional def operand which the pattern has not
815 // overridden, or which we aren't letting it override; emit the 'default
816 // ops' operands.
804817 const DAGDefaultOperand &DefaultOp
805818 = CGP.getDefaultOperand(OperandNode);
806819 for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)