llvm.org GIT mirror llvm / 14fd63c
Add support to LegalizeTypes for building legal vectors out of illegal elements (BUILD_VECTOR). Uses and beefs up BUILD_PAIR, though it didn't really have to. Like most of LegalizeTypes, does not support soft-float. This cures all "make check" vector building failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47537 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 12 years ago
3 changed file(s) with 103 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
158158
159159 // Result Promotion.
160160 void PromoteResult(SDNode *N, unsigned ResNo);
161 SDOperand PromoteResult_BUILD_PAIR(SDNode *N);
161162 SDOperand PromoteResult_Constant(SDNode *N);
162163 SDOperand PromoteResult_CTLZ(SDNode *N);
163164 SDOperand PromoteResult_CTPOP(SDNode *N);
181182 // Operand Promotion.
182183 bool PromoteOperand(SDNode *N, unsigned OperandNo);
183184 SDOperand PromoteOperand_ANY_EXTEND(SDNode *N);
185 SDOperand PromoteOperand_BUILD_PAIR(SDNode *N);
184186 SDOperand PromoteOperand_BR_CC(SDNode *N, unsigned OpNo);
185187 SDOperand PromoteOperand_BRCOND(SDNode *N, unsigned OpNo);
188 SDOperand PromoteOperand_BUILD_VECTOR(SDNode *N);
186189 SDOperand PromoteOperand_FP_EXTEND(SDNode *N);
187190 SDOperand PromoteOperand_FP_ROUND(SDNode *N);
188191 SDOperand PromoteOperand_INT_TO_FP(SDNode *N);
239242 bool ExpandOperand(SDNode *N, unsigned OperandNo);
240243 SDOperand ExpandOperand_BIT_CONVERT(SDNode *N);
241244 SDOperand ExpandOperand_BR_CC(SDNode *N);
245 SDOperand ExpandOperand_BUILD_VECTOR(SDNode *N);
242246 SDOperand ExpandOperand_EXTRACT_ELEMENT(SDNode *N);
243247 SDOperand ExpandOperand_SETCC(SDNode *N);
244248 SDOperand ExpandOperand_SINT_TO_FP(SDOperand Source, MVT::ValueType DestTy);
864864 case ISD::MEMSET:
865865 case ISD::MEMCPY:
866866 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
867
868 case ISD::BUILD_VECTOR: Res = ExpandOperand_BUILD_VECTOR(N); break;
867869 }
868870 }
869871
12231225 }
12241226 }
12251227
1228 SDOperand DAGTypeLegalizer::ExpandOperand_BUILD_VECTOR(SDNode *N) {
1229 // The vector type is legal but the element type needs expansion.
1230 MVT::ValueType VecVT = N->getValueType(0);
1231 unsigned NumElts = MVT::getVectorNumElements(VecVT);
1232 MVT::ValueType OldVT = N->getOperand(0).getValueType();
1233 MVT::ValueType NewVT = TLI.getTypeToTransformTo(OldVT);
1234
1235 assert(MVT::getSizeInBits(OldVT) == 2 * MVT::getSizeInBits(NewVT) &&
1236 "Do not know how to expand this operand!");
1237
1238 // Build a vector of twice the length out of the expanded elements.
1239 // For example <2 x i64> -> <4 x i32>.
1240 std::vector NewElts;
1241 NewElts.reserve(NumElts*2);
1242
1243 for (unsigned i = 0; i < NumElts; ++i) {
1244 SDOperand Lo, Hi;
1245 GetExpandedOp(N->getOperand(i), Lo, Hi);
1246 if (TLI.isBigEndian())
1247 std::swap(Lo, Hi);
1248 NewElts.push_back(Lo);
1249 NewElts.push_back(Hi);
1250 }
1251
1252 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
1253 MVT::getVectorType(NewVT, NewElts.size()),
1254 &NewElts[0], NewElts.size());
1255
1256 // Convert the new vector to the old vector type.
1257 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
1258 }
4848 case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
4949 case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
5050 case ISD::LOAD: Result = PromoteResult_LOAD(cast(N)); break;
51 case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
5152
5253 case ISD::AND:
5354 case ISD::OR:
197198 // use the new one.
198199 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
199200 return Res;
201 }
202
203 SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
204 // The pair element type may be legal, or may not promote to the same type as
205 // the result, for example i16 = BUILD_PAIR (i8, i8) when i8 is legal but i16
206 // is not. Handle all cases.
207 MVT::ValueType LVT = N->getOperand(0).getValueType();
208 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
209 SDOperand Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
210 SDOperand Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, N->getOperand(1));
211 Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT),
212 TLI.getShiftAmountTy()));
213 return DAG.getNode(ISD::OR, NVT, Lo, Hi);
200214 }
201215
202216 SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
328342 case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
329343 case ISD::SINT_TO_FP:
330344 case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
331
345 case ISD::BUILD_PAIR: Res = PromoteOperand_BUILD_PAIR(N); break;
346
332347 case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
333348 case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
334349 case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
339354 case ISD::MEMSET:
340355 case ISD::MEMCPY:
341356 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
357
358 case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break;
342359
343360 case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break;
344361 }
406423 In, DAG.getValueType(OpVT));
407424
408425 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
426 }
427
428 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
429 // Since the result type is legal, the operands must promote to it.
430 MVT::ValueType OVT = N->getOperand(0).getValueType();
431 SDOperand Lo = GetPromotedOp(N->getOperand(0));
432 SDOperand Hi = GetPromotedOp(N->getOperand(1));
433 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
434
435 Lo = DAG.getZeroExtendInReg(Lo, OVT);
436 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
437 DAG.getConstant(MVT::getSizeInBits(OVT),
438 TLI.getShiftAmountTy()));
439 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
409440 }
410441
411442 SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
526557 isVolatile, Alignment);
527558 }
528559
560 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
561 // The vector type is legal but the element type is not. This implies
562 // that the vector is a power-of-two in length and that the element
563 // type does not have a strange size (eg: it is not i1).
564 MVT::ValueType VecVT = N->getValueType(0);
565 unsigned NumElts = MVT::getVectorNumElements(VecVT);
566 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
567
568 // Build a vector of half the length out of elements of twice the bitwidth.
569 // For example <4 x i16> -> <2 x i32>.
570 MVT::ValueType OldVT = N->getOperand(0).getValueType();
571 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
572 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
573
574 std::vector NewElts;
575 NewElts.reserve(NumElts/2);
576
577 for (unsigned i = 0; i < NumElts; i += 2) {
578 // Combine two successive elements into one promoted element.
579 SDOperand Lo = N->getOperand(i);
580 SDOperand Hi = N->getOperand(i+1);
581 if (TLI.isBigEndian())
582 std::swap(Lo, Hi);
583 NewElts.push_back(DAG.getNode(ISD::BUILD_PAIR, NewVT, Lo, Hi));
584 }
585
586 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
587 MVT::getVectorType(NewVT, NewElts.size()),
588 &NewElts[0], NewElts.size());
589
590 // Convert the new vector to the old vector type.
591 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
592 }
593
529594 SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) {
530595 assert(!(OpNo & 1) && "Return values should be legally typed!");
531596 assert((N->getNumOperands() & 1) && "Wrong number of operands!");