llvm.org GIT mirror llvm / 1425038
Move FrameInstructions from MachineModuleInfo to MachineFunction This is per function data so it is better kept at the function instead of the module. This is a necessary step to have machine module passes work properly. Differential Revision: https://reviews.llvm.org/D27185 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288291 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 2 years ago
17 changed file(s) with 114 addition(s) and 119 deletion(s). Raw diff Collapse all Expand all
2424 #include "llvm/CodeGen/MachineMemOperand.h"
2525 #include "llvm/IR/DebugLoc.h"
2626 #include "llvm/IR/Metadata.h"
27 #include "llvm/MC/MCDwarf.h"
2728 #include "llvm/Support/Allocator.h"
2829 #include "llvm/Support/ArrayRecycler.h"
2930 #include "llvm/Support/Compiler.h"
244245 // Allocation management for pseudo source values.
245246 std::unique_ptr PSVManager;
246247
248 /// List of moves done by a function's prolog. Used to construct frame maps
249 /// by debug and exception handling consumers.
250 std::vector FrameInstructions;
251
247252 MachineFunction(const MachineFunction &) = delete;
248253 void operator=(const MachineFunction&) = delete;
249254
639644 /// getPICBaseSymbol - Return a function-local symbol to represent the PIC
640645 /// base.
641646 MCSymbol *getPICBaseSymbol() const;
647
648 /// Returns a reference to a list of cfi instructions in the function's
649 /// prologue. Used to construct frame maps for debug and exception handling
650 /// comsumers.
651 const std::vector &getFrameInstructions() const {
652 return FrameInstructions;
653 }
654
655 LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst) {
656 FrameInstructions.push_back(Inst);
657 return FrameInstructions.size() - 1;
658 }
642659 };
643660
644661 //===--------------------------------------------------------------------===//
121121 /// want.
122122 MachineModuleInfoImpl *ObjFileMMI;
123123
124 /// List of moves done by a function's prolog. Used to construct frame maps
125 /// by debug and exception handling consumers.
126 std::vector FrameInstructions;
127
128124 /// List of LandingPadInfo describing the landing pad information in the
129125 /// current function.
130126 std::vector LandingPads;
278274 UsesMorestackAddr = b;
279275 }
280276
281 /// Returns a reference to a list of cfi instructions in the current
282 /// function's prologue. Used to construct frame maps for debug and
283 /// exception handling comsumers.
284 const std::vector &getFrameInstructions() const {
285 return FrameInstructions;
286 }
287
288 LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst) {
289 FrameInstructions.push_back(Inst);
290 return FrameInstructions.size() - 1;
291 }
292
293277 /// Return the symbol to be used for the specified basic block when its
294278 /// address is taken. This cannot be its normal LBB label because the block
295279 /// may be accessed outside its containing function.
820820 if (needsCFIMoves() == CFI_M_None)
821821 return;
822822
823 const MachineModuleInfo &MMI = MF->getMMI();
824 const std::vector &Instrs = MMI.getFrameInstructions();
823 const std::vector &Instrs = MF->getFrameInstructions();
825824 unsigned CFIIndex = MI.getOperand(0).getCFIIndex();
826825 const MCCFIInstruction &CFI = Instrs[CFIIndex];
827826 emitCFIInstruction(CFI);
13901390 bool MIParser::parseCFIOperand(MachineOperand &Dest) {
13911391 auto Kind = Token.kind();
13921392 lex();
1393 auto &MMI = MF.getMMI();
13941393 int Offset;
13951394 unsigned Reg;
13961395 unsigned CFIIndex;
13981397 case MIToken::kw_cfi_same_value:
13991398 if (parseCFIRegister(Reg))
14001399 return true;
1401 CFIIndex =
1402 MMI.addFrameInst(MCCFIInstruction::createSameValue(nullptr, Reg));
1400 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(nullptr, Reg));
14031401 break;
14041402 case MIToken::kw_cfi_offset:
14051403 if (parseCFIRegister(Reg) || expectAndConsume(MIToken::comma) ||
14061404 parseCFIOffset(Offset))
14071405 return true;
14081406 CFIIndex =
1409 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg, Offset));
1407 MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, Reg, Offset));
14101408 break;
14111409 case MIToken::kw_cfi_def_cfa_register:
14121410 if (parseCFIRegister(Reg))
14131411 return true;
14141412 CFIIndex =
1415 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
1413 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
14161414 break;
14171415 case MIToken::kw_cfi_def_cfa_offset:
14181416 if (parseCFIOffset(Offset))
14191417 return true;
14201418 // NB: MCCFIInstruction::createDefCfaOffset negates the offset.
1421 CFIIndex = MMI.addFrameInst(
1419 CFIIndex = MF.addFrameInst(
14221420 MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
14231421 break;
14241422 case MIToken::kw_cfi_def_cfa:
14271425 return true;
14281426 // NB: MCCFIInstruction::createDefCfa negates the offset.
14291427 CFIIndex =
1430 MMI.addFrameInst(MCCFIInstruction::createDefCfa(nullptr, Reg, -Offset));
1428 MF.addFrameInst(MCCFIInstruction::createDefCfa(nullptr, Reg, -Offset));
14311429 break;
14321430 default:
14331431 // TODO: Parse the other CFI operands.
887887 OS << "";
888888 break;
889889 case MachineOperand::MO_CFIIndex: {
890 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
891 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
890 const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
891 print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
892892 break;
893893 }
894894 case MachineOperand::MO_IntrinsicID: {
229229 }
230230
231231 void MachineModuleInfo::EndFunction() {
232 // Clean up frame info.
233 FrameInstructions.clear();
234
235232 // Clean up exception info.
236233 LandingPads.clear();
237234 PersonalityTypeCache = EHPersonality::Unknown;
203203 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
204204 MachineFunction &MF = *MBB.getParent();
205205 MachineFrameInfo &MFI = MF.getFrameInfo();
206 MachineModuleInfo &MMI = MF.getMMI();
207 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
208 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
206 const TargetSubtargetInfo &STI = MF.getSubtarget();
207 const MCRegisterInfo *MRI = STI.getRegisterInfo();
208 const TargetInstrInfo *TII = STI.getInstrInfo();
209209 DebugLoc DL = MBB.findDebugLoc(MBBI);
210210
211211 // Add callee saved registers to move list.
218218 int64_t Offset =
219219 MFI.getObjectOffset(Info.getFrameIdx()) - getOffsetOfLocalArea();
220220 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
221 unsigned CFIIndex = MMI.addFrameInst(
221 unsigned CFIIndex = MF.addFrameInst(
222222 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
223223 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
224224 .addCFIIndex(CFIIndex)
445445 // Label used to tie together the PROLOG_LABEL and the MachineMoves.
446446 MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
447447 // Encode the stack size of the leaf function.
448 unsigned CFIIndex = MMI.addFrameInst(
448 unsigned CFIIndex = MF.addFrameInst(
449449 MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
450450 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
451451 .addCFIIndex(CFIIndex)
620620 if (HasFP) {
621621 // Define the current CFA rule to use the provided FP.
622622 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
623 unsigned CFIIndex = MMI.addFrameInst(
623 unsigned CFIIndex = MF.addFrameInst(
624624 MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth));
625625 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
626626 .addCFIIndex(CFIIndex)
627627 .setMIFlags(MachineInstr::FrameSetup);
628628 } else {
629629 // Encode the stack size of the leaf function.
630 unsigned CFIIndex = MMI.addFrameInst(
630 unsigned CFIIndex = MF.addFrameInst(
631631 MCCFIInstruction::createDefCfaOffset(nullptr, -MFI.getStackSize()));
632632 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
633633 .addCFIIndex(CFIIndex)
200200 Info->SPAdjust += ExtraBytes;
201201 }
202202
203 void emitDefCFAOffsets(MachineModuleInfo &MMI, MachineBasicBlock &MBB,
204 const DebugLoc &dl, const ARMBaseInstrInfo &TII,
205 bool HasFP) {
203 void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
204 const ARMBaseInstrInfo &TII, bool HasFP) {
205 MachineFunction &MF = *MBB.getParent();
206206 unsigned CFAOffset = 0;
207207 for (auto &Info : Insts) {
208208 if (HasFP && !Info.BeforeFPSet)
209209 return;
210210
211211 CFAOffset -= Info.SPAdjust;
212 unsigned CFIIndex = MMI.addFrameInst(
212 unsigned CFIIndex = MF.addFrameInst(
213213 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
214214 BuildMI(MBB, std::next(Info.I), dl,
215215 TII.get(TargetOpcode::CFI_INSTRUCTION))
337337 DefCFAOffsetCandidates.addInst(std::prev(MBBI),
338338 NumBytes - ArgRegsSaveSize, true);
339339 }
340 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
340 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
341341 return;
342342 }
343343
525525 PushSize + FramePtrOffsetInPush,
526526 MachineInstr::FrameSetup);
527527 if (FramePtrOffsetInPush + PushSize != 0) {
528 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
528 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
529529 nullptr, MRI->getDwarfRegNum(FramePtr, true),
530530 -(ArgRegsSaveSize - FramePtrOffsetInPush)));
531531 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
533533 .setMIFlags(MachineInstr::FrameSetup);
534534 } else {
535535 unsigned CFIIndex =
536 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
536 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
537537 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
538538 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
539539 .addCFIIndex(CFIIndex)
568568 case ARM::R6:
569569 case ARM::R7:
570570 case ARM::LR:
571 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
571 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
572572 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
573573 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
574574 .addCFIIndex(CFIIndex)
592592 if (STI.splitFramePushPop(MF)) {
593593 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
594594 unsigned Offset = MFI.getObjectOffset(FI);
595 unsigned CFIIndex = MMI.addFrameInst(
595 unsigned CFIIndex = MF.addFrameInst(
596596 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
597597 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
598598 .addCFIIndex(CFIIndex)
614614 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
615615 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
616616 unsigned Offset = MFI.getObjectOffset(FI);
617 unsigned CFIIndex = MMI.addFrameInst(
617 unsigned CFIIndex = MF.addFrameInst(
618618 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
619619 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
620620 .addCFIIndex(CFIIndex)
627627 // throughout the process. If we have a frame pointer, it takes over the job
628628 // half-way through, so only the first few .cfi_def_cfa_offset instructions
629629 // actually get emitted.
630 DefCFAOffsetCandidates.emitDefCFAOffsets(MMI, MBB, dl, TII, HasFP);
630 DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
631631
632632 if (STI.isTargetELF() && hasFP(MF))
633633 MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
20912091 // Emit the relevant DWARF information about the change in stack pointer as
20922092 // well as where to find both r4 and r5 (the callee-save registers)
20932093 CFIIndex =
2094 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
2094 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -8));
20952095 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
20962096 .addCFIIndex(CFIIndex);
2097 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2097 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
20982098 nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
20992099 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
21002100 .addCFIIndex(CFIIndex);
2101 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2101 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
21022102 nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
21032103 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
21042104 .addCFIIndex(CFIIndex);
22092209 // Emit the DWARF info about the change in stack as well as where to find the
22102210 // previous link register
22112211 CFIIndex =
2212 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
2212 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -12));
22132213 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
22142214 .addCFIIndex(CFIIndex);
2215 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
2215 CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
22162216 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
22172217 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
22182218 .addCFIIndex(CFIIndex);
22642264 }
22652265
22662266 // Update the CFA offset now that we've popped
2267 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2267 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
22682268 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
22692269 .addCFIIndex(CFIIndex);
22702270
22872287 }
22882288
22892289 // Update the CFA offset now that we've popped
2290 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
2290 CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
22912291 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
22922292 .addCFIIndex(CFIIndex);
22932293
22942294 // Tell debuggers that r4 and r5 are now the same as they were in the
22952295 // previous function, that they're the "Same Value".
2296 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2296 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
22972297 nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
22982298 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
22992299 .addCFIIndex(CFIIndex);
2300 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createSameValue(
2300 CFIIndex = MF.addFrameInst(MCCFIInstruction::createSameValue(
23012301 nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
23022302 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
23032303 .addCFIIndex(CFIIndex);
120120 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
121121 MachineInstr::FrameSetup);
122122 CFAOffset -= ArgRegsSaveSize;
123 unsigned CFIIndex = MMI.addFrameInst(
123 unsigned CFIIndex = MF.addFrameInst(
124124 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
125125 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
126126 .addCFIIndex(CFIIndex)
132132 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
133133 MachineInstr::FrameSetup);
134134 CFAOffset -= NumBytes - ArgRegsSaveSize;
135 unsigned CFIIndex = MMI.addFrameInst(
135 unsigned CFIIndex = MF.addFrameInst(
136136 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
137137 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
138138 .addCFIIndex(CFIIndex)
196196
197197 if (adjustedGPRCS1Size) {
198198 CFAOffset -= adjustedGPRCS1Size;
199 unsigned CFIIndex = MMI.addFrameInst(
199 unsigned CFIIndex = MF.addFrameInst(
200200 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
201201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
202202 .addCFIIndex(CFIIndex)
224224 case ARM::R6:
225225 case ARM::R7:
226226 case ARM::LR:
227 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
227 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
228228 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
229229 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
230230 .addCFIIndex(CFIIndex)
242242 .setMIFlags(MachineInstr::FrameSetup));
243243 if(FramePtrOffsetInBlock) {
244244 CFAOffset += FramePtrOffsetInBlock;
245 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
245 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
246246 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
247247 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
248248 .addCFIIndex(CFIIndex)
249249 .setMIFlags(MachineInstr::FrameSetup);
250250 } else {
251251 unsigned CFIIndex =
252 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
252 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
253253 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
254254 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
255255 .addCFIIndex(CFIIndex)
291291 case ARM::R10:
292292 case ARM::R11:
293293 case ARM::R12: {
294 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
294 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
295295 nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
296296 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
297297 .addCFIIndex(CFIIndex)
309309 MachineInstr::FrameSetup);
310310 if (!HasFP) {
311311 CFAOffset -= NumBytes;
312 unsigned CFIIndex = MMI.addFrameInst(
312 unsigned CFIIndex = MF.addFrameInst(
313313 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
314314 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
315315 .addCFIIndex(CFIIndex)
813813 // MCCFIInstruction::createOffset takes the offset without sign change.
814814 auto DefCfa = MCCFIInstruction::createDefCfa(FrameLabel, DwFPReg, -8);
815815 BuildMI(MBB, At, DL, CFID)
816 .addCFIIndex(MMI.addFrameInst(DefCfa));
816 .addCFIIndex(MF.addFrameInst(DefCfa));
817817 // R31 (return addr) = CFA - 4
818818 auto OffR31 = MCCFIInstruction::createOffset(FrameLabel, DwRAReg, -4);
819819 BuildMI(MBB, At, DL, CFID)
820 .addCFIIndex(MMI.addFrameInst(OffR31));
820 .addCFIIndex(MF.addFrameInst(OffR31));
821821 // R30 (frame ptr) = CFA - 8
822822 auto OffR30 = MCCFIInstruction::createOffset(FrameLabel, DwFPReg, -8);
823823 BuildMI(MBB, At, DL, CFID)
824 .addCFIIndex(MMI.addFrameInst(OffR30));
824 .addCFIIndex(MF.addFrameInst(OffR30));
825825 }
826826
827827 static unsigned int RegsToMove[] = {
867867 auto OffReg = MCCFIInstruction::createOffset(FrameLabel, DwarfReg,
868868 Offset);
869869 BuildMI(MBB, At, DL, CFID)
870 .addCFIIndex(MMI.addFrameInst(OffReg));
870 .addCFIIndex(MF.addFrameInst(OffReg));
871871 } else {
872872 // Split the double regs into subregs, and generate appropriate
873873 // cfi_offsets.
882882 auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
883883 Offset+4);
884884 BuildMI(MBB, At, DL, CFID)
885 .addCFIIndex(MMI.addFrameInst(OffHi));
885 .addCFIIndex(MF.addFrameInst(OffHi));
886886 auto OffLo = MCCFIInstruction::createOffset(FrameLabel, LoDwarfReg,
887887 Offset);
888888 BuildMI(MBB, At, DL, CFID)
889 .addCFIIndex(MMI.addFrameInst(OffLo));
889 .addCFIIndex(MF.addFrameInst(OffLo));
890890 }
891891 }
892892 }
5555 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
5656
5757 // emit ".cfi_def_cfa_offset StackSize"
58 unsigned CFIIndex = MMI.addFrameInst(
58 unsigned CFIIndex = MF.addFrameInst(
5959 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
6060 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
6161 .addCFIIndex(CFIIndex);
7070 int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
7171 unsigned Reg = I->getReg();
7272 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
73 unsigned CFIIndex = MMI.addFrameInst(
73 unsigned CFIIndex = MF.addFrameInst(
7474 MCCFIInstruction::createOffset(nullptr, DReg, Offset));
7575 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
7676 .addCFIIndex(CFIIndex);
408408 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
409409
410410 // emit ".cfi_def_cfa_offset StackSize"
411 unsigned CFIIndex = MMI.addFrameInst(
411 unsigned CFIIndex = MF.addFrameInst(
412412 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
413413 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
414414 .addCFIIndex(CFIIndex);
442442 if (!STI.isLittle())
443443 std::swap(Reg0, Reg1);
444444
445 unsigned CFIIndex = MMI.addFrameInst(
445 unsigned CFIIndex = MF.addFrameInst(
446446 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
447447 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
448448 .addCFIIndex(CFIIndex);
449449
450 CFIIndex = MMI.addFrameInst(
450 CFIIndex = MF.addFrameInst(
451451 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
452452 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
453453 .addCFIIndex(CFIIndex);
458458 if (!STI.isLittle())
459459 std::swap(Reg0, Reg1);
460460
461 unsigned CFIIndex = MMI.addFrameInst(
461 unsigned CFIIndex = MF.addFrameInst(
462462 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
463463 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
464464 .addCFIIndex(CFIIndex);
465465
466 CFIIndex = MMI.addFrameInst(
466 CFIIndex = MF.addFrameInst(
467467 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
468468 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
469469 .addCFIIndex(CFIIndex);
470470 } else {
471471 // Reg is either in GPR32 or FGR32.
472 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
472 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
473473 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
474474 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
475475 .addCFIIndex(CFIIndex);
490490 for (int I = 0; I < 4; ++I) {
491491 int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
492492 unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
493 unsigned CFIIndex = MMI.addFrameInst(
493 unsigned CFIIndex = MF.addFrameInst(
494494 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
495495 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
496496 .addCFIIndex(CFIIndex);
504504 .setMIFlag(MachineInstr::FrameSetup);
505505
506506 // emit ".cfi_def_cfa_register $fp"
507 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
507 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
508508 nullptr, MRI->getDwarfRegNum(FP, true)));
509509 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
510510 .addCFIIndex(CFIIndex);
11041104 // because if the stack needed aligning then CFA won't be at a fixed
11051105 // offset from FP/SP.
11061106 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1107 CFIIndex = MMI.addFrameInst(
1107 CFIIndex = MF.addFrameInst(
11081108 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
11091109 } else {
11101110 // Adjust the definition of CFA to account for the change in SP.
11111111 assert(NegFrameSize);
1112 CFIIndex = MMI.addFrameInst(
1112 CFIIndex = MF.addFrameInst(
11131113 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
11141114 }
11151115 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11181118 if (HasFP) {
11191119 // Describe where FP was saved, at a fixed offset from CFA.
11201120 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1121 CFIIndex = MMI.addFrameInst(
1121 CFIIndex = MF.addFrameInst(
11221122 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
11231123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11241124 .addCFIIndex(CFIIndex);
11271127 if (FI->usesPICBase()) {
11281128 // Describe where FP was saved, at a fixed offset from CFA.
11291129 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1130 CFIIndex = MMI.addFrameInst(
1130 CFIIndex = MF.addFrameInst(
11311131 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
11321132 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11331133 .addCFIIndex(CFIIndex);
11361136 if (HasBP) {
11371137 // Describe where BP was saved, at a fixed offset from CFA.
11381138 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1139 CFIIndex = MMI.addFrameInst(
1139 CFIIndex = MF.addFrameInst(
11401140 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
11411141 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11421142 .addCFIIndex(CFIIndex);
11451145 if (MustSaveLR) {
11461146 // Describe where LR was saved, at a fixed offset from CFA.
11471147 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1148 CFIIndex = MMI.addFrameInst(
1148 CFIIndex = MF.addFrameInst(
11491149 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
11501150 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11511151 .addCFIIndex(CFIIndex);
11621162 // Change the definition of CFA from SP+offset to FP+offset, because SP
11631163 // will change at every alloca.
11641164 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1165 unsigned CFIIndex = MMI.addFrameInst(
1165 unsigned CFIIndex = MF.addFrameInst(
11661166 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
11671167
11681168 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
11961196 // the whole CR word. In the ELFv2 ABI, every CR that was
11971197 // actually saved gets its own CFI record.
11981198 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1199 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1199 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
12001200 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
12011201 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
12021202 .addCFIIndex(CFIIndex);
12041204 }
12051205
12061206 int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1207 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
1207 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
12081208 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
12091209 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
12101210 .addCFIIndex(CFIIndex);
153153
154154 emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
155155
156 MachineModuleInfo &MMI = MF.getMMI();
157156 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
158157
159158 // Emit ".cfi_def_cfa_register 30".
160159 unsigned CFIIndex =
161 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
160 MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
162161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163162 .addCFIIndex(CFIIndex);
164163
165164 // Emit ".cfi_window_save".
166 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
165 CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
167166 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168167 .addCFIIndex(CFIIndex);
169168
170169 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
171170 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
172171 // Emit ".cfi_register 15, 31".
173 CFIIndex = MMI.addFrameInst(
172 CFIIndex = MF.addFrameInst(
174173 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
175174 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176175 .addCFIIndex(CFIIndex);
349349 unsigned Reg = Save.getReg();
350350 if (SystemZ::GR64BitRegClass.contains(Reg)) {
351351 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
352 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
352 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
353353 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
354354 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
355355 .addCFIIndex(CFIIndex);
373373 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
374374
375375 // Add CFI for the allocation.
376 unsigned CFIIndex = MMI.addFrameInst(
376 unsigned CFIIndex = MF.addFrameInst(
377377 MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
378378 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
379379 .addCFIIndex(CFIIndex);
391391
392392 // Add CFI for the new frame location.
393393 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
394 unsigned CFIIndex = MMI.addFrameInst(
394 unsigned CFIIndex = MF.addFrameInst(
395395 MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
396396 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
397397 .addCFIIndex(CFIIndex);
421421 int64_t Offset =
422422 getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
423423
424 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
424 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
425425 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
426426 CFIIndexes.push_back(CFIIndex);
427427 }
417417 const DebugLoc &DL,
418418 const MCCFIInstruction &CFIInst) const {
419419 MachineFunction &MF = *MBB.getParent();
420 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
420 unsigned CFIIndex = MF.addFrameInst(CFIInst);
421421 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
422422 .addCFIIndex(CFIIndex);
423423 }
6060 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
6161 MachineBasicBlock::iterator MBBI,
6262 const DebugLoc &dl, const TargetInstrInfo &TII,
63 MachineModuleInfo *MMI, unsigned DRegNum) {
64 unsigned CFIIndex = MMI->addFrameInst(
63 MachineFunction &MF, unsigned DRegNum) {
64 unsigned CFIIndex = MF.addFrameInst(
6565 MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
6666 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
6767 .addCFIIndex(CFIIndex);
7070 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
7171 MachineBasicBlock::iterator MBBI,
7272 const DebugLoc &dl, const TargetInstrInfo &TII,
73 MachineModuleInfo *MMI, int Offset) {
73 int Offset) {
74 MachineFunction &MF = *MBB.getParent();
7475 unsigned CFIIndex =
75 MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
76 MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
7677 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
7778 .addCFIIndex(CFIIndex);
7879 }
7980
8081 static void EmitCfiOffset(MachineBasicBlock &MBB,
8182 MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
82 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
83 unsigned DRegNum, int Offset) {
84 unsigned CFIIndex = MMI->addFrameInst(
83 const TargetInstrInfo &TII, unsigned DRegNum,
84 int Offset) {
85 MachineFunction &MF = *MBB.getParent();
86 unsigned CFIIndex = MF.addFrameInst(
8587 MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
8688 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
8789 .addCFIIndex(CFIIndex);
9597 /// \param [in,out] Adjusted the current SP offset from the top of the frame.
9698 static void IfNeededExtSP(MachineBasicBlock &MBB,
9799 MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
98 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
99 int OffsetFromTop, int &Adjusted, int FrameSize,
100 bool emitFrameMoves) {
100 const TargetInstrInfo &TII, int OffsetFromTop,
101 int &Adjusted, int FrameSize, bool emitFrameMoves) {
101102 while (OffsetFromTop > Adjusted) {
102103 assert(Adjusted < FrameSize && "OffsetFromTop is beyond FrameSize");
103104 int remaining = FrameSize - Adjusted;
106107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
107108 Adjusted += OpImm;
108109 if (emitFrameMoves)
109 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
110111 }
111112 }
112113
265266 MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
266267 true);
267268 if (emitFrameMoves) {
268 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
269 EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
269270 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
270 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0);
271 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0);
271272 }
272273 }
273274
280281 assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
281282 assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
282283 int OffsetFromTop = - SpillList[i].Offset/4;
283 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
284 IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize,
284285 emitFrameMoves);
285286 int Offset = Adjusted - OffsetFromTop;
286287 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
292293 MachineMemOperand::MOStore));
293294 if (emitFrameMoves) {
294295 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
295 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillList[i].Offset);
296 EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset);
296297 }
297298 }
298299
299300 // Complete any remaining Stack adjustment.
300 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, FrameSize, Adjusted, FrameSize,
301 IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize,
301302 emitFrameMoves);
302303 assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
303304
305306 // Set the FP from the SP.
306307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
307308 if (emitFrameMoves)
308 EmitDefCfaRegister(MBB, MBBI, dl, TII, MMI,
309 EmitDefCfaRegister(MBB, MBBI, dl, TII, MF,
309310 MRI->getDwarfRegNum(FramePtr, true));
310311 }
311312
317318 const CalleeSavedInfo &CSI = SpillLabel.second;
318319 int Offset = MFI.getObjectOffset(CSI.getFrameIdx());
319320 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
320 EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset);
321 EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset);
321322 }
322323 if (XFI->hasEHSpillSlot()) {
323324 // The unwinder requires stack slot & CFI offsets for the exception info.
329330 GetEHSpillList(SpillList, MFI, XFI, PersonalityFn,
330331 MF.getSubtarget().getTargetLowering());
331332 assert(SpillList.size()==2 && "Unexpected SpillList size");
332 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
333 EmitCfiOffset(MBB, MBBI, dl, TII,
333334 MRI->getDwarfRegNum(SpillList[0].Reg, true),
334335 SpillList[0].Offset);
335 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
336 EmitCfiOffset(MBB, MBBI, dl, TII,
336337 MRI->getDwarfRegNum(SpillList[1].Reg, true),
337338 SpillList[1].Offset);
338339 }