llvm.org GIT mirror llvm / 13a8300
[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343213 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 1 year, 10 months ago
10 changed file(s) with 76 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
362362 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
363363 "Use alias analysis during codegen">;
364364
365 // Armv8.5-A extensions
366
367 def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
368 "Enable speculation control barrier" >;
369
365370 //===----------------------------------------------------------------------===//
366371 // ARM architecture class
367372 //
453458
454459 def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
455460 "Support ARM v8.5a instructions",
456 [HasV8_4aOps]>;
461 [HasV8_4aOps, FeatureSpecCtrl]>;
457462
458463 //===----------------------------------------------------------------------===//
459464 // ARM Processor subtarget features.
390390
391391 def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">;
392392
393 // Armv8.5-A extensions
394 def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
395 AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
396
393397 //===----------------------------------------------------------------------===//
394398 // ARM Flag Definitions.
395399
48744878
48754879 }
48764880
4881 // Armv8.5-A speculation barrier
4882 def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
4883 Requires<[IsARM, HasSpecCtrl]>, Sched<[]> {
4884 let Inst{31-0} = 0xf57ff070;
4885 let Unpredictable = 0x000fff0f;
4886 let hasSideEffects = 1;
4887 }
4888
48774889 let usesCustomInserter = 1, Defs = [CPSR] in {
48784890
48794891 // Pseudo instruction that combines movs + predicated rsbmi
32283228 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> {
32293229 let Inst{31-0} = 0xf3af8012;
32303230 }
3231 }
3232
3233 // Armv8.5-A speculation barrier
3234 def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
3235 Requires<[IsThumb2, HasSpecCtrl]>, Sched<[]> {
3236 let Inst{31-0} = 0xf3bf8f70;
3237 let Unpredictable = 0x000f2f0f;
3238 let hasSideEffects = 1;
32313239 }
32323240
32333241 class T2I_ldrex opcod, dag oops, dag iops, AddrMode am, int sz,
415415 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
416416 bool UseSjLjEH = false;
417417
418 /// Has speculation barrier
419 bool HasSpecCtrl = false;
420
418421 /// Implicitly convert an instruction to a different one if its immediates
419422 /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
420423 bool NegativeImmediates = true;
624627 bool hasDSP() const { return HasDSP; }
625628 bool useNaClTrap() const { return UseNaClTrap; }
626629 bool useSjLjEH() const { return UseSjLjEH; }
630 bool hasSpecCtrl() const { return HasSpecCtrl; }
627631 bool genLongCalls() const { return GenLongCalls; }
628632 bool genExecuteOnly() const { return GenExecuteOnly; }
629633
57195719 Mnemonic == "vmovx" || Mnemonic == "vins" ||
57205720 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
57215721 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
5722 Mnemonic == "vfmal" || Mnemonic == "vfmsl") {
5722 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
5723 Mnemonic == "sb") {
57235724 // These mnemonics are never predicable
57245725 CanAcceptPredicationCode = false;
57255726 } else if (!isThumb()) {
0 // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
1
2 it eq
3 sbeq
4
5 // CHECK: instruction 'sb' is not predicable, but condition code specified
0 // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s 2>&1 | FileCheck %s
1
2 sbeq
3
4 // CHECK: instruction 'sb' is not predicable
0 // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s
1 // RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s --check-prefix=THUMB
4 // RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
5 // RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
6
7 // Flag manipulation
8 sb
9
10 // CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
11 // THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
12
13 // NOSB: instruction requires: specctrl
14 // NOSB-NEXT: sb
0 # RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 0xbf 0xf3 0x70 0x8f
5
6 # CHECK: sb
7 # NOSB: invalid instruction encoding
8 # NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
0 # RUN: llvm-mc -triple=armv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=armv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=armv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 0x70 0xf0 0x7f 0xf5
5
6 # CHECK: sb
7 # NOSB: invalid instruction encoding
8 # NOSB-NEXT: 0x70 0xf0 0x7f 0xf5