llvm.org GIT mirror llvm / 1336daa
Use std::bitset for SubtargetFeatures Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237234 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Kuperstein 4 years ago
37 changed file(s) with 1080 addition(s) and 1033 deletion(s). Raw diff Collapse all Expand all
143143 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
144144 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
145145 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
146 uint64_t
146 FeatureBitset
147147 DeprecatedFeatureMask; // Feature bits that this is deprecated on, if any
148
148149 // A complex method to determine is a certain is deprecated or not, and return
149150 // the reason for deprecation.
150151 bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
167168 std::string &Info) const {
168169 if (ComplexDeprecationInfo)
169170 return ComplexDeprecationInfo(MI, STI, Info);
170 if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
171 if ((STI.getFeatureBits() & DeprecatedFeatureMask).any()) {
171172 // FIXME: it would be nice to include the subtarget feature here.
172173 Info = "deprecated";
173174 return true;
4141 const InstrStage *Stages; // Instruction itinerary stages
4242 const unsigned *OperandCycles; // Itinerary operand cycles
4343 const unsigned *ForwardingPaths; // Forwarding paths
44 uint64_t FeatureBits; // Feature bits for current CPU + FS
44 FeatureBitset FeatureBits; // Feature bits for current CPU + FS
4545
4646 public:
4747 void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
6666
6767 /// getFeatureBits - Return the feature bits.
6868 ///
69 uint64_t getFeatureBits() const {
69 const FeatureBitset& getFeatureBits() const {
7070 return FeatureBits;
7171 }
7272
7373 /// setFeatureBits - Set the feature bits.
7474 ///
75 void setFeatureBits(uint64_t FeatureBits_) { FeatureBits = FeatureBits_; }
75 void setFeatureBits(FeatureBitset& FeatureBits_) { FeatureBits = FeatureBits_; }
7676
7777 /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
7878 /// feature string). Recompute feature bits and scheduling model.
8383
8484 /// ToggleFeature - Toggle a feature and returns the re-computed feature
8585 /// bits. This version does not change the implied bits.
86 uint64_t ToggleFeature(uint64_t FB);
86 FeatureBitset ToggleFeature(uint64_t FB);
8787
8888 /// ToggleFeature - Toggle a feature and returns the re-computed feature
89 /// bits. This version will also change all implied bits.
90 uint64_t ToggleFeature(StringRef FS);
89 /// bits. This version does not change the implied bits.
90 FeatureBitset ToggleFeature(const FeatureBitset& FB);
91
92 /// ToggleFeature - Toggle a set of features and returns the re-computed
93 /// feature bits. This version will also change all implied bits.
94 FeatureBitset ToggleFeature(StringRef FS);
9195
9296 /// getSchedModelForCPU - Get the machine model of a CPU.
9397 ///
2020 #include "llvm/ADT/ArrayRef.h"
2121 #include "llvm/ADT/Triple.h"
2222 #include "llvm/Support/DataTypes.h"
23 #include
2324
2425 namespace llvm {
2526 class raw_ostream;
2627 class StringRef;
28
29 // A container class for subtarget features.
30 // This is convenient because std::bitset does not have a constructor
31 // with an initializer list of set bits.
32 const unsigned MAX_SUBTARGET_FEATURES = 64;
33 class FeatureBitset : public std::bitset {
34 public:
35 // Cannot inherit constructors because it's not supported by VC++..
36 FeatureBitset() : bitset() {}
37
38 FeatureBitset(const bitset& B) : bitset(B) {}
39
40 FeatureBitset(std::initializer_list Init) : bitset() {
41 for (auto I = Init.begin() , E = Init.end(); I != E; ++I)
42 set(*I);
43 }
44 };
2745
2846 //===----------------------------------------------------------------------===//
2947 ///
3351 struct SubtargetFeatureKV {
3452 const char *Key; // K-V key string
3553 const char *Desc; // Help descriptor
36 uint64_t Value; // K-V integer value
37 uint64_t Implies; // K-V bit mask
54 FeatureBitset Value; // K-V integer value
55 FeatureBitset Implies; // K-V bit mask
3856
3957 // Compare routine for std::lower_bound
4058 bool operator<(StringRef S) const {
8199
82100 /// ToggleFeature - Toggle a feature and returns the newly updated feature
83101 /// bits.
84 uint64_t ToggleFeature(uint64_t Bits, StringRef String,
102 FeatureBitset ToggleFeature(FeatureBitset Bits, StringRef String,
85103 ArrayRef FeatureTable);
86104
87105 /// Get feature bits of a CPU.
88 uint64_t getFeatureBits(StringRef CPU,
106 FeatureBitset getFeatureBits(StringRef CPU,
89107 ArrayRef CPUTable,
90108 ArrayRef FeatureTable);
91109
6262
6363 /// ToggleFeature - Toggle a feature and returns the re-computed feature
6464 /// bits. This version does not change the implied bits.
65 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
65 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
66 FeatureBits.flip(FB);
67 return FeatureBits;
68 }
69
70 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
6671 FeatureBits ^= FB;
6772 return FeatureBits;
6873 }
6974
7075 /// ToggleFeature - Toggle a feature and returns the re-computed feature
7176 /// bits. This version will also change all implied bits.
72 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
77 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
7378 SubtargetFeatures Features;
7479 FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
7580 return FeatureBits;
150150 /// feature, set it.
151151 ///
152152 static
153 void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry,
153 void SetImpliedBits(FeatureBitset &Bits, const SubtargetFeatureKV *FeatureEntry,
154154 ArrayRef FeatureTable) {
155155 for (auto &FE : FeatureTable) {
156156 if (FeatureEntry->Value == FE.Value) continue;
157157
158 if (FeatureEntry->Implies & FE.Value) {
158 if ((FeatureEntry->Implies & FE.Value).any()) {
159159 Bits |= FE.Value;
160160 SetImpliedBits(Bits, &FE, FeatureTable);
161161 }
166166 /// feature, clear it.
167167 ///
168168 static
169 void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry,
169 void ClearImpliedBits(FeatureBitset &Bits,
170 const SubtargetFeatureKV *FeatureEntry,
170171 ArrayRef FeatureTable) {
171172 for (auto &FE : FeatureTable) {
172173 if (FeatureEntry->Value == FE.Value) continue;
173174
174 if (FE.Implies & FeatureEntry->Value) {
175 if ((FE.Implies & FeatureEntry->Value).any()) {
175176 Bits &= ~FE.Value;
176177 ClearImpliedBits(Bits, &FE, FeatureTable);
177178 }
180181
181182 /// ToggleFeature - Toggle a feature and returns the newly updated feature
182183 /// bits.
183 uint64_t
184 SubtargetFeatures::ToggleFeature(uint64_t Bits, StringRef Feature,
184 FeatureBitset
185 SubtargetFeatures::ToggleFeature(FeatureBitset Bits, StringRef Feature,
185186 ArrayRef FeatureTable) {
186187
187188 // Find feature in table.
191192 if (FeatureEntry) {
192193 if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
193194 Bits &= ~FeatureEntry->Value;
194
195195 // For each feature that implies this, clear it.
196196 ClearImpliedBits(Bits, FeatureEntry, FeatureTable);
197197 } else {
212212
213213 /// getFeatureBits - Get feature bits a CPU.
214214 ///
215 uint64_t
215 FeatureBitset
216216 SubtargetFeatures::getFeatureBits(StringRef CPU,
217217 ArrayRef CPUTable,
218218 ArrayRef FeatureTable) {
219219
220220 if (CPUTable.empty() || FeatureTable.empty())
221 return 0;
221 return FeatureBitset();
222222
223223 #ifndef NDEBUG
224224 for (size_t i = 1, e = CPUTable.size(); i != e; ++i) {
230230 "CPU features table is not sorted");
231231 }
232232 #endif
233 uint64_t Bits = 0; // Resulting bits
233 // Resulting bits
234 FeatureBitset Bits;
234235
235236 // Check if help is needed
236237 if (CPU == "help")
247248
248249 // Set the feature implied by this CPU feature, if any.
249250 for (auto &FE : FeatureTable) {
250 if (CPUEntry->Value & FE.Value)
251 if ((CPUEntry->Value & FE.Value).any())
251252 SetImpliedBits(Bits, &FE, FeatureTable);
252253 }
253254 } else {
1717
1818 using namespace llvm;
1919
20 StringRef AArch64NamedImmMapper::toString(uint32_t Value, uint64_t FeatureBits,
21 bool &Valid) const {
20 StringRef AArch64NamedImmMapper::toString(uint32_t Value,
21 const FeatureBitset& FeatureBits, bool &Valid) const {
2222 for (unsigned i = 0; i < NumMappings; ++i) {
2323 if (Mappings[i].isValueEqual(Value, FeatureBits)) {
2424 Valid = true;
3030 return StringRef();
3131 }
3232
33 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, uint64_t FeatureBits,
34 bool &Valid) const {
33 uint32_t AArch64NamedImmMapper::fromString(StringRef Name,
34 const FeatureBitset& FeatureBits, bool &Valid) const {
3535 std::string LowerCaseName = Name.lower();
3636 for (unsigned i = 0; i < NumMappings; ++i) {
3737 if (Mappings[i].isNameEqual(LowerCaseName, FeatureBits)) {
4949 }
5050
5151 const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
52 {"s1e1r", S1E1R, 0},
53 {"s1e2r", S1E2R, 0},
54 {"s1e3r", S1E3R, 0},
55 {"s1e1w", S1E1W, 0},
56 {"s1e2w", S1E2W, 0},
57 {"s1e3w", S1E3W, 0},
58 {"s1e0r", S1E0R, 0},
59 {"s1e0w", S1E0W, 0},
60 {"s12e1r", S12E1R, 0},
61 {"s12e1w", S12E1W, 0},
62 {"s12e0r", S12E0R, 0},
63 {"s12e0w", S12E0W, 0},
52 {"s1e1r", S1E1R, {}},
53 {"s1e2r", S1E2R, {}},
54 {"s1e3r", S1E3R, {}},
55 {"s1e1w", S1E1W, {}},
56 {"s1e2w", S1E2W, {}},
57 {"s1e3w", S1E3W, {}},
58 {"s1e0r", S1E0R, {}},
59 {"s1e0w", S1E0W, {}},
60 {"s12e1r", S12E1R, {}},
61 {"s12e1w", S12E1W, {}},
62 {"s12e0r", S12E0R, {}},
63 {"s12e0w", S12E0W, {}},
6464 };
6565
6666 AArch64AT::ATMapper::ATMapper()
6767 : AArch64NamedImmMapper(ATMappings, 0) {}
6868
6969 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
70 {"oshld", OSHLD, 0},
71 {"oshst", OSHST, 0},
72 {"osh", OSH, 0},
73 {"nshld", NSHLD, 0},
74 {"nshst", NSHST, 0},
75 {"nsh", NSH, 0},
76 {"ishld", ISHLD, 0},
77 {"ishst", ISHST, 0},
78 {"ish", ISH, 0},
79 {"ld", LD, 0},
80 {"st", ST, 0},
81 {"sy", SY, 0}
70 {"oshld", OSHLD, {}},
71 {"oshst", OSHST, {}},
72 {"osh", OSH, {}},
73 {"nshld", NSHLD, {}},
74 {"nshst", NSHST, {}},
75 {"nsh", NSH, {}},
76 {"ishld", ISHLD, {}},
77 {"ishst", ISHST, {}},
78 {"ish", ISH, {}},
79 {"ld", LD, {}},
80 {"st", ST, {}},
81 {"sy", SY, {}}
8282 };
8383
8484 AArch64DB::DBarrierMapper::DBarrierMapper()
8585 : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
8686
8787 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
88 {"zva", ZVA, 0},
89 {"ivac", IVAC, 0},
90 {"isw", ISW, 0},
91 {"cvac", CVAC, 0},
92 {"csw", CSW, 0},
93 {"cvau", CVAU, 0},
94 {"civac", CIVAC, 0},
95 {"cisw", CISW, 0}
88 {"zva", ZVA, {}},
89 {"ivac", IVAC, {}},
90 {"isw", ISW, {}},
91 {"cvac", CVAC, {}},
92 {"csw", CSW, {}},
93 {"cvau", CVAU, {}},
94 {"civac", CIVAC, {}},
95 {"cisw", CISW, {}}
9696 };
9797
9898 AArch64DC::DCMapper::DCMapper()
9999 : AArch64NamedImmMapper(DCMappings, 0) {}
100100
101101 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
102 {"ialluis", IALLUIS, 0},
103 {"iallu", IALLU, 0},
104 {"ivau", IVAU, 0}
102 {"ialluis", IALLUIS, {}},
103 {"iallu", IALLU, {}},
104 {"ivau", IVAU, {}}
105105 };
106106
107107 AArch64IC::ICMapper::ICMapper()
108108 : AArch64NamedImmMapper(ICMappings, 0) {}
109109
110110 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
111 {"sy", SY, 0},
111 {"sy", SY, {}},
112112 };
113113
114114 AArch64ISB::ISBMapper::ISBMapper()
115115 : AArch64NamedImmMapper(ISBMappings, 16) {}
116116
117117 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
118 {"pldl1keep", PLDL1KEEP, 0},
119 {"pldl1strm", PLDL1STRM, 0},
120 {"pldl2keep", PLDL2KEEP, 0},
121 {"pldl2strm", PLDL2STRM, 0},
122 {"pldl3keep", PLDL3KEEP, 0},
123 {"pldl3strm", PLDL3STRM, 0},
124 {"plil1keep", PLIL1KEEP, 0},
125 {"plil1strm", PLIL1STRM, 0},
126 {"plil2keep", PLIL2KEEP, 0},
127 {"plil2strm", PLIL2STRM, 0},
128 {"plil3keep", PLIL3KEEP, 0},
129 {"plil3strm", PLIL3STRM, 0},
130 {"pstl1keep", PSTL1KEEP, 0},
131 {"pstl1strm", PSTL1STRM, 0},
132 {"pstl2keep", PSTL2KEEP, 0},
133 {"pstl2strm", PSTL2STRM, 0},
134 {"pstl3keep", PSTL3KEEP, 0},
135 {"pstl3strm", PSTL3STRM, 0}
118 {"pldl1keep", PLDL1KEEP, {}},
119 {"pldl1strm", PLDL1STRM, {}},
120 {"pldl2keep", PLDL2KEEP, {}},
121 {"pldl2strm", PLDL2STRM, {}},
122 {"pldl3keep", PLDL3KEEP, {}},
123 {"pldl3strm", PLDL3STRM, {}},
124 {"plil1keep", PLIL1KEEP, {}},
125 {"plil1strm", PLIL1STRM, {}},
126 {"plil2keep", PLIL2KEEP, {}},
127 {"plil2strm", PLIL2STRM, {}},
128 {"plil3keep", PLIL3KEEP, {}},
129 {"plil3strm", PLIL3STRM, {}},
130 {"pstl1keep", PSTL1KEEP, {}},
131 {"pstl1strm", PSTL1STRM, {}},
132 {"pstl2keep", PSTL2KEEP, {}},
133 {"pstl2strm", PSTL2STRM, {}},
134 {"pstl3keep", PSTL3KEEP, {}},
135 {"pstl3strm", PSTL3STRM, {}}
136136 };
137137
138138 AArch64PRFM::PRFMMapper::PRFMMapper()
139139 : AArch64NamedImmMapper(PRFMMappings, 32) {}
140140
141141 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
142 {"spsel", SPSel, 0},
143 {"daifset", DAIFSet, 0},
144 {"daifclr", DAIFClr, 0},
142 {"spsel", SPSel, {}},
143 {"daifset", DAIFSet, {}},
144 {"daifclr", DAIFClr, {}},
145145
146146 // v8.1a "Privileged Access Never" extension-specific PStates
147 {"pan", PAN, AArch64::HasV8_1aOps},
147 {"pan", PAN, {AArch64::HasV8_1aOps}},
148148 };
149149
150150 AArch64PState::PStateMapper::PStateMapper()
151151 : AArch64NamedImmMapper(PStateMappings, 0) {}
152152
153153 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
154 {"mdccsr_el0", MDCCSR_EL0, 0},
155 {"dbgdtrrx_el0", DBGDTRRX_EL0, 0},
156 {"mdrar_el1", MDRAR_EL1, 0},
157 {"oslsr_el1", OSLSR_EL1, 0},
158 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, 0},
159 {"pmceid0_el0", PMCEID0_EL0, 0},
160 {"pmceid1_el0", PMCEID1_EL0, 0},
161 {"midr_el1", MIDR_EL1, 0},
162 {"ccsidr_el1", CCSIDR_EL1, 0},
163 {"clidr_el1", CLIDR_EL1, 0},
164 {"ctr_el0", CTR_EL0, 0},
165 {"mpidr_el1", MPIDR_EL1, 0},
166 {"revidr_el1", REVIDR_EL1, 0},
167 {"aidr_el1", AIDR_EL1, 0},
168 {"dczid_el0", DCZID_EL0, 0},
169 {"id_pfr0_el1", ID_PFR0_EL1, 0},
170 {"id_pfr1_el1", ID_PFR1_EL1, 0},
171 {"id_dfr0_el1", ID_DFR0_EL1, 0},
172 {"id_afr0_el1", ID_AFR0_EL1, 0},
173 {"id_mmfr0_el1", ID_MMFR0_EL1, 0},
174 {"id_mmfr1_el1", ID_MMFR1_EL1, 0},
175 {"id_mmfr2_el1", ID_MMFR2_EL1, 0},
176 {"id_mmfr3_el1", ID_MMFR3_EL1, 0},
177 {"id_isar0_el1", ID_ISAR0_EL1, 0},
178 {"id_isar1_el1", ID_ISAR1_EL1, 0},
179 {"id_isar2_el1", ID_ISAR2_EL1, 0},
180 {"id_isar3_el1", ID_ISAR3_EL1, 0},
181 {"id_isar4_el1", ID_ISAR4_EL1, 0},
182 {"id_isar5_el1", ID_ISAR5_EL1, 0},
183 {"id_aa64pfr0_el1", ID_A64PFR0_EL1, 0},
184 {"id_aa64pfr1_el1", ID_A64PFR1_EL1, 0},
185 {"id_aa64dfr0_el1", ID_A64DFR0_EL1, 0},
186 {"id_aa64dfr1_el1", ID_A64DFR1_EL1, 0},
187 {"id_aa64afr0_el1", ID_A64AFR0_EL1, 0},
188 {"id_aa64afr1_el1", ID_A64AFR1_EL1, 0},
189 {"id_aa64isar0_el1", ID_A64ISAR0_EL1, 0},
190 {"id_aa64isar1_el1", ID_A64ISAR1_EL1, 0},
191 {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, 0},
192 {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, 0},
193 {"mvfr0_el1", MVFR0_EL1, 0},
194 {"mvfr1_el1", MVFR1_EL1, 0},
195 {"mvfr2_el1", MVFR2_EL1, 0},
196 {"rvbar_el1", RVBAR_EL1, 0},
197 {"rvbar_el2", RVBAR_EL2, 0},
198 {"rvbar_el3", RVBAR_EL3, 0},
199 {"isr_el1", ISR_EL1, 0},
200 {"cntpct_el0", CNTPCT_EL0, 0},
201 {"cntvct_el0", CNTVCT_EL0, 0},
154 {"mdccsr_el0", MDCCSR_EL0, {}},
155 {"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
156 {"mdrar_el1", MDRAR_EL1, {}},
157 {"oslsr_el1", OSLSR_EL1, {}},
158 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1, {}},
159 {"pmceid0_el0", PMCEID0_EL0, {}},
160 {"pmceid1_el0", PMCEID1_EL0, {}},
161 {"midr_el1", MIDR_EL1, {}},
162 {"ccsidr_el1", CCSIDR_EL1, {}},
163 {"clidr_el1", CLIDR_EL1, {}},
164 {"ctr_el0", CTR_EL0, {}},
165 {"mpidr_el1", MPIDR_EL1, {}},
166 {"revidr_el1", REVIDR_EL1, {}},
167 {"aidr_el1", AIDR_EL1, {}},
168 {"dczid_el0", DCZID_EL0, {}},
169 {"id_pfr0_el1", ID_PFR0_EL1, {}},
170 {"id_pfr1_el1", ID_PFR1_EL1, {}},
171 {"id_dfr0_el1", ID_DFR0_EL1, {}},
172 {"id_afr0_el1", ID_AFR0_EL1, {}},
173 {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
174 {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
175 {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
176 {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
177 {"id_isar0_el1", ID_ISAR0_EL1, {}},
178 {"id_isar1_el1", ID_ISAR1_EL1, {}},
179 {"id_isar2_el1", ID_ISAR2_EL1, {}},
180 {"id_isar3_el1", ID_ISAR3_EL1, {}},
181 {"id_isar4_el1", ID_ISAR4_EL1, {}},
182 {"id_isar5_el1", ID_ISAR5_EL1, {}},
183 {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
184 {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},
185 {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}},
186 {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}},
187 {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}},
188 {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}},
189 {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}},
190 {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
191 {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
192 {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
193 {"mvfr0_el1", MVFR0_EL1, {}},
194 {"mvfr1_el1", MVFR1_EL1, {}},
195 {"mvfr2_el1", MVFR2_EL1, {}},
196 {"rvbar_el1", RVBAR_EL1, {}},
197 {"rvbar_el2", RVBAR_EL2, {}},
198 {"rvbar_el3", RVBAR_EL3, {}},
199 {"isr_el1", ISR_EL1, {}},
200 {"cntpct_el0", CNTPCT_EL0, {}},
201 {"cntvct_el0", CNTVCT_EL0, {}},
202202
203203 // Trace registers
204 {"trcstatr", TRCSTATR, 0},
205 {"trcidr8", TRCIDR8, 0},
206 {"trcidr9", TRCIDR9, 0},
207 {"trcidr10", TRCIDR10, 0},
208 {"trcidr11", TRCIDR11, 0},
209 {"trcidr12", TRCIDR12, 0},
210 {"trcidr13", TRCIDR13, 0},
211 {"trcidr0", TRCIDR0, 0},
212 {"trcidr1", TRCIDR1, 0},
213 {"trcidr2", TRCIDR2, 0},
214 {"trcidr3", TRCIDR3, 0},
215 {"trcidr4", TRCIDR4, 0},
216 {"trcidr5", TRCIDR5, 0},
217 {"trcidr6", TRCIDR6, 0},
218 {"trcidr7", TRCIDR7, 0},
219 {"trcoslsr", TRCOSLSR, 0},
220 {"trcpdsr", TRCPDSR, 0},
221 {"trcdevaff0", TRCDEVAFF0, 0},
222 {"trcdevaff1", TRCDEVAFF1, 0},
223 {"trclsr", TRCLSR, 0},
224 {"trcauthstatus", TRCAUTHSTATUS, 0},
225 {"trcdevarch", TRCDEVARCH, 0},
226 {"trcdevid", TRCDEVID, 0},
227 {"trcdevtype", TRCDEVTYPE, 0},
228 {"trcpidr4", TRCPIDR4, 0},
229 {"trcpidr5", TRCPIDR5, 0},
230 {"trcpidr6", TRCPIDR6, 0},
231 {"trcpidr7", TRCPIDR7, 0},
232 {"trcpidr0", TRCPIDR0, 0},
233 {"trcpidr1", TRCPIDR1, 0},
234 {"trcpidr2", TRCPIDR2, 0},
235 {"trcpidr3", TRCPIDR3, 0},
236 {"trccidr0", TRCCIDR0, 0},
237 {"trccidr1", TRCCIDR1, 0},
238 {"trccidr2", TRCCIDR2, 0},
239 {"trccidr3", TRCCIDR3, 0},
204 {"trcstatr", TRCSTATR, {}},
205 {"trcidr8", TRCIDR8, {}},
206 {"trcidr9", TRCIDR9, {}},
207 {"trcidr10", TRCIDR10, {}},
208 {"trcidr11", TRCIDR11, {}},
209 {"trcidr12", TRCIDR12, {}},
210 {"trcidr13", TRCIDR13, {}},
211 {"trcidr0", TRCIDR0, {}},
212 {"trcidr1", TRCIDR1, {}},
213 {"trcidr2", TRCIDR2, {}},
214 {"trcidr3", TRCIDR3, {}},
215 {"trcidr4", TRCIDR4, {}},
216 {"trcidr5", TRCIDR5, {}},
217 {"trcidr6", TRCIDR6, {}},
218 {"trcidr7", TRCIDR7, {}},
219 {"trcoslsr", TRCOSLSR, {}},
220 {"trcpdsr", TRCPDSR, {}},
221 {"trcdevaff0", TRCDEVAFF0, {}},
222 {"trcdevaff1", TRCDEVAFF1, {}},
223 {"trclsr", TRCLSR, {}},
224 {"trcauthstatus", TRCAUTHSTATUS, {}},
225 {"trcdevarch", TRCDEVARCH, {}},
226 {"trcdevid", TRCDEVID, {}},
227 {"trcdevtype", TRCDEVTYPE, {}},
228 {"trcpidr4", TRCPIDR4, {}},
229 {"trcpidr5", TRCPIDR5, {}},
230 {"trcpidr6", TRCPIDR6, {}},
231 {"trcpidr7", TRCPIDR7, {}},
232 {"trcpidr0", TRCPIDR0, {}},
233 {"trcpidr1", TRCPIDR1, {}},
234 {"trcpidr2", TRCPIDR2, {}},
235 {"trcpidr3", TRCPIDR3, {}},
236 {"trccidr0", TRCCIDR0, {}},
237 {"trccidr1", TRCCIDR1, {}},
238 {"trccidr2", TRCCIDR2, {}},
239 {"trccidr3", TRCCIDR3, {}},
240240
241241 // GICv3 registers
242 {"icc_iar1_el1", ICC_IAR1_EL1, 0},
243 {"icc_iar0_el1", ICC_IAR0_EL1, 0},
244 {"icc_hppir1_el1", ICC_HPPIR1_EL1, 0},
245 {"icc_hppir0_el1", ICC_HPPIR0_EL1, 0},
246 {"icc_rpr_el1", ICC_RPR_EL1, 0},
247 {"ich_vtr_el2", ICH_VTR_EL2, 0},
248 {"ich_eisr_el2", ICH_EISR_EL2, 0},
249 {"ich_elsr_el2", ICH_ELSR_EL2, 0},
242 {"icc_iar1_el1", ICC_IAR1_EL1, {}},
243 {"icc_iar0_el1", ICC_IAR0_EL1, {}},
244 {"icc_hppir1_el1", ICC_HPPIR1_EL1, {}},
245 {"icc_hppir0_el1", ICC_HPPIR0_EL1, {}},
246 {"icc_rpr_el1", ICC_RPR_EL1, {}},
247 {"ich_vtr_el2", ICH_VTR_EL2, {}},
248 {"ich_eisr_el2", ICH_EISR_EL2, {}},
249 {"ich_elsr_el2", ICH_ELSR_EL2, {}},
250250
251251 // v8.1a "Limited Ordering Regions" extension-specific system registers
252 {"lorid_el1", LORID_EL1, AArch64::HasV8_1aOps},
252 {"lorid_el1", LORID_EL1, {AArch64::HasV8_1aOps}},
253253 };
254254
255255 AArch64SysReg::MRSMapper::MRSMapper() {
258258 }
259259
260260 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
261 {"dbgdtrtx_el0", DBGDTRTX_EL0, 0},
262 {"oslar_el1", OSLAR_EL1, 0},
263 {"pmswinc_el0", PMSWINC_EL0, 0},
261 {"dbgdtrtx_el0", DBGDTRTX_EL0, {}},
262 {"oslar_el1", OSLAR_EL1, {}},
263 {"pmswinc_el0", PMSWINC_EL0, {}},
264264
265265 // Trace registers
266 {"trcoslar", TRCOSLAR, 0},
267 {"trclar", TRCLAR, 0},
266 {"trcoslar", TRCOSLAR, {}},
267 {"trclar", TRCLAR, {}},
268268
269269 // GICv3 registers
270 {"icc_eoir1_el1", ICC_EOIR1_EL1, 0},
271 {"icc_eoir0_el1", ICC_EOIR0_EL1, 0},
272 {"icc_dir_el1", ICC_DIR_EL1, 0},
273 {"icc_sgi1r_el1", ICC_SGI1R_EL1, 0},
274 {"icc_asgi1r_el1", ICC_ASGI1R_EL1, 0},
275 {"icc_sgi0r_el1", ICC_SGI0R_EL1, 0},
270 {"icc_eoir1_el1", ICC_EOIR1_EL1, {}},
271 {"icc_eoir0_el1", ICC_EOIR0_EL1, {}},
272 {"icc_dir_el1", ICC_DIR_EL1, {}},
273 {"icc_sgi1r_el1", ICC_SGI1R_EL1, {}},
274 {"icc_asgi1r_el1", ICC_ASGI1R_EL1, {}},
275 {"icc_sgi0r_el1", ICC_SGI0R_EL1, {}},
276276
277277 // v8.1a "Privileged Access Never" extension-specific system registers
278 {"pan", PAN, AArch64::HasV8_1aOps},
278 {"pan", PAN, {AArch64::HasV8_1aOps}},
279279 };
280280
281281 AArch64SysReg::MSRMapper::MSRMapper() {
285285
286286
287287 const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
288 {"osdtrrx_el1", OSDTRRX_EL1, 0},
289 {"osdtrtx_el1", OSDTRTX_EL1, 0},
290 {"teecr32_el1", TEECR32_EL1, 0},
291 {"mdccint_el1", MDCCINT_EL1, 0},
292 {"mdscr_el1", MDSCR_EL1, 0},
293 {"dbgdtr_el0", DBGDTR_EL0, 0},
294 {"oseccr_el1", OSECCR_EL1, 0},
295 {"dbgvcr32_el2", DBGVCR32_EL2, 0},
296 {"dbgbvr0_el1", DBGBVR0_EL1, 0},
297 {"dbgbvr1_el1", DBGBVR1_EL1, 0},
298 {"dbgbvr2_el1", DBGBVR2_EL1, 0},
299 {"dbgbvr3_el1", DBGBVR3_EL1, 0},
300 {"dbgbvr4_el1", DBGBVR4_EL1, 0},
301 {"dbgbvr5_el1", DBGBVR5_EL1, 0},
302 {"dbgbvr6_el1", DBGBVR6_EL1, 0},
303 {"dbgbvr7_el1", DBGBVR7_EL1, 0},
304 {"dbgbvr8_el1", DBGBVR8_EL1, 0},
305 {"dbgbvr9_el1", DBGBVR9_EL1, 0},
306 {"dbgbvr10_el1", DBGBVR10_EL1, 0},
307 {"dbgbvr11_el1", DBGBVR11_EL1, 0},
308 {"dbgbvr12_el1", DBGBVR12_EL1, 0},
309 {"dbgbvr13_el1", DBGBVR13_EL1, 0},
310 {"dbgbvr14_el1", DBGBVR14_EL1, 0},
311 {"dbgbvr15_el1", DBGBVR15_EL1, 0},
312 {"dbgbcr0_el1", DBGBCR0_EL1, 0},
313 {"dbgbcr1_el1", DBGBCR1_EL1, 0},
314 {"dbgbcr2_el1", DBGBCR2_EL1, 0},
315 {"dbgbcr3_el1", DBGBCR3_EL1, 0},
316 {"dbgbcr4_el1", DBGBCR4_EL1, 0},
317 {"dbgbcr5_el1", DBGBCR5_EL1, 0},
318 {"dbgbcr6_el1", DBGBCR6_EL1, 0},
319 {"dbgbcr7_el1", DBGBCR7_EL1, 0},
320 {"dbgbcr8_el1", DBGBCR8_EL1, 0},
321 {"dbgbcr9_el1", DBGBCR9_EL1, 0},
322 {"dbgbcr10_el1", DBGBCR10_EL1, 0},
323 {"dbgbcr11_el1", DBGBCR11_EL1, 0},
324 {"dbgbcr12_el1", DBGBCR12_EL1, 0},
325 {"dbgbcr13_el1", DBGBCR13_EL1, 0},
326 {"dbgbcr14_el1", DBGBCR14_EL1, 0},
327 {"dbgbcr15_el1", DBGBCR15_EL1, 0},
328 {"dbgwvr0_el1", DBGWVR0_EL1, 0},
329 {"dbgwvr1_el1", DBGWVR1_EL1, 0},
330 {"dbgwvr2_el1", DBGWVR2_EL1, 0},
331 {"dbgwvr3_el1", DBGWVR3_EL1, 0},
332 {"dbgwvr4_el1", DBGWVR4_EL1, 0},
333 {"dbgwvr5_el1", DBGWVR5_EL1, 0},
334 {"dbgwvr6_el1", DBGWVR6_EL1, 0},
335 {"dbgwvr7_el1", DBGWVR7_EL1, 0},
336 {"dbgwvr8_el1", DBGWVR8_EL1, 0},
337 {"dbgwvr9_el1", DBGWVR9_EL1, 0},
338 {"dbgwvr10_el1", DBGWVR10_EL1, 0},
339 {"dbgwvr11_el1", DBGWVR11_EL1, 0},
340 {"dbgwvr12_el1", DBGWVR12_EL1, 0},
341 {"dbgwvr13_el1", DBGWVR13_EL1, 0},
342 {"dbgwvr14_el1", DBGWVR14_EL1, 0},
343 {"dbgwvr15_el1", DBGWVR15_EL1, 0},
344 {"dbgwcr0_el1", DBGWCR0_EL1, 0},
345 {"dbgwcr1_el1", DBGWCR1_EL1, 0},
346 {"dbgwcr2_el1", DBGWCR2_EL1, 0},
347 {"dbgwcr3_el1", DBGWCR3_EL1, 0},
348 {"dbgwcr4_el1", DBGWCR4_EL1, 0},
349 {"dbgwcr5_el1", DBGWCR5_EL1, 0},
350 {"dbgwcr6_el1", DBGWCR6_EL1, 0},
351 {"dbgwcr7_el1", DBGWCR7_EL1, 0},
352 {"dbgwcr8_el1", DBGWCR8_EL1, 0},
353 {"dbgwcr9_el1", DBGWCR9_EL1, 0},
354 {"dbgwcr10_el1", DBGWCR10_EL1, 0},
355 {"dbgwcr11_el1", DBGWCR11_EL1, 0},
356 {"dbgwcr12_el1", DBGWCR12_EL1, 0},
357 {"dbgwcr13_el1", DBGWCR13_EL1, 0},
358 {"dbgwcr14_el1", DBGWCR14_EL1, 0},
359 {"dbgwcr15_el1", DBGWCR15_EL1, 0},
360 {"teehbr32_el1", TEEHBR32_EL1, 0},
361 {"osdlr_el1", OSDLR_EL1, 0},
362 {"dbgprcr_el1", DBGPRCR_EL1, 0},
363 {"dbgclaimset_el1", DBGCLAIMSET_EL1, 0},
364 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, 0},
365 {"csselr_el1", CSSELR_EL1, 0},
366 {"vpidr_el2", VPIDR_EL2, 0},
367 {"vmpidr_el2", VMPIDR_EL2, 0},
368 {"sctlr_el1", SCTLR_EL1, 0},
369 {"sctlr_el2", SCTLR_EL2, 0},
370 {"sctlr_el3", SCTLR_EL3, 0},
371 {"actlr_el1", ACTLR_EL1, 0},
372 {"actlr_el2", ACTLR_EL2, 0},
373 {"actlr_el3", ACTLR_EL3, 0},
374 {"cpacr_el1", CPACR_EL1, 0},
375 {"hcr_el2", HCR_EL2, 0},
376 {"scr_el3", SCR_EL3, 0},
377 {"mdcr_el2", MDCR_EL2, 0},
378 {"sder32_el3", SDER32_EL3, 0},
379 {"cptr_el2", CPTR_EL2, 0},
380 {"cptr_el3", CPTR_EL3, 0},
381 {"hstr_el2", HSTR_EL2, 0},
382 {"hacr_el2", HACR_EL2, 0},
383 {"mdcr_el3", MDCR_EL3, 0},
384 {"ttbr0_el1", TTBR0_EL1, 0},
385 {"ttbr0_el2", TTBR0_EL2, 0},
386 {"ttbr0_el3", TTBR0_EL3, 0},
387 {"ttbr1_el1", TTBR1_EL1, 0},
388 {"tcr_el1", TCR_EL1, 0},
389 {"tcr_el2", TCR_EL2, 0},
390 {"tcr_el3", TCR_EL3, 0},
391 {"vttbr_el2", VTTBR_EL2, 0},
392 {"vtcr_el2", VTCR_EL2, 0},
393 {"dacr32_el2", DACR32_EL2, 0},
394 {"spsr_el1", SPSR_EL1, 0},
395 {"spsr_el2", SPSR_EL2, 0},
396 {"spsr_el3", SPSR_EL3, 0},
397 {"elr_el1", ELR_EL1, 0},
398 {"elr_el2", ELR_EL2, 0},
399 {"elr_el3", ELR_EL3, 0},
400 {"sp_el0", SP_EL0, 0},
401 {"sp_el1", SP_EL1, 0},
402 {"sp_el2", SP_EL2, 0},
403 {"spsel", SPSel, 0},
404 {"nzcv", NZCV, 0},
405 {"daif", DAIF, 0},
406 {"currentel", CurrentEL, 0},
407 {"spsr_irq", SPSR_irq, 0},
408 {"spsr_abt", SPSR_abt, 0},
409 {"spsr_und", SPSR_und, 0},
410 {"spsr_fiq", SPSR_fiq, 0},
411 {"fpcr", FPCR, 0},
412 {"fpsr", FPSR, 0},
413 {"dspsr_el0", DSPSR_EL0, 0},
414 {"dlr_el0", DLR_EL0, 0},
415 {"ifsr32_el2", IFSR32_EL2, 0},
416 {"afsr0_el1", AFSR0_EL1, 0},
417 {"afsr0_el2", AFSR0_EL2, 0},
418 {"afsr0_el3", AFSR0_EL3, 0},
419 {"afsr1_el1", AFSR1_EL1, 0},
420 {"afsr1_el2", AFSR1_EL2, 0},
421 {"afsr1_el3", AFSR1_EL3, 0},
422 {"esr_el1", ESR_EL1, 0},
423 {"esr_el2", ESR_EL2, 0},
424 {"esr_el3", ESR_EL3, 0},
425 {"fpexc32_el2", FPEXC32_EL2, 0},
426 {"far_el1", FAR_EL1, 0},
427 {"far_el2", FAR_EL2, 0},
428 {"far_el3", FAR_EL3, 0},
429 {"hpfar_el2", HPFAR_EL2, 0},
430 {"par_el1", PAR_EL1, 0},
431 {"pmcr_el0", PMCR_EL0, 0},
432 {"pmcntenset_el0", PMCNTENSET_EL0, 0},
433 {"pmcntenclr_el0", PMCNTENCLR_EL0, 0},
434 {"pmovsclr_el0", PMOVSCLR_EL0, 0},
435 {"pmselr_el0", PMSELR_EL0, 0},
436 {"pmccntr_el0", PMCCNTR_EL0, 0},
437 {"pmxevtyper_el0", PMXEVTYPER_EL0, 0},
438 {"pmxevcntr_el0", PMXEVCNTR_EL0, 0},
439 {"pmuserenr_el0", PMUSERENR_EL0, 0},
440 {"pmintenset_el1", PMINTENSET_EL1, 0},
441 {"pmintenclr_el1", PMINTENCLR_EL1, 0},
442 {"pmovsset_el0", PMOVSSET_EL0, 0},
443 {"mair_el1", MAIR_EL1, 0},
444 {"mair_el2", MAIR_EL2, 0},
445 {"mair_el3", MAIR_EL3, 0},
446 {"amair_el1", AMAIR_EL1, 0},
447 {"amair_el2", AMAIR_EL2, 0},
448 {"amair_el3", AMAIR_EL3, 0},
449 {"vbar_el1", VBAR_EL1, 0},
450 {"vbar_el2", VBAR_EL2, 0},
451 {"vbar_el3", VBAR_EL3, 0},
452 {"rmr_el1", RMR_EL1, 0},
453 {"rmr_el2", RMR_EL2, 0},
454 {"rmr_el3", RMR_EL3, 0},
455 {"contextidr_el1", CONTEXTIDR_EL1, 0},
456 {"tpidr_el0", TPIDR_EL0, 0},
457 {"tpidr_el2", TPIDR_EL2, 0},
458 {"tpidr_el3", TPIDR_EL3, 0},
459 {"tpidrro_el0", TPIDRRO_EL0, 0},
460 {"tpidr_el1", TPIDR_EL1, 0},
461 {"cntfrq_el0", CNTFRQ_EL0, 0},
462 {"cntvoff_el2", CNTVOFF_EL2, 0},
463 {"cntkctl_el1", CNTKCTL_EL1, 0},
464 {"cnthctl_el2", CNTHCTL_EL2, 0},
465 {"cntp_tval_el0", CNTP_TVAL_EL0, 0},
466 {"cnthp_tval_el2", CNTHP_TVAL_EL2, 0},
467 {"cntps_tval_el1", CNTPS_TVAL_EL1, 0},
468 {"cntp_ctl_el0", CNTP_CTL_EL0, 0},
469 {"cnthp_ctl_el2", CNTHP_CTL_EL2, 0},
470 {"cntps_ctl_el1", CNTPS_CTL_EL1, 0},
471 {"cntp_cval_el0", CNTP_CVAL_EL0, 0},
472 {"cnthp_cval_el2", CNTHP_CVAL_EL2, 0},
473 {"cntps_cval_el1", CNTPS_CVAL_EL1, 0},
474 {"cntv_tval_el0", CNTV_TVAL_EL0, 0},
475 {"cntv_ctl_el0", CNTV_CTL_EL0, 0},
476 {"cntv_cval_el0", CNTV_CVAL_EL0, 0},
477 {"pmevcntr0_el0", PMEVCNTR0_EL0, 0},
478 {"pmevcntr1_el0", PMEVCNTR1_EL0, 0},
479 {"pmevcntr2_el0", PMEVCNTR2_EL0, 0},
480 {"pmevcntr3_el0", PMEVCNTR3_EL0, 0},
481 {"pmevcntr4_el0", PMEVCNTR4_EL0, 0},
482 {"pmevcntr5_el0", PMEVCNTR5_EL0, 0},
483 {"pmevcntr6_el0", PMEVCNTR6_EL0, 0},
484 {"pmevcntr7_el0", PMEVCNTR7_EL0, 0},
485 {"pmevcntr8_el0", PMEVCNTR8_EL0, 0},
486 {"pmevcntr9_el0", PMEVCNTR9_EL0, 0},
487 {"pmevcntr10_el0", PMEVCNTR10_EL0, 0},
488 {"pmevcntr11_el0", PMEVCNTR11_EL0, 0},
489 {"pmevcntr12_el0", PMEVCNTR12_EL0, 0},
490 {"pmevcntr13_el0", PMEVCNTR13_EL0, 0},
491 {"pmevcntr14_el0", PMEVCNTR14_EL0, 0},
492 {"pmevcntr15_el0", PMEVCNTR15_EL0, 0},
493 {"pmevcntr16_el0", PMEVCNTR16_EL0, 0},
494 {"pmevcntr17_el0", PMEVCNTR17_EL0, 0},
495 {"pmevcntr18_el0", PMEVCNTR18_EL0, 0},
496 {"pmevcntr19_el0", PMEVCNTR19_EL0, 0},
497 {"pmevcntr20_el0", PMEVCNTR20_EL0, 0},
498 {"pmevcntr21_el0", PMEVCNTR21_EL0, 0},
499 {"pmevcntr22_el0", PMEVCNTR22_EL0, 0},
500 {"pmevcntr23_el0", PMEVCNTR23_EL0, 0},
501 {"pmevcntr24_el0", PMEVCNTR24_EL0, 0},
502 {"pmevcntr25_el0", PMEVCNTR25_EL0, 0},
503 {"pmevcntr26_el0", PMEVCNTR26_EL0, 0},
504 {"pmevcntr27_el0", PMEVCNTR27_EL0, 0},
505 {"pmevcntr28_el0", PMEVCNTR28_EL0, 0},
506 {"pmevcntr29_el0", PMEVCNTR29_EL0, 0},
507 {"pmevcntr30_el0", PMEVCNTR30_EL0, 0},
508 {"pmccfiltr_el0", PMCCFILTR_EL0, 0},
509 {"pmevtyper0_el0", PMEVTYPER0_EL0, 0},
510 {"pmevtyper1_el0", PMEVTYPER1_EL0, 0},
511 {"pmevtyper2_el0", PMEVTYPER2_EL0, 0},
512 {"pmevtyper3_el0", PMEVTYPER3_EL0, 0},
513 {"pmevtyper4_el0", PMEVTYPER4_EL0, 0},
514 {"pmevtyper5_el0", PMEVTYPER5_EL0, 0},
515 {"pmevtyper6_el0", PMEVTYPER6_EL0, 0},
516 {"pmevtyper7_el0", PMEVTYPER7_EL0, 0},
517 {"pmevtyper8_el0", PMEVTYPER8_EL0, 0},
518 {"pmevtyper9_el0", PMEVTYPER9_EL0, 0},
519 {"pmevtyper10_el0", PMEVTYPER10_EL0, 0},
520 {"pmevtyper11_el0", PMEVTYPER11_EL0, 0},
521 {"pmevtyper12_el0", PMEVTYPER12_EL0, 0},
522 {"pmevtyper13_el0", PMEVTYPER13_EL0, 0},
523 {"pmevtyper14_el0", PMEVTYPER14_EL0, 0},
524 {"pmevtyper15_el0", PMEVTYPER15_EL0, 0},
525 {"pmevtyper16_el0", PMEVTYPER16_EL0, 0},
526 {"pmevtyper17_el0", PMEVTYPER17_EL0, 0},
527 {"pmevtyper18_el0", PMEVTYPER18_EL0, 0},
528 {"pmevtyper19_el0", PMEVTYPER19_EL0, 0},
529 {"pmevtyper20_el0", PMEVTYPER20_EL0, 0},
530 {"pmevtyper21_el0", PMEVTYPER21_EL0, 0},
531 {"pmevtyper22_el0", PMEVTYPER22_EL0, 0},
532 {"pmevtyper23_el0", PMEVTYPER23_EL0, 0},
533 {"pmevtyper24_el0", PMEVTYPER24_EL0, 0},
534 {"pmevtyper25_el0", PMEVTYPER25_EL0, 0},
535 {"pmevtyper26_el0", PMEVTYPER26_EL0, 0},
536 {"pmevtyper27_el0", PMEVTYPER27_EL0, 0},
537 {"pmevtyper28_el0", PMEVTYPER28_EL0, 0},
538 {"pmevtyper29_el0", PMEVTYPER29_EL0, 0},
539 {"pmevtyper30_el0", PMEVTYPER30_EL0, 0},
288 {"osdtrrx_el1", OSDTRRX_EL1, {}},
289 {"osdtrtx_el1", OSDTRTX_EL1, {}},
290 {"teecr32_el1", TEECR32_EL1, {}},
291 {"mdccint_el1", MDCCINT_EL1, {}},
292 {"mdscr_el1", MDSCR_EL1, {}},
293 {"dbgdtr_el0", DBGDTR_EL0, {}},
294 {"oseccr_el1", OSECCR_EL1, {}},
295 {"dbgvcr32_el2", DBGVCR32_EL2, {}},
296 {"dbgbvr0_el1", DBGBVR0_EL1, {}},
297 {"dbgbvr1_el1", DBGBVR1_EL1, {}},
298 {"dbgbvr2_el1", DBGBVR2_EL1, {}},
299 {"dbgbvr3_el1", DBGBVR3_EL1, {}},
300 {"dbgbvr4_el1", DBGBVR4_EL1, {}},
301 {"dbgbvr5_el1", DBGBVR5_EL1, {}},
302 {"dbgbvr6_el1", DBGBVR6_EL1, {}},
303 {"dbgbvr7_el1", DBGBVR7_EL1, {}},
304 {"dbgbvr8_el1", DBGBVR8_EL1, {}},
305 {"dbgbvr9_el1", DBGBVR9_EL1, {}},
306 {"dbgbvr10_el1", DBGBVR10_EL1, {}},
307 {"dbgbvr11_el1", DBGBVR11_EL1, {}},
308 {"dbgbvr12_el1", DBGBVR12_EL1, {}},
309 {"dbgbvr13_el1", DBGBVR13_EL1, {}},
310 {"dbgbvr14_el1", DBGBVR14_EL1, {}},
311 {"dbgbvr15_el1", DBGBVR15_EL1, {}},
312 {"dbgbcr0_el1", DBGBCR0_EL1, {}},
313 {"dbgbcr1_el1", DBGBCR1_EL1, {}},
314 {"dbgbcr2_el1", DBGBCR2_EL1, {}},
315 {"dbgbcr3_el1", DBGBCR3_EL1, {}},
316 {"dbgbcr4_el1", DBGBCR4_EL1, {}},
317 {"dbgbcr5_el1", DBGBCR5_EL1, {}},
318 {"dbgbcr6_el1", DBGBCR6_EL1, {}},
319 {"dbgbcr7_el1", DBGBCR7_EL1, {}},
320 {"dbgbcr8_el1", DBGBCR8_EL1, {}},
321 {"dbgbcr9_el1", DBGBCR9_EL1, {}},
322 {"dbgbcr10_el1", DBGBCR10_EL1, {}},
323 {"dbgbcr11_el1", DBGBCR11_EL1, {}},
324 {"dbgbcr12_el1", DBGBCR12_EL1, {}},
325 {"dbgbcr13_el1", DBGBCR13_EL1, {}},
326 {"dbgbcr14_el1", DBGBCR14_EL1, {}},
327 {"dbgbcr15_el1", DBGBCR15_EL1, {}},
328 {"dbgwvr0_el1", DBGWVR0_EL1, {}},
329 {"dbgwvr1_el1", DBGWVR1_EL1, {}},
330 {"dbgwvr2_el1", DBGWVR2_EL1, {}},
331 {"dbgwvr3_el1", DBGWVR3_EL1, {}},
332 {"dbgwvr4_el1", DBGWVR4_EL1, {}},
333 {"dbgwvr5_el1", DBGWVR5_EL1, {}},
334 {"dbgwvr6_el1", DBGWVR6_EL1, {}},
335 {"dbgwvr7_el1", DBGWVR7_EL1, {}},
336 {"dbgwvr8_el1", DBGWVR8_EL1, {}},
337 {"dbgwvr9_el1", DBGWVR9_EL1, {}},
338 {"dbgwvr10_el1", DBGWVR10_EL1, {}},
339 {"dbgwvr11_el1", DBGWVR11_EL1, {}},
340 {"dbgwvr12_el1", DBGWVR12_EL1, {}},
341 {"dbgwvr13_el1", DBGWVR13_EL1, {}},
342 {"dbgwvr14_el1", DBGWVR14_EL1, {}},
343 {"dbgwvr15_el1", DBGWVR15_EL1, {}},
344 {"dbgwcr0_el1", DBGWCR0_EL1, {}},
345 {"dbgwcr1_el1", DBGWCR1_EL1, {}},
346 {"dbgwcr2_el1", DBGWCR2_EL1, {}},
347 {"dbgwcr3_el1", DBGWCR3_EL1, {}},
348 {"dbgwcr4_el1", DBGWCR4_EL1, {}},
349 {"dbgwcr5_el1", DBGWCR5_EL1, {}},
350 {"dbgwcr6_el1", DBGWCR6_EL1, {}},
351 {"dbgwcr7_el1", DBGWCR7_EL1, {}},
352 {"dbgwcr8_el1", DBGWCR8_EL1, {}},
353 {"dbgwcr9_el1", DBGWCR9_EL1, {}},
354 {"dbgwcr10_el1", DBGWCR10_EL1, {}},
355 {"dbgwcr11_el1", DBGWCR11_EL1, {}},
356 {"dbgwcr12_el1", DBGWCR12_EL1, {}},
357 {"dbgwcr13_el1", DBGWCR13_EL1, {}},
358 {"dbgwcr14_el1", DBGWCR14_EL1, {}},
359 {"dbgwcr15_el1", DBGWCR15_EL1, {}},
360 {"teehbr32_el1", TEEHBR32_EL1, {}},
361 {"osdlr_el1", OSDLR_EL1, {}},
362 {"dbgprcr_el1", DBGPRCR_EL1, {}},
363 {"dbgclaimset_el1", DBGCLAIMSET_EL1, {}},
364 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1, {}},
365 {"csselr_el1", CSSELR_EL1, {}},
366 {"vpidr_el2", VPIDR_EL2, {}},
367 {"vmpidr_el2", VMPIDR_EL2, {}},
368 {"sctlr_el1", SCTLR_EL1, {}},
369 {"sctlr_el2", SCTLR_EL2, {}},
370 {"sctlr_el3", SCTLR_EL3, {}},
371 {"actlr_el1", ACTLR_EL1, {}},
372 {"actlr_el2", ACTLR_EL2, {}},
373 {"actlr_el3", ACTLR_EL3, {}},
374 {"cpacr_el1", CPACR_EL1, {}},
375 {"hcr_el2", HCR_EL2, {}},
376 {"scr_el3", SCR_EL3, {}},
377 {"mdcr_el2", MDCR_EL2, {}},
378 {"sder32_el3", SDER32_EL3, {}},
379 {"cptr_el2", CPTR_EL2, {}},
380 {"cptr_el3", CPTR_EL3, {}},
381 {"hstr_el2", HSTR_EL2, {}},
382 {"hacr_el2", HACR_EL2, {}},
383 {"mdcr_el3", MDCR_EL3, {}},
384 {"ttbr0_el1", TTBR0_EL1, {}},
385 {"ttbr0_el2", TTBR0_EL2, {}},
386 {"ttbr0_el3", TTBR0_EL3, {}},
387 {"ttbr1_el1", TTBR1_EL1, {}},
388 {"tcr_el1", TCR_EL1, {}},
389 {"tcr_el2", TCR_EL2, {}},
390 {"tcr_el3", TCR_EL3, {}},
391 {"vttbr_el2", VTTBR_EL2, {}},
392 {"vtcr_el2", VTCR_EL2, {}},
393 {"dacr32_el2", DACR32_EL2, {}},
394 {"spsr_el1", SPSR_EL1, {}},
395 {"spsr_el2", SPSR_EL2, {}},
396 {"spsr_el3", SPSR_EL3, {}},
397 {"elr_el1", ELR_EL1, {}},
398 {"elr_el2", ELR_EL2, {}},
399 {"elr_el3", ELR_EL3, {}},
400 {"sp_el0", SP_EL0, {}},
401 {"sp_el1", SP_EL1, {}},
402 {"sp_el2", SP_EL2, {}},
403 {"spsel", SPSel, {}},
404 {"nzcv", NZCV, {}},
405 {"daif", DAIF, {}},
406 {"currentel", CurrentEL, {}},
407 {"spsr_irq", SPSR_irq, {}},
408 {"spsr_abt", SPSR_abt, {}},
409 {"spsr_und", SPSR_und, {}},
410 {"spsr_fiq", SPSR_fiq, {}},
411 {"fpcr", FPCR, {}},
412 {"fpsr", FPSR, {}},
413 {"dspsr_el0", DSPSR_EL0, {}},
414 {"dlr_el0", DLR_EL0, {}},
415 {"ifsr32_el2", IFSR32_EL2, {}},
416 {"afsr0_el1", AFSR0_EL1, {}},
417 {"afsr0_el2", AFSR0_EL2, {}},
418 {"afsr0_el3", AFSR0_EL3, {}},
419 {"afsr1_el1", AFSR1_EL1, {}},
420 {"afsr1_el2", AFSR1_EL2, {}},
421 {"afsr1_el3", AFSR1_EL3, {}},
422 {"esr_el1", ESR_EL1, {}},
423 {"esr_el2", ESR_EL2, {}},
424 {"esr_el3", ESR_EL3, {}},
425 {"fpexc32_el2", FPEXC32_EL2, {}},
426 {"far_el1", FAR_EL1, {}},
427 {"far_el2", FAR_EL2, {}},
428 {"far_el3", FAR_EL3, {}},
429 {"hpfar_el2", HPFAR_EL2, {}},
430 {"par_el1", PAR_EL1, {}},
431 {"pmcr_el0", PMCR_EL0, {}},
432 {"pmcntenset_el0", PMCNTENSET_EL0, {}},
433 {"pmcntenclr_el0", PMCNTENCLR_EL0, {}},
434 {"pmovsclr_el0", PMOVSCLR_EL0, {}},
435 {"pmselr_el0", PMSELR_EL0, {}},
436 {"pmccntr_el0", PMCCNTR_EL0, {}},
437 {"pmxevtyper_el0", PMXEVTYPER_EL0, {}},
438 {"pmxevcntr_el0", PMXEVCNTR_EL0, {}},
439 {"pmuserenr_el0", PMUSERENR_EL0, {}},
440 {"pmintenset_el1", PMINTENSET_EL1, {}},
441 {"pmintenclr_el1", PMINTENCLR_EL1, {}},
442 {"pmovsset_el0", PMOVSSET_EL0, {}},
443 {"mair_el1", MAIR_EL1, {}},
444 {"mair_el2", MAIR_EL2, {}},
445 {"mair_el3", MAIR_EL3, {}},
446 {"amair_el1", AMAIR_EL1, {}},
447 {"amair_el2", AMAIR_EL2, {}},
448 {"amair_el3", AMAIR_EL3, {}},
449 {"vbar_el1", VBAR_EL1, {}},
450 {"vbar_el2", VBAR_EL2, {}},
451 {"vbar_el3", VBAR_EL3, {}},
452 {"rmr_el1", RMR_EL1, {}},
453 {"rmr_el2", RMR_EL2, {}},
454 {"rmr_el3", RMR_EL3, {}},
455 {"contextidr_el1", CONTEXTIDR_EL1, {}},
456 {"tpidr_el0", TPIDR_EL0, {}},
457 {"tpidr_el2", TPIDR_EL2, {}},
458 {"tpidr_el3", TPIDR_EL3, {}},
459 {"tpidrro_el0", TPIDRRO_EL0, {}},
460 {"tpidr_el1", TPIDR_EL1, {}},
461 {"cntfrq_el0", CNTFRQ_EL0, {}},
462 {"cntvoff_el2", CNTVOFF_EL2, {}},
463 {"cntkctl_el1", CNTKCTL_EL1, {}},
464 {"cnthctl_el2", CNTHCTL_EL2, {}},
465 {"cntp_tval_el0", CNTP_TVAL_EL0, {}},
466 {"cnthp_tval_el2", CNTHP_TVAL_EL2, {}},
467 {"cntps_tval_el1", CNTPS_TVAL_EL1, {}},
468 {"cntp_ctl_el0", CNTP_CTL_EL0, {}},
469 {"cnthp_ctl_el2", CNTHP_CTL_EL2, {}},
470 {"cntps_ctl_el1", CNTPS_CTL_EL1, {}},
471 {"cntp_cval_el0", CNTP_CVAL_EL0, {}},
472 {"cnthp_cval_el2", CNTHP_CVAL_EL2, {}},
473 {"cntps_cval_el1", CNTPS_CVAL_EL1, {}},
474 {"cntv_tval_el0", CNTV_TVAL_EL0, {}},
475 {"cntv_ctl_el0", CNTV_CTL_EL0, {}},
476 {"cntv_cval_el0", CNTV_CVAL_EL0, {}},
477 {"pmevcntr0_el0", PMEVCNTR0_EL0, {}},
478 {"pmevcntr1_el0", PMEVCNTR1_EL0, {}},
479 {"pmevcntr2_el0", PMEVCNTR2_EL0, {}},
480 {"pmevcntr3_el0", PMEVCNTR3_EL0, {}},
481 {"pmevcntr4_el0", PMEVCNTR4_EL0, {}},
482 {"pmevcntr5_el0", PMEVCNTR5_EL0, {}},
483 {"pmevcntr6_el0", PMEVCNTR6_EL0, {}},
484 {"pmevcntr7_el0", PMEVCNTR7_EL0, {}},
485 {"pmevcntr8_el0", PMEVCNTR8_EL0, {}},
486 {"pmevcntr9_el0", PMEVCNTR9_EL0, {}},
487 {"pmevcntr10_el0", PMEVCNTR10_EL0, {}},
488 {"pmevcntr11_el0", PMEVCNTR11_EL0, {}},
489 {"pmevcntr12_el0", PMEVCNTR12_EL0, {}},
490 {"pmevcntr13_el0", PMEVCNTR13_EL0, {}},
491 {"pmevcntr14_el0", PMEVCNTR14_EL0, {}},
492 {"pmevcntr15_el0", PMEVCNTR15_EL0, {}},
493 {"pmevcntr16_el0", PMEVCNTR16_EL0, {}},
494 {"pmevcntr17_el0", PMEVCNTR17_EL0, {}},
495 {"pmevcntr18_el0", PMEVCNTR18_EL0, {}},
496 {"pmevcntr19_el0", PMEVCNTR19_EL0, {}},
497 {"pmevcntr20_el0", PMEVCNTR20_EL0, {}},
498 {"pmevcntr21_el0", PMEVCNTR21_EL0, {}},
499 {"pmevcntr22_el0", PMEVCNTR22_EL0, {}},
500 {"pmevcntr23_el0", PMEVCNTR23_EL0, {}},
501 {"pmevcntr24_el0", PMEVCNTR24_EL0, {}},
502 {"pmevcntr25_el0", PMEVCNTR25_EL0, {}},
503 {"pmevcntr26_el0", PMEVCNTR26_EL0, {}},
504 {"pmevcntr27_el0", PMEVCNTR27_EL0, {}},
505 {"pmevcntr28_el0", PMEVCNTR28_EL0, {}},
506 {"pmevcntr29_el0", PMEVCNTR29_EL0, {}},
507 {"pmevcntr30_el0", PMEVCNTR30_EL0, {}},
508 {"pmccfiltr_el0", PMCCFILTR_EL0, {}},
509 {"pmevtyper0_el0", PMEVTYPER0_EL0, {}},
510 {"pmevtyper1_el0", PMEVTYPER1_EL0, {}},
511 {"pmevtyper2_el0", PMEVTYPER2_EL0, {}},
512 {"pmevtyper3_el0", PMEVTYPER3_EL0, {}},
513 {"pmevtyper4_el0", PMEVTYPER4_EL0, {}},
514 {"pmevtyper5_el0", PMEVTYPER5_EL0, {}},
515 {"pmevtyper6_el0", PMEVTYPER6_EL0, {}},
516 {"pmevtyper7_el0", PMEVTYPER7_EL0, {}},
517 {"pmevtyper8_el0", PMEVTYPER8_EL0, {}},
518 {"pmevtyper9_el0", PMEVTYPER9_EL0, {}},
519 {"pmevtyper10_el0", PMEVTYPER10_EL0, {}},
520 {"pmevtyper11_el0", PMEVTYPER11_EL0, {}},
521 {"pmevtyper12_el0", PMEVTYPER12_EL0, {}},
522 {"pmevtyper13_el0", PMEVTYPER13_EL0, {}},
523 {"pmevtyper14_el0", PMEVTYPER14_EL0, {}},
524 {"pmevtyper15_el0", PMEVTYPER15_EL0, {}},
525 {"pmevtyper16_el0", PMEVTYPER16_EL0, {}},
526 {"pmevtyper17_el0", PMEVTYPER17_EL0, {}},
527 {"pmevtyper18_el0", PMEVTYPER18_EL0, {}},
528 {"pmevtyper19_el0", PMEVTYPER19_EL0, {}},
529 {"pmevtyper20_el0", PMEVTYPER20_EL0, {}},
530 {"pmevtyper21_el0", PMEVTYPER21_EL0, {}},
531 {"pmevtyper22_el0", PMEVTYPER22_EL0, {}},
532 {"pmevtyper23_el0", PMEVTYPER23_EL0, {}},
533 {"pmevtyper24_el0", PMEVTYPER24_EL0, {}},
534 {"pmevtyper25_el0", PMEVTYPER25_EL0, {}},
535 {"pmevtyper26_el0", PMEVTYPER26_EL0, {}},
536 {"pmevtyper27_el0", PMEVTYPER27_EL0, {}},
537 {"pmevtyper28_el0", PMEVTYPER28_EL0, {}},
538 {"pmevtyper29_el0", PMEVTYPER29_EL0, {}},
539 {"pmevtyper30_el0", PMEVTYPER30_EL0, {}},
540540
541541 // Trace registers
542 {"trcprgctlr", TRCPRGCTLR, 0},
543 {"trcprocselr", TRCPROCSELR, 0},
544 {"trcconfigr", TRCCONFIGR, 0},
545 {"trcauxctlr", TRCAUXCTLR, 0},
546 {"trceventctl0r", TRCEVENTCTL0R, 0},
547 {"trceventctl1r", TRCEVENTCTL1R, 0},
548 {"trcstallctlr", TRCSTALLCTLR, 0},
549 {"trctsctlr", TRCTSCTLR, 0},
550 {"trcsyncpr", TRCSYNCPR, 0},
551 {"trcccctlr", TRCCCCTLR, 0},
552 {"trcbbctlr", TRCBBCTLR, 0},
553 {"trctraceidr", TRCTRACEIDR, 0},
554 {"trcqctlr", TRCQCTLR, 0},
555 {"trcvictlr", TRCVICTLR, 0},
556 {"trcviiectlr", TRCVIIECTLR, 0},
557 {"trcvissctlr", TRCVISSCTLR, 0},
558 {"trcvipcssctlr", TRCVIPCSSCTLR, 0},
559 {"trcvdctlr", TRCVDCTLR, 0},
560 {"trcvdsacctlr", TRCVDSACCTLR, 0},
561 {"trcvdarcctlr", TRCVDARCCTLR, 0},
562 {"trcseqevr0", TRCSEQEVR0, 0},
563 {"trcseqevr1", TRCSEQEVR1, 0},
564 {"trcseqevr2", TRCSEQEVR2, 0},
565 {"trcseqrstevr", TRCSEQRSTEVR, 0},
566 {"trcseqstr", TRCSEQSTR, 0},
567 {"trcextinselr", TRCEXTINSELR, 0},
568 {"trccntrldvr0", TRCCNTRLDVR0, 0},
569 {"trccntrldvr1", TRCCNTRLDVR1, 0},
570 {"trccntrldvr2", TRCCNTRLDVR2, 0},
571 {"trccntrldvr3", TRCCNTRLDVR3, 0},
572 {"trccntctlr0", TRCCNTCTLR0, 0},
573 {"trccntctlr1", TRCCNTCTLR1, 0},
574 {"trccntctlr2", TRCCNTCTLR2, 0},
575 {"trccntctlr3", TRCCNTCTLR3, 0},
576 {"trccntvr0", TRCCNTVR0, 0},
577 {"trccntvr1", TRCCNTVR1, 0},
578 {"trccntvr2", TRCCNTVR2, 0},
579 {"trccntvr3", TRCCNTVR3, 0},
580 {"trcimspec0", TRCIMSPEC0, 0},
581 {"trcimspec1", TRCIMSPEC1, 0},
582 {"trcimspec2", TRCIMSPEC2, 0},
583 {"trcimspec3", TRCIMSPEC3, 0},
584 {"trcimspec4", TRCIMSPEC4, 0},
585 {"trcimspec5", TRCIMSPEC5, 0},
586 {"trcimspec6", TRCIMSPEC6, 0},
587 {"trcimspec7", TRCIMSPEC7, 0},
588 {"trcrsctlr2", TRCRSCTLR2, 0},
589 {"trcrsctlr3", TRCRSCTLR3, 0},
590 {"trcrsctlr4", TRCRSCTLR4, 0},
591 {"trcrsctlr5", TRCRSCTLR5, 0},
592 {"trcrsctlr6", TRCRSCTLR6, 0},
593 {"trcrsctlr7", TRCRSCTLR7, 0},
594 {"trcrsctlr8", TRCRSCTLR8, 0},
595 {"trcrsctlr9", TRCRSCTLR9, 0},
596 {"trcrsctlr10", TRCRSCTLR10, 0},
597 {"trcrsctlr11", TRCRSCTLR11, 0},
598 {"trcrsctlr12", TRCRSCTLR12, 0},
599 {"trcrsctlr13", TRCRSCTLR13, 0},
600 {"trcrsctlr14", TRCRSCTLR14, 0},
601 {"trcrsctlr15", TRCRSCTLR15, 0},
602 {"trcrsctlr16", TRCRSCTLR16, 0},
603 {"trcrsctlr17", TRCRSCTLR17, 0},
604 {"trcrsctlr18", TRCRSCTLR18, 0},
605 {"trcrsctlr19", TRCRSCTLR19, 0},
606 {"trcrsctlr20", TRCRSCTLR20, 0},
607 {"trcrsctlr21", TRCRSCTLR21, 0},
608 {"trcrsctlr22", TRCRSCTLR22, 0},
609 {"trcrsctlr23", TRCRSCTLR23, 0},
610 {"trcrsctlr24", TRCRSCTLR24, 0},
611 {"trcrsctlr25", TRCRSCTLR25, 0},
612 {"trcrsctlr26", TRCRSCTLR26, 0},
613 {"trcrsctlr27", TRCRSCTLR27, 0},
614 {"trcrsctlr28", TRCRSCTLR28, 0},
615 {"trcrsctlr29", TRCRSCTLR29, 0},
616 {"trcrsctlr30", TRCRSCTLR30, 0},
617 {"trcrsctlr31", TRCRSCTLR31, 0},
618 {"trcssccr0", TRCSSCCR0, 0},
619 {"trcssccr1", TRCSSCCR1, 0},
620 {"trcssccr2", TRCSSCCR2, 0},
621 {"trcssccr3", TRCSSCCR3, 0},
622 {"trcssccr4", TRCSSCCR4, 0},
623 {"trcssccr5", TRCSSCCR5, 0},
624 {"trcssccr6", TRCSSCCR6, 0},
625 {"trcssccr7", TRCSSCCR7, 0},
626 {"trcsscsr0", TRCSSCSR0, 0},
627 {"trcsscsr1", TRCSSCSR1, 0},
628 {"trcsscsr2", TRCSSCSR2, 0},
629 {"trcsscsr3", TRCSSCSR3, 0},
630 {"trcsscsr4", TRCSSCSR4, 0},
631 {"trcsscsr5", TRCSSCSR5, 0},
632 {"trcsscsr6", TRCSSCSR6, 0},
633 {"trcsscsr7", TRCSSCSR7, 0},
634 {"trcsspcicr0", TRCSSPCICR0, 0},
635 {"trcsspcicr1", TRCSSPCICR1, 0},
636 {"trcsspcicr2", TRCSSPCICR2, 0},
637 {"trcsspcicr3", TRCSSPCICR3, 0},
638 {"trcsspcicr4", TRCSSPCICR4, 0},
639 {"trcsspcicr5", TRCSSPCICR5, 0},
640 {"trcsspcicr6", TRCSSPCICR6, 0},
641 {"trcsspcicr7", TRCSSPCICR7, 0},
642 {"trcpdcr", TRCPDCR, 0},
643 {"trcacvr0", TRCACVR0, 0},
644 {"trcacvr1", TRCACVR1, 0},
645 {"trcacvr2", TRCACVR2, 0},
646 {"trcacvr3", TRCACVR3, 0},
647 {"trcacvr4", TRCACVR4, 0},
648 {"trcacvr5", TRCACVR5, 0},
649 {"trcacvr6", TRCACVR6, 0},
650 {"trcacvr7", TRCACVR7, 0},
651 {"trcacvr8", TRCACVR8, 0},
652 {"trcacvr9", TRCACVR9, 0},
653 {"trcacvr10", TRCACVR10, 0},
654 {"trcacvr11", TRCACVR11, 0},
655 {"trcacvr12", TRCACVR12, 0},
656 {"trcacvr13", TRCACVR13, 0},
657 {"trcacvr14", TRCACVR14, 0},
658 {"trcacvr15", TRCACVR15, 0},
659 {"trcacatr0", TRCACATR0, 0},
660 {"trcacatr1", TRCACATR1, 0},
661 {"trcacatr2", TRCACATR2, 0},
662 {"trcacatr3", TRCACATR3, 0},
663 {"trcacatr4", TRCACATR4, 0},
664 {"trcacatr5", TRCACATR5, 0},
665 {"trcacatr6", TRCACATR6, 0},
666 {"trcacatr7", TRCACATR7, 0},
667 {"trcacatr8", TRCACATR8, 0},
668 {"trcacatr9", TRCACATR9, 0},
669 {"trcacatr10", TRCACATR10, 0},
670 {"trcacatr11", TRCACATR11, 0},
671 {"trcacatr12", TRCACATR12, 0},
672 {"trcacatr13", TRCACATR13, 0},
673 {"trcacatr14", TRCACATR14, 0},
674 {"trcacatr15", TRCACATR15, 0},
675 {"trcdvcvr0", TRCDVCVR0, 0},
676 {"trcdvcvr1", TRCDVCVR1, 0},
677 {"trcdvcvr2", TRCDVCVR2, 0},
678 {"trcdvcvr3", TRCDVCVR3, 0},
679 {"trcdvcvr4", TRCDVCVR4, 0},
680 {"trcdvcvr5", TRCDVCVR5, 0},
681 {"trcdvcvr6", TRCDVCVR6, 0},
682 {"trcdvcvr7", TRCDVCVR7, 0},
683 {"trcdvcmr0", TRCDVCMR0, 0},
684 {"trcdvcmr1", TRCDVCMR1, 0},
685 {"trcdvcmr2", TRCDVCMR2, 0},
686 {"trcdvcmr3", TRCDVCMR3, 0},
687 {"trcdvcmr4", TRCDVCMR4, 0},
688 {"trcdvcmr5", TRCDVCMR5, 0},
689 {"trcdvcmr6", TRCDVCMR6, 0},
690 {"trcdvcmr7", TRCDVCMR7, 0},
691 {"trccidcvr0", TRCCIDCVR0, 0},
692 {"trccidcvr1", TRCCIDCVR1, 0},
693 {"trccidcvr2", TRCCIDCVR2, 0},
694 {"trccidcvr3", TRCCIDCVR3, 0},
695 {"trccidcvr4", TRCCIDCVR4, 0},
696 {"trccidcvr5", TRCCIDCVR5, 0},
697 {"trccidcvr6", TRCCIDCVR6, 0},
698 {"trccidcvr7", TRCCIDCVR7, 0},
699 {"trcvmidcvr0", TRCVMIDCVR0, 0},
700 {"trcvmidcvr1", TRCVMIDCVR1, 0},
701 {"trcvmidcvr2", TRCVMIDCVR2, 0},
702 {"trcvmidcvr3", TRCVMIDCVR3, 0},
703 {"trcvmidcvr4", TRCVMIDCVR4, 0},
704 {"trcvmidcvr5", TRCVMIDCVR5, 0},
705 {"trcvmidcvr6", TRCVMIDCVR6, 0},
706 {"trcvmidcvr7", TRCVMIDCVR7, 0},
707 {"trccidcctlr0", TRCCIDCCTLR0, 0},
708 {"trccidcctlr1", TRCCIDCCTLR1, 0},
709 {"trcvmidcctlr0", TRCVMIDCCTLR0, 0},
710 {"trcvmidcctlr1", TRCVMIDCCTLR1, 0},
711 {"trcitctrl", TRCITCTRL, 0},
712 {"trcclaimset", TRCCLAIMSET, 0},
713 {"trcclaimclr", TRCCLAIMCLR, 0},
542 {"trcprgctlr", TRCPRGCTLR, {}},
543 {"trcprocselr", TRCPROCSELR, {}},
544 {"trcconfigr", TRCCONFIGR, {}},
545 {"trcauxctlr", TRCAUXCTLR, {}},
546 {"trceventctl0r", TRCEVENTCTL0R, {}},
547 {"trceventctl1r", TRCEVENTCTL1R, {}},
548 {"trcstallctlr", TRCSTALLCTLR, {}},
549 {"trctsctlr", TRCTSCTLR, {}},
550 {"trcsyncpr", TRCSYNCPR, {}},
551 {"trcccctlr", TRCCCCTLR, {}},
552 {"trcbbctlr", TRCBBCTLR, {}},
553 {"trctraceidr", TRCTRACEIDR, {}},
554 {"trcqctlr", TRCQCTLR, {}},
555 {"trcvictlr", TRCVICTLR, {}},
556 {"trcviiectlr", TRCVIIECTLR, {}},
557 {"trcvissctlr", TRCVISSCTLR, {}},
558 {"trcvipcssctlr", TRCVIPCSSCTLR, {}},
559 {"trcvdctlr", TRCVDCTLR, {}},
560 {"trcvdsacctlr", TRCVDSACCTLR, {}},
561 {"trcvdarcctlr", TRCVDARCCTLR, {}},
562 {"trcseqevr0", TRCSEQEVR0, {}},
563 {"trcseqevr1", TRCSEQEVR1, {}},
564 {"trcseqevr2", TRCSEQEVR2, {}},
565 {"trcseqrstevr", TRCSEQRSTEVR, {}},
566 {"trcseqstr", TRCSEQSTR, {}},
567 {"trcextinselr", TRCEXTINSELR, {}},
568 {"trccntrldvr0", TRCCNTRLDVR0, {}},
569 {"trccntrldvr1", TRCCNTRLDVR1, {}},
570 {"trccntrldvr2", TRCCNTRLDVR2, {}},
571 {"trccntrldvr3", TRCCNTRLDVR3, {}},
572 {"trccntctlr0", TRCCNTCTLR0, {}},
573 {"trccntctlr1", TRCCNTCTLR1, {}},
574 {"trccntctlr2", TRCCNTCTLR2, {}},
575 {"trccntctlr3", TRCCNTCTLR3, {}},
576 {"trccntvr0", TRCCNTVR0, {}},
577 {"trccntvr1", TRCCNTVR1, {}},
578 {"trccntvr2", TRCCNTVR2, {}},
579 {"trccntvr3", TRCCNTVR3, {}},
580 {"trcimspec0", TRCIMSPEC0, {}},
581 {"trcimspec1", TRCIMSPEC1, {}},
582 {"trcimspec2", TRCIMSPEC2, {}},
583 {"trcimspec3", TRCIMSPEC3, {}},
584 {"trcimspec4", TRCIMSPEC4, {}},
585 {"trcimspec5", TRCIMSPEC5, {}},
586 {"trcimspec6", TRCIMSPEC6, {}},
587 {"trcimspec7", TRCIMSPEC7, {}},
588 {"trcrsctlr2", TRCRSCTLR2, {}},
589 {"trcrsctlr3", TRCRSCTLR3, {}},
590 {"trcrsctlr4", TRCRSCTLR4, {}},
591 {"trcrsctlr5", TRCRSCTLR5, {}},
592 {"trcrsctlr6", TRCRSCTLR6, {}},
593 {"trcrsctlr7", TRCRSCTLR7, {}},
594 {"trcrsctlr8", TRCRSCTLR8, {}},
595 {"trcrsctlr9", TRCRSCTLR9, {}},
596 {"trcrsctlr10", TRCRSCTLR10, {}},
597 {"trcrsctlr11", TRCRSCTLR11, {}},
598 {"trcrsctlr12", TRCRSCTLR12, {}},
599 {"trcrsctlr13", TRCRSCTLR13, {}},
600 {"trcrsctlr14", TRCRSCTLR14, {}},
601 {"trcrsctlr15", TRCRSCTLR15, {}},
602 {"trcrsctlr16", TRCRSCTLR16, {}},
603 {"trcrsctlr17", TRCRSCTLR17, {}},
604 {"trcrsctlr18", TRCRSCTLR18, {}},
605 {"trcrsctlr19", TRCRSCTLR19, {}},
606 {"trcrsctlr20", TRCRSCTLR20, {}},
607 {"trcrsctlr21", TRCRSCTLR21, {}},
608 {"trcrsctlr22", TRCRSCTLR22, {}},
609 {"trcrsctlr23", TRCRSCTLR23, {}},
610 {"trcrsctlr24", TRCRSCTLR24, {}},
611 {"trcrsctlr25", TRCRSCTLR25, {}},
612 {"trcrsctlr26", TRCRSCTLR26, {}},
613 {"trcrsctlr27", TRCRSCTLR27, {}},
614 {"trcrsctlr28", TRCRSCTLR28, {}},
615 {"trcrsctlr29", TRCRSCTLR29, {}},
616 {"trcrsctlr30", TRCRSCTLR30, {}},
617 {"trcrsctlr31", TRCRSCTLR31, {}},
618 {"trcssccr0", TRCSSCCR0, {}},
619 {"trcssccr1", TRCSSCCR1, {}},
620 {"trcssccr2", TRCSSCCR2, {}},
621 {"trcssccr3", TRCSSCCR3, {}},
622 {"trcssccr4", TRCSSCCR4, {}},
623 {"trcssccr5", TRCSSCCR5, {}},
624 {"trcssccr6", TRCSSCCR6, {}},
625 {"trcssccr7", TRCSSCCR7, {}},
626 {"trcsscsr0", TRCSSCSR0, {}},
627 {"trcsscsr1", TRCSSCSR1, {}},
628 {"trcsscsr2", TRCSSCSR2, {}},
629 {"trcsscsr3", TRCSSCSR3, {}},
630 {"trcsscsr4", TRCSSCSR4, {}},
631 {"trcsscsr5", TRCSSCSR5, {}},
632 {"trcsscsr6", TRCSSCSR6, {}},
633 {"trcsscsr7", TRCSSCSR7, {}},
634 {"trcsspcicr0", TRCSSPCICR0, {}},
635 {"trcsspcicr1", TRCSSPCICR1, {}},
636 {"trcsspcicr2", TRCSSPCICR2, {}},
637 {"trcsspcicr3", TRCSSPCICR3, {}},
638 {"trcsspcicr4", TRCSSPCICR4, {}},
639 {"trcsspcicr5", TRCSSPCICR5, {}},
640 {"trcsspcicr6", TRCSSPCICR6, {}},
641 {"trcsspcicr7", TRCSSPCICR7, {}},
642 {"trcpdcr", TRCPDCR, {}},
643 {"trcacvr0", TRCACVR0, {}},
644 {"trcacvr1", TRCACVR1, {}},
645 {"trcacvr2", TRCACVR2, {}},
646 {"trcacvr3", TRCACVR3, {}},
647 {"trcacvr4", TRCACVR4, {}},
648 {"trcacvr5", TRCACVR5, {}},
649 {"trcacvr6", TRCACVR6, {}},
650 {"trcacvr7", TRCACVR7, {}},
651 {"trcacvr8", TRCACVR8, {}},
652 {"trcacvr9", TRCACVR9, {}},
653 {"trcacvr10", TRCACVR10, {}},
654 {"trcacvr11", TRCACVR11, {}},
655 {"trcacvr12", TRCACVR12, {}},
656 {"trcacvr13", TRCACVR13, {}},
657 {"trcacvr14", TRCACVR14, {}},
658 {"trcacvr15", TRCACVR15, {}},
659 {"trcacatr0", TRCACATR0, {}},
660 {"trcacatr1", TRCACATR1, {}},
661 {"trcacatr2", TRCACATR2, {}},
662 {"trcacatr3", TRCACATR3, {}},
663 {"trcacatr4", TRCACATR4, {}},
664 {"trcacatr5", TRCACATR5, {}},
665 {"trcacatr6", TRCACATR6, {}},
666 {"trcacatr7", TRCACATR7, {}},
667 {"trcacatr8", TRCACATR8, {}},
668 {"trcacatr9", TRCACATR9, {}},
669 {"trcacatr10", TRCACATR10, {}},
670 {"trcacatr11", TRCACATR11, {}},
671 {"trcacatr12", TRCACATR12, {}},
672 {"trcacatr13", TRCACATR13, {}},
673 {"trcacatr14", TRCACATR14, {}},
674 {"trcacatr15", TRCACATR15, {}},
675 {"trcdvcvr0", TRCDVCVR0, {}},
676 {"trcdvcvr1", TRCDVCVR1, {}},
677 {"trcdvcvr2", TRCDVCVR2, {}},
678 {"trcdvcvr3", TRCDVCVR3, {}},
679 {"trcdvcvr4", TRCDVCVR4, {}},
680 {"trcdvcvr5", TRCDVCVR5, {}},
681 {"trcdvcvr6", TRCDVCVR6, {}},
682 {"trcdvcvr7", TRCDVCVR7, {}},
683 {"trcdvcmr0", TRCDVCMR0, {}},
684 {"trcdvcmr1", TRCDVCMR1, {}},
685 {"trcdvcmr2", TRCDVCMR2, {}},
686 {"trcdvcmr3", TRCDVCMR3, {}},
687 {"trcdvcmr4", TRCDVCMR4, {}},
688 {"trcdvcmr5", TRCDVCMR5, {}},
689 {"trcdvcmr6", TRCDVCMR6, {}},
690 {"trcdvcmr7", TRCDVCMR7, {}},
691 {"trccidcvr0", TRCCIDCVR0, {}},
692 {"trccidcvr1", TRCCIDCVR1, {}},
693 {"trccidcvr2", TRCCIDCVR2, {}},
694 {"trccidcvr3", TRCCIDCVR3, {}},
695 {"trccidcvr4", TRCCIDCVR4, {}},
696 {"trccidcvr5", TRCCIDCVR5, {}},
697 {"trccidcvr6", TRCCIDCVR6, {}},
698 {"trccidcvr7", TRCCIDCVR7, {}},
699 {"trcvmidcvr0", TRCVMIDCVR0, {}},
700 {"trcvmidcvr1", TRCVMIDCVR1, {}},
701 {"trcvmidcvr2", TRCVMIDCVR2, {}},
702 {"trcvmidcvr3", TRCVMIDCVR3, {}},
703 {"trcvmidcvr4", TRCVMIDCVR4, {}},
704 {"trcvmidcvr5", TRCVMIDCVR5, {}},
705 {"trcvmidcvr6", TRCVMIDCVR6, {}},
706 {"trcvmidcvr7", TRCVMIDCVR7, {}},
707 {"trccidcctlr0", TRCCIDCCTLR0, {}},
708 {"trccidcctlr1", TRCCIDCCTLR1, {}},
709 {"trcvmidcctlr0", TRCVMIDCCTLR0, {}},
710 {"trcvmidcctlr1", TRCVMIDCCTLR1, {}},
711 {"trcitctrl", TRCITCTRL, {}},
712 {"trcclaimset", TRCCLAIMSET, {}},
713 {"trcclaimclr", TRCCLAIMCLR, {}},
714714
715715 // GICv3 registers
716 {"icc_bpr1_el1", ICC_BPR1_EL1, 0},
717 {"icc_bpr0_el1", ICC_BPR0_EL1, 0},
718 {"icc_pmr_el1", ICC_PMR_EL1, 0},
719 {"icc_ctlr_el1", ICC_CTLR_EL1, 0},
720 {"icc_ctlr_el3", ICC_CTLR_EL3, 0},
721 {"icc_sre_el1", ICC_SRE_EL1, 0},
722 {"icc_sre_el2", ICC_SRE_EL2, 0},
723 {"icc_sre_el3", ICC_SRE_EL3, 0},
724 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, 0},
725 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, 0},
726 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, 0},
727 {"icc_seien_el1", ICC_SEIEN_EL1, 0},
728 {"icc_ap0r0_el1", ICC_AP0R0_EL1, 0},
729 {"icc_ap0r1_el1", ICC_AP0R1_EL1, 0},
730 {"icc_ap0r2_el1", ICC_AP0R2_EL1, 0},
731 {"icc_ap0r3_el1", ICC_AP0R3_EL1, 0},
732 {"icc_ap1r0_el1", ICC_AP1R0_EL1, 0},
733 {"icc_ap1r1_el1", ICC_AP1R1_EL1, 0},
734 {"icc_ap1r2_el1", ICC_AP1R2_EL1, 0},
735 {"icc_ap1r3_el1", ICC_AP1R3_EL1, 0},
736 {"ich_ap0r0_el2", ICH_AP0R0_EL2, 0},
737 {"ich_ap0r1_el2", ICH_AP0R1_EL2, 0},
738 {"ich_ap0r2_el2", ICH_AP0R2_EL2, 0},
739 {"ich_ap0r3_el2", ICH_AP0R3_EL2, 0},
740 {"ich_ap1r0_el2", ICH_AP1R0_EL2, 0},
741 {"ich_ap1r1_el2", ICH_AP1R1_EL2, 0},
742 {"ich_ap1r2_el2", ICH_AP1R2_EL2, 0},
743 {"ich_ap1r3_el2", ICH_AP1R3_EL2, 0},
744 {"ich_hcr_el2", ICH_HCR_EL2, 0},
745 {"ich_misr_el2", ICH_MISR_EL2, 0},
746 {"ich_vmcr_el2", ICH_VMCR_EL2, 0},
747 {"ich_vseir_el2", ICH_VSEIR_EL2, 0},
748 {"ich_lr0_el2", ICH_LR0_EL2, 0},
749 {"ich_lr1_el2", ICH_LR1_EL2, 0},
750 {"ich_lr2_el2", ICH_LR2_EL2, 0},
751 {"ich_lr3_el2", ICH_LR3_EL2, 0},
752 {"ich_lr4_el2", ICH_LR4_EL2, 0},
753 {"ich_lr5_el2", ICH_LR5_EL2, 0},
754 {"ich_lr6_el2", ICH_LR6_EL2, 0},
755 {"ich_lr7_el2", ICH_LR7_EL2, 0},
756 {"ich_lr8_el2", ICH_LR8_EL2, 0},
757 {"ich_lr9_el2", ICH_LR9_EL2, 0},
758 {"ich_lr10_el2", ICH_LR10_EL2, 0},
759 {"ich_lr11_el2", ICH_LR11_EL2, 0},
760 {"ich_lr12_el2", ICH_LR12_EL2, 0},
761 {"ich_lr13_el2", ICH_LR13_EL2, 0},
762 {"ich_lr14_el2", ICH_LR14_EL2, 0},
763 {"ich_lr15_el2", ICH_LR15_EL2, 0},
716 {"icc_bpr1_el1", ICC_BPR1_EL1, {}},
717 {"icc_bpr0_el1", ICC_BPR0_EL1, {}},
718 {"icc_pmr_el1", ICC_PMR_EL1, {}},
719 {"icc_ctlr_el1", ICC_CTLR_EL1, {}},
720 {"icc_ctlr_el3", ICC_CTLR_EL3, {}},
721 {"icc_sre_el1", ICC_SRE_EL1, {}},
722 {"icc_sre_el2", ICC_SRE_EL2, {}},
723 {"icc_sre_el3", ICC_SRE_EL3, {}},
724 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1, {}},
725 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1, {}},
726 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3, {}},
727 {"icc_seien_el1", ICC_SEIEN_EL1, {}},
728 {"icc_ap0r0_el1", ICC_AP0R0_EL1, {}},
729 {"icc_ap0r1_el1", ICC_AP0R1_EL1, {}},
730 {"icc_ap0r2_el1", ICC_AP0R2_EL1, {}},
731 {"icc_ap0r3_el1", ICC_AP0R3_EL1, {}},
732 {"icc_ap1r0_el1", ICC_AP1R0_EL1, {}},
733 {"icc_ap1r1_el1", ICC_AP1R1_EL1, {}},
734 {"icc_ap1r2_el1", ICC_AP1R2_EL1, {}},
735 {"icc_ap1r3_el1", ICC_AP1R3_EL1, {}},
736 {"ich_ap0r0_el2", ICH_AP0R0_EL2, {}},
737 {"ich_ap0r1_el2", ICH_AP0R1_EL2, {}},
738 {"ich_ap0r2_el2", ICH_AP0R2_EL2, {}},
739 {"ich_ap0r3_el2", ICH_AP0R3_EL2, {}},
740 {"ich_ap1r0_el2", ICH_AP1R0_EL2, {}},
741 {"ich_ap1r1_el2", ICH_AP1R1_EL2, {}},
742 {"ich_ap1r2_el2", ICH_AP1R2_EL2, {}},
743 {"ich_ap1r3_el2", ICH_AP1R3_EL2, {}},
744 {"ich_hcr_el2", ICH_HCR_EL2, {}},
745 {"ich_misr_el2", ICH_MISR_EL2, {}},
746 {"ich_vmcr_el2", ICH_VMCR_EL2, {}},
747 {"ich_vseir_el2", ICH_VSEIR_EL2, {}},
748 {"ich_lr0_el2", ICH_LR0_EL2, {}},
749 {"ich_lr1_el2", ICH_LR1_EL2, {}},
750 {"ich_lr2_el2", ICH_LR2_EL2, {}},
751 {"ich_lr3_el2", ICH_LR3_EL2, {}},
752 {"ich_lr4_el2", ICH_LR4_EL2, {}},
753 {"ich_lr5_el2", ICH_LR5_EL2, {}},
754 {"ich_lr6_el2", ICH_LR6_EL2, {}},
755 {"ich_lr7_el2", ICH_LR7_EL2, {}},
756 {"ich_lr8_el2", ICH_LR8_EL2, {}},
757 {"ich_lr9_el2", ICH_LR9_EL2, {}},
758 {"ich_lr10_el2", ICH_LR10_EL2, {}},
759 {"ich_lr11_el2", ICH_LR11_EL2, {}},
760 {"ich_lr12_el2", ICH_LR12_EL2, {}},
761 {"ich_lr13_el2", ICH_LR13_EL2, {}},
762 {"ich_lr14_el2", ICH_LR14_EL2, {}},
763 {"ich_lr15_el2", ICH_LR15_EL2, {}},
764764
765765 // Cyclone registers
766 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, AArch64::ProcCyclone},
766 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, {AArch64::ProcCyclone}},
767767
768768 // v8.1a "Privileged Access Never" extension-specific system registers
769 {"pan", PAN, AArch64::HasV8_1aOps},
769 {"pan", PAN, {AArch64::HasV8_1aOps}},
770770
771771 // v8.1a "Limited Ordering Regions" extension-specific system registers
772 {"lorsa_el1", LORSA_EL1, AArch64::HasV8_1aOps},
773 {"lorea_el1", LOREA_EL1, AArch64::HasV8_1aOps},
774 {"lorn_el1", LORN_EL1, AArch64::HasV8_1aOps},
775 {"lorc_el1", LORC_EL1, AArch64::HasV8_1aOps},
772 {"lorsa_el1", LORSA_EL1, {AArch64::HasV8_1aOps}},
773 {"lorea_el1", LOREA_EL1, {AArch64::HasV8_1aOps}},
774 {"lorn_el1", LORN_EL1, {AArch64::HasV8_1aOps}},
775 {"lorc_el1", LORC_EL1, {AArch64::HasV8_1aOps}},
776776
777777 // v8.1a "Virtualization host extensions" system registers
778 {"ttbr1_el2", TTBR1_EL2, AArch64::HasV8_1aOps},
779 {"contextidr_el2", CONTEXTIDR_EL2, AArch64::HasV8_1aOps},
780 {"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::HasV8_1aOps},
781 {"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::HasV8_1aOps},
782 {"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::HasV8_1aOps},
783 {"sctlr_el12", SCTLR_EL12, AArch64::HasV8_1aOps},
784 {"cpacr_el12", CPACR_EL12, AArch64::HasV8_1aOps},
785 {"ttbr0_el12", TTBR0_EL12, AArch64::HasV8_1aOps},
786 {"ttbr1_el12", TTBR1_EL12, AArch64::HasV8_1aOps},
787 {"tcr_el12", TCR_EL12, AArch64::HasV8_1aOps},
788 {"afsr0_el12", AFSR0_EL12, AArch64::HasV8_1aOps},
789 {"afsr1_el12", AFSR1_EL12, AArch64::HasV8_1aOps},
790 {"esr_el12", ESR_EL12, AArch64::HasV8_1aOps},
791 {"far_el12", FAR_EL12, AArch64::HasV8_1aOps},
792 {"mair_el12", MAIR_EL12, AArch64::HasV8_1aOps},
793 {"amair_el12", AMAIR_EL12, AArch64::HasV8_1aOps},
794 {"vbar_el12", VBAR_EL12, AArch64::HasV8_1aOps},
795 {"contextidr_el12", CONTEXTIDR_EL12, AArch64::HasV8_1aOps},
796 {"cntkctl_el12", CNTKCTL_EL12, AArch64::HasV8_1aOps},
797 {"cntp_tval_el02", CNTP_TVAL_EL02, AArch64::HasV8_1aOps},
798 {"cntp_ctl_el02", CNTP_CTL_EL02, AArch64::HasV8_1aOps},
799 {"cntp_cval_el02", CNTP_CVAL_EL02, AArch64::HasV8_1aOps},
800 {"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::HasV8_1aOps},
801 {"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::HasV8_1aOps},
802 {"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::HasV8_1aOps},
803 {"spsr_el12", SPSR_EL12, AArch64::HasV8_1aOps},
804 {"elr_el12", ELR_EL12, AArch64::HasV8_1aOps},
778 {"ttbr1_el2", TTBR1_EL2, {AArch64::HasV8_1aOps}},
779 {"contextidr_el2", CONTEXTIDR_EL2, {AArch64::HasV8_1aOps}},
780 {"cnthv_tval_el2", CNTHV_TVAL_EL2, {AArch64::HasV8_1aOps}},
781 {"cnthv_cval_el2", CNTHV_CVAL_EL2, {AArch64::HasV8_1aOps}},
782 {"cnthv_ctl_el2", CNTHV_CTL_EL2, {AArch64::HasV8_1aOps}},
783 {"sctlr_el12", SCTLR_EL12, {AArch64::HasV8_1aOps}},
784 {"cpacr_el12", CPACR_EL12, {AArch64::HasV8_1aOps}},
785 {"ttbr0_el12", TTBR0_EL12, {AArch64::HasV8_1aOps}},
786 {"ttbr1_el12", TTBR1_EL12, {AArch64::HasV8_1aOps}},
787 {"tcr_el12", TCR_EL12, {AArch64::HasV8_1aOps}},
788 {"afsr0_el12", AFSR0_EL12, {AArch64::HasV8_1aOps}},
789 {"afsr1_el12", AFSR1_EL12, {AArch64::HasV8_1aOps}},
790 {"esr_el12", ESR_EL12, {AArch64::HasV8_1aOps}},
791 {"far_el12", FAR_EL12, {AArch64::HasV8_1aOps}},
792 {"mair_el12", MAIR_EL12, {AArch64::HasV8_1aOps}},
793 {"amair_el12", AMAIR_EL12, {AArch64::HasV8_1aOps}},
794 {"vbar_el12", VBAR_EL12, {AArch64::HasV8_1aOps}},
795 {"contextidr_el12", CONTEXTIDR_EL12, {AArch64::HasV8_1aOps}},
796 {"cntkctl_el12", CNTKCTL_EL12, {AArch64::HasV8_1aOps}},
797 {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}},
798 {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}},
799 {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}},
800 {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}},
801 {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
802 {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
803 {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
804 {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
805805 };
806806
807807 uint32_t
808 AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits,
809 bool &Valid) const {
808 AArch64SysReg::SysRegMapper::fromString(StringRef Name,
809 const FeatureBitset& FeatureBits, bool &Valid) const {
810810 std::string NameLower = Name.lower();
811811
812812 // First search the registers shared by all
849849 }
850850
851851 std::string
852 AArch64SysReg::SysRegMapper::toString(uint32_t Bits, uint64_t FeatureBits) const {
852 AArch64SysReg::SysRegMapper::toString(uint32_t Bits,
853 const FeatureBitset& FeatureBits) const {
853854 // First search the registers shared by all
854855 for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
855856 if (SysRegMappings[i].isValueEqual(Bits, FeatureBits)) {
877878 }
878879
879880 const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
880 {"ipas2e1is", IPAS2E1IS, 0},
881 {"ipas2le1is", IPAS2LE1IS, 0},
882 {"vmalle1is", VMALLE1IS, 0},
883 {"alle2is", ALLE2IS, 0},
884 {"alle3is", ALLE3IS, 0},
885 {"vae1is", VAE1IS, 0},
886 {"vae2is", VAE2IS, 0},
887 {"vae3is", VAE3IS, 0},
888 {"aside1is", ASIDE1IS, 0},
889 {"vaae1is", VAAE1IS, 0},
890 {"alle1is", ALLE1IS, 0},
891 {"vale1is", VALE1IS, 0},
892 {"vale2is", VALE2IS, 0},
893 {"vale3is", VALE3IS, 0},
894 {"vmalls12e1is", VMALLS12E1IS, 0},
895 {"vaale1is", VAALE1IS, 0},
896 {"ipas2e1", IPAS2E1, 0},
897 {"ipas2le1", IPAS2LE1, 0},
898 {"vmalle1", VMALLE1, 0},
899 {"alle2", ALLE2, 0},
900 {"alle3", ALLE3, 0},
901 {"vae1", VAE1, 0},
902 {"vae2", VAE2, 0},
903 {"vae3", VAE3, 0},
904 {"aside1", ASIDE1, 0},
905 {"vaae1", VAAE1, 0},
906 {"alle1", ALLE1, 0},
907 {"vale1", VALE1, 0},
908 {"vale2", VALE2, 0},
909 {"vale3", VALE3, 0},
910 {"vmalls12e1", VMALLS12E1, 0},
911 {"vaale1", VAALE1, 0}
881 {"ipas2e1is", IPAS2E1IS, {}},
882 {"ipas2le1is", IPAS2LE1IS, {}},
883 {"vmalle1is", VMALLE1IS, {}},
884 {"alle2is", ALLE2IS, {}},
885 {"alle3is", ALLE3IS, {}},
886 {"vae1is", VAE1IS, {}},
887 {"vae2is", VAE2IS, {}},
888 {"vae3is", VAE3IS, {}},
889 {"aside1is", ASIDE1IS, {}},
890 {"vaae1is", VAAE1IS, {}},
891 {"alle1is", ALLE1IS, {}},
892 {"vale1is", VALE1IS, {}},
893 {"vale2is", VALE2IS, {}},
894 {"vale3is", VALE3IS, {}},
895 {"vmalls12e1is", VMALLS12E1IS, {}},
896 {"vaale1is", VAALE1IS, {}},
897 {"ipas2e1", IPAS2E1, {}},
898 {"ipas2le1", IPAS2LE1, {}},
899 {"vmalle1", VMALLE1, {}},
900 {"alle2", ALLE2, {}},
901 {"alle3", ALLE3, {}},
902 {"vae1", VAE1, {}},
903 {"vae2", VAE2, {}},
904 {"vae3", VAE3, {}},
905 {"aside1", ASIDE1, {}},
906 {"vaae1", VAAE1, {}},
907 {"alle1", ALLE1, {}},
908 {"vale1", VALE1, {}},
909 {"vale2", VALE2, {}},
910 {"vale3", VALE3, {}},
911 {"vmalls12e1", VMALLS12E1, {}},
912 {"vaale1", VAALE1, {}}
912913 };
913914
914915 AArch64TLBI::TLBIMapper::TLBIMapper()
2121 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
2222 #include "llvm/ADT/STLExtras.h"
2323 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/MC/SubtargetFeature.h"
2425 #include "llvm/Support/ErrorHandling.h"
2526
2627 namespace llvm {
279280 struct Mapping {
280281 const char *Name;
281282 uint32_t Value;
282 uint64_t AvailableForFeatures;
283 FeatureBitset AvailableForFeatures;
283284 // empty AvailableForFeatures means "always-on"
284 bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) const {
285 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
285 bool isNameEqual(std::string Other,
286 const FeatureBitset& FeatureBits) const {
287 if (AvailableForFeatures.any() &&
288 (AvailableForFeatures & FeatureBits).none())
286289 return false;
287290 return Name == Other;
288291 }
289 bool isValueEqual(uint32_t Other, uint64_t FeatureBits=~0ULL) const {
290 if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
292 bool isValueEqual(uint32_t Other,
293 const FeatureBitset& FeatureBits) const {
294 if (AvailableForFeatures.any() &&
295 (AvailableForFeatures & FeatureBits).none())
291296 return false;
292297 return Value == Other;
293298 }
297302 AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
298303 : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
299304
300 StringRef toString(uint32_t Value, uint64_t FeatureBits, bool &Valid) const;
301 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
305 StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
306 bool &Valid) const;
307 uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
308 bool &Valid) const;
302309
303310 /// Many of the instructions allow an alternative assembly form consisting of
304311 /// a simple immediate. Currently the only valid forms are ranges [0, N) where
11911198 size_t NumInstMappings;
11921199
11931200 SysRegMapper() { }
1194 uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
1195 std::string toString(uint32_t Bits, uint64_t FeatureBits) const;
1201 uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
1202 bool &Valid) const;
1203 std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const;
11961204 };
11971205
11981206 struct MSRMapper : SysRegMapper {
418418 }
419419
420420 static bool isThumb(const MCSubtargetInfo& STI) {
421 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
421 return STI.getFeatureBits()[ARM::ModeThumb];
422422 }
423423
424424 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
45384538 }
45394539
45404540 bool ARMBaseInstrInfo::hasNOP() const {
4541 return (Subtarget.getFeatureBits() & ARM::HasV6KOps) != 0;
4541 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
45424542 }
45434543
45444544 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
264264 }
265265
266266 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
267 uint64_t Bits = getFeatureBits();
268 if ((Bits & ARM::ProcA5 || Bits & ARM::ProcA8) && // Where this matters
267 const FeatureBitset &Bits = getFeatureBits();
268 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
269269 (Options.UnsafeFPMath || isTargetDarwin()))
270270 UseNEONForSinglePrecisionFP = true;
271271 }
242242
243243 bool isThumb() const {
244244 // FIXME: Can tablegen auto-generate this?
245 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
245 return STI.getFeatureBits()[ARM::ModeThumb];
246246 }
247247 bool isThumbOne() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
248 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
249249 }
250250 bool isThumbTwo() const {
251 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
251 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
252252 }
253253 bool hasThumb() const {
254 return STI.getFeatureBits() & ARM::HasV4TOps;
254 return STI.getFeatureBits()[ARM::HasV4TOps];
255255 }
256256 bool hasV6Ops() const {
257 return STI.getFeatureBits() & ARM::HasV6Ops;
257 return STI.getFeatureBits()[ARM::HasV6Ops];
258258 }
259259 bool hasV6MOps() const {
260 return STI.getFeatureBits() & ARM::HasV6MOps;
260 return STI.getFeatureBits()[ARM::HasV6MOps];
261261 }
262262 bool hasV7Ops() const {
263 return STI.getFeatureBits() & ARM::HasV7Ops;
263 return STI.getFeatureBits()[ARM::HasV7Ops];
264264 }
265265 bool hasV8Ops() const {
266 return STI.getFeatureBits() & ARM::HasV8Ops;
266 return STI.getFeatureBits()[ARM::HasV8Ops];
267267 }
268268 bool hasARM() const {
269 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
269 return !STI.getFeatureBits()[ARM::FeatureNoARM];
270270 }
271271 bool hasThumb2DSP() const {
272 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
272 return STI.getFeatureBits()[ARM::FeatureDSPThumb2];
273273 }
274274 bool hasD16() const {
275 return STI.getFeatureBits() & ARM::FeatureD16;
275 return STI.getFeatureBits()[ARM::FeatureD16];
276276 }
277277 bool hasV8_1aOps() const {
278 return STI.getFeatureBits() & ARM::HasV8_1aOps;
278 return STI.getFeatureBits()[ARM::HasV8_1aOps];
279279 }
280280
281281 void SwitchMode() {
283283 setAvailableFeatures(FB);
284284 }
285285 bool isMClass() const {
286 return STI.getFeatureBits() & ARM::FeatureMClass;
286 return STI.getFeatureBits()[ARM::FeatureMClass];
287287 }
288288
289289 /// @name Auto-generated Match Functions
91869186 // tools/clang/lib/Driver/Tools.cpp
91879187 static const struct {
91889188 const unsigned ID;
9189 const uint64_t Enabled;
9190 const uint64_t Disabled;
9189 const FeatureBitset Enabled;
9190 const FeatureBitset Disabled;
91919191 } FPUs[] = {
9192 {/* ID */ ARM::FK_VFP,
9193 /* Enabled */ ARM::FeatureVFP2,
9194 /* Disabled */ ARM::FeatureNEON},
9195 {/* ID */ ARM::FK_VFPV2,
9196 /* Enabled */ ARM::FeatureVFP2,
9197 /* Disabled */ ARM::FeatureNEON},
9198 {/* ID */ ARM::FK_VFPV3,
9199 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
9200 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9201 {/* ID */ ARM::FK_VFPV3_D16,
9202 /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
9203 /* Disabled */ ARM::FeatureNEON},
9204 {/* ID */ ARM::FK_VFPV4,
9205 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
9206 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9207 {/* ID */ ARM::FK_VFPV4_D16,
9208 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9209 ARM::FeatureD16,
9210 /* Disabled */ ARM::FeatureNEON},
9211 {/* ID */ ARM::FK_FPV5_D16,
9212 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9213 ARM::FeatureFPARMv8 | ARM::FeatureD16,
9214 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
9215 {/* ID */ ARM::FK_FP_ARMV8,
9216 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9217 ARM::FeatureFPARMv8,
9218 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
9219 {/* ID */ ARM::FK_NEON,
9220 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
9221 /* Disabled */ ARM::FeatureD16},
9222 {/* ID */ ARM::FK_NEON_VFPV4,
9223 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9224 ARM::FeatureNEON,
9225 /* Disabled */ ARM::FeatureD16},
9226 {/* ID */ ARM::FK_NEON_FP_ARMV8,
9227 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9228 ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9229 /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
9192 {/* ID */ ARM::FK_VFP,
9193 /* Enabled */ {ARM::FeatureVFP2},
9194 /* Disabled */ {ARM::FeatureNEON}},
9195 {/* ID */ ARM::FK_VFPV2,
9196 /* Enabled */ {ARM::FeatureVFP2},
9197 /* Disabled */ {ARM::FeatureNEON}},
9198 {/* ID */ ARM::FK_VFPV3,
9199 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3},
9200 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
9201 {/* ID */ ARM::FK_VFPV3_D16,
9202 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureD16},
9203 /* Disabled */ {ARM::FeatureNEON}},
9204 {/* ID */ ARM::FK_VFPV4,
9205 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4},
9206 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureD16}},
9207 {/* ID */ ARM::FK_VFPV4_D16,
9208 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9209 ARM::FeatureD16},
9210 /* Disabled */ {ARM::FeatureNEON}},
9211 {/* ID */ ARM::FK_FPV5_D16,
9212 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9213 ARM::FeatureFPARMv8, ARM::FeatureD16},
9214 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto}},
9215 {/* ID */ ARM::FK_FP_ARMV8,
9216 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9217 ARM::FeatureFPARMv8},
9218 /* Disabled */ {ARM::FeatureNEON, ARM::FeatureCrypto, ARM::FeatureD16}},
9219 {/* ID */ ARM::FK_NEON,
9220 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON},
9221 /* Disabled */ {ARM::FeatureD16}},
9222 {/* ID */ ARM::FK_NEON_VFPV4,
9223 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9224 ARM::FeatureNEON},
9225 /* Disabled */ {ARM::FeatureD16}},
9226 {/* ID */ ARM::FK_NEON_FP_ARMV8,
9227 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9228 ARM::FeatureFPARMv8, ARM::FeatureNEON},
9229 /* Disabled */ {ARM::FeatureCrypto, ARM::FeatureD16}},
92309230 {/* ID */ ARM::FK_CRYPTO_NEON_FP_ARMV8,
9231 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9232 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
9233 /* Disabled */ ARM::FeatureD16},
9234 {ARM::FK_SOFTVFP, 0, 0},
9231 /* Enabled */ {ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureVFP4,
9232 ARM::FeatureFPARMv8, ARM::FeatureNEON,
9233 ARM::FeatureCrypto},
9234 /* Disabled */ {ARM::FeatureD16}},
9235 {ARM::FK_SOFTVFP, {}, {}},
92359236 };
92369237
92379238 /// parseDirectiveFPU
92539254
92549255 // Need to toggle features that should be on but are off and that
92559256 // should off but are on.
9256 uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9257 (Entry.Disabled & STI.getFeatureBits());
9257 FeatureBitset Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9258 (Entry.Disabled & STI.getFeatureBits());
92589259 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
92599260 break;
92609261 }
99839984 static const struct {
99849985 const char *Name;
99859986 const unsigned ArchCheck;
9986 const uint64_t Features;
9987 const FeatureBitset Features;
99879988 } Extensions[] = {
9988 { "crc", Feature_HasV8, ARM::FeatureCRC },
9989 { "crc", Feature_HasV8, {ARM::FeatureCRC} },
99899990 { "crypto", Feature_HasV8,
9990 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9991 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9991 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9992 { "fp", Feature_HasV8, {ARM::FeatureFPARMv8} },
99929993 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9993 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9994 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
99949995 // FIXME: iWMMXT not supported
9995 { "iwmmxt", Feature_None, 0 },
9996 { "iwmmxt", Feature_None, {} },
99969997 // FIXME: iWMMXT2 not supported
9997 { "iwmmxt2", Feature_None, 0 },
9998 { "iwmmxt2", Feature_None, {} },
99989999 // FIXME: Maverick not supported
9999 { "maverick", Feature_None, 0 },
10000 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
10000 { "maverick", Feature_None, {} },
10001 { "mp", Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
1000110002 // FIXME: ARMv6-m OS Extensions feature not checked
10002 { "os", Feature_None, 0 },
10003 { "os", Feature_None, {} },
1000310004 // FIXME: Also available in ARMv6-K
10004 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
10005 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10005 { "sec", Feature_HasV7, {ARM::FeatureTrustZone} },
10006 { "simd", Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
1000610007 // FIXME: Only available in A-class, isel not predicated
10007 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
10008 { "virt", Feature_HasV7, {ARM::FeatureVirtualization} },
1000810009 // FIXME: xscale not supported
10009 { "xscale", Feature_None, 0 },
10010 { "xscale", Feature_None, {} },
1001010011 };
1001110012
1001210013 /// parseDirectiveArchExtension
1003410035 if (Extension.Name != Name)
1003510036 continue;
1003610037
10037 if (!Extension.Features)
10038 if (Extension.Features.none())
1003810039 report_fatal_error("unsupported architectural extension: " + Name);
1003910040
1004010041 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
1004310044 return false;
1004410045 }
1004510046
10046 uint64_t ToggleFeatures = EnableFeature
10047 ? (~STI.getFeatureBits() & Extension.Features)
10048 : ( STI.getFeatureBits() & Extension.Features);
10047 FeatureBitset ToggleFeatures = EnableFeature
10048 ? (~STI.getFeatureBits() & Extension.Features)
10049 : ( STI.getFeatureBits() & Extension.Features);
10050
1004910051 uint64_t Features =
1005010052 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
1005110053 setAvailableFeatures(Features);
434434 raw_ostream &CS) const {
435435 CommentStream = &CS;
436436
437 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
437 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
438438 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
439439 "mode!");
440440
699699 raw_ostream &CS) const {
700700 CommentStream = &CS;
701701
702 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
702 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
703703 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
704704
705705 // We want to read exactly 2 bytes of data.
10251025
10261026 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
10271027 uint64_t Address, const void *Decoder) {
1028 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1029 .getFeatureBits();
1030 bool hasD16 = featureBits & ARM::FeatureD16;
1028 const FeatureBitset &featureBits =
1029 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1030
1031 bool hasD16 = featureBits[ARM::FeatureD16];
10311032
10321033 if (RegNo > 31 || (hasD16 && RegNo > 15))
10331034 return MCDisassembler::Fail;
13721373 break;
13731374 }
13741375
1375 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1376 .getFeatureBits();
1377 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1376 const FeatureBitset &featureBits =
1377 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1378 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
13781379 return MCDisassembler::Fail;
13791380
13801381 Inst.addOperand(MCOperand::CreateImm(coproc));
21502151 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
21512152
21522153 const MCDisassembler *Dis = static_cast(Decoder);
2153 uint64_t FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2154 if ((FeatureBits & ARM::HasV8_1aOps) == 0 ||
2155 (FeatureBits & ARM::HasV8Ops) == 0 )
2154 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2155
2156 if (!FeatureBits[ARM::HasV8_1aOps] ||
2157 !FeatureBits[ARM::HasV8Ops])
21562158 return MCDisassembler::Fail;
21572159
21582160 // Decoder can be called from DecodeTST, which does not check the full
33183320 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
33193321 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
33203322
3321 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3322 .getFeatureBits();
3323 bool hasMP = featureBits & ARM::FeatureMP;
3324 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3323 const FeatureBitset &featureBits =
3324 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3325
3326 bool hasMP = featureBits[ARM::FeatureMP];
3327 bool hasV7Ops = featureBits[ARM::HasV7Ops];
33253328
33263329 if (Rn == 15) {
33273330 switch (Inst.getOpcode()) {
34043407 imm |= (Rn << 9);
34053408 unsigned add = fieldFromInstruction(Insn, 9, 1);
34063409
3407 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3408 .getFeatureBits();
3409 bool hasMP = featureBits & ARM::FeatureMP;
3410 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3410 const FeatureBitset &featureBits =
3411 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3412
3413 bool hasMP = featureBits[ARM::FeatureMP];
3414 bool hasV7Ops = featureBits[ARM::HasV7Ops];
34113415
34123416 if (Rn == 15) {
34133417 switch (Inst.getOpcode()) {
34843488 unsigned imm = fieldFromInstruction(Insn, 0, 12);
34853489 imm |= (Rn << 13);
34863490
3487 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3488 .getFeatureBits();
3489 bool hasMP = (featureBits & ARM::FeatureMP);
3490 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3491 const FeatureBitset &featureBits =
3492 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3493
3494 bool hasMP = featureBits[ARM::FeatureMP];
3495 bool hasV7Ops = featureBits[ARM::HasV7Ops];
34913496
34923497 if (Rn == 15) {
34933498 switch (Inst.getOpcode()) {
36013606 unsigned U = fieldFromInstruction(Insn, 23, 1);
36023607 int imm = fieldFromInstruction(Insn, 0, 12);
36033608
3604 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3605 .getFeatureBits();
3606 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3609 const FeatureBitset &featureBits =
3610 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3611
3612 bool hasV7Ops = featureBits[ARM::HasV7Ops];
36073613
36083614 if (Rt == 15) {
36093615 switch (Inst.getOpcode()) {
39243930 if (Val == 0xA || Val == 0xB)
39253931 return MCDisassembler::Fail;
39263932
3927 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3928 .getFeatureBits();
3929 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3933 const FeatureBitset &featureBits =
3934 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3935
3936 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
39303937 return MCDisassembler::Fail;
39313938
39323939 Inst.addOperand(MCOperand::CreateImm(Val));
40764083 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
40774084 uint64_t Address, const void *Decoder) {
40784085 DecodeStatus S = MCDisassembler::Success;
4079 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4080 .getFeatureBits();
4081 if (FeatureBits & ARM::FeatureMClass) {
4086 const FeatureBitset &FeatureBits =
4087 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4088
4089 if (FeatureBits[ARM::FeatureMClass]) {
40824090 unsigned ValLow = Val & 0xff;
40834091
40844092 // Validate the SYSm value first.
40984106 case 17: // basepri
40994107 case 18: // basepri_max
41004108 case 19: // faultmask
4101 if (!(FeatureBits & ARM::HasV7Ops))
4109 if (!(FeatureBits[ARM::HasV7Ops]))
41024110 // Values basepri, basepri_max and faultmask are only valid for v7m.
41034111 return MCDisassembler::Fail;
41044112 break;
41084116
41094117 if (Inst.getOpcode() == ARM::t2MSR_M) {
41104118 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4111 if (!(FeatureBits & ARM::HasV7Ops)) {
4119 if (!(FeatureBits[ARM::HasV7Ops])) {
41124120 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
41134121 // unpredictable.
41144122 if (Mask != 2)
41224130 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
41234131 // only if the processor includes the DSP extension.
41244132 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4125 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4133 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
41264134 S = MCDisassembler::SoftFail;
41274135 }
41284136 }
9292 O << "\tsev";
9393 break;
9494 case 5:
95 if ((STI.getFeatureBits() & ARM::HasV8Ops)) {
95 if (STI.getFeatureBits()[ARM::HasV8Ops]) {
9696 O << "\tsevl";
9797 break;
9898 } // Fallthrough for non-v8
301301 case ARM::t2SUBS_PC_LR: {
302302 if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
303303 MI->getOperand(0).getImm() == 0 &&
304 (STI.getFeatureBits() & ARM::FeatureVirtualization)) {
304 STI.getFeatureBits()[ARM::FeatureVirtualization]) {
305305 O << "\teret";
306306 printPredicateOperand(MI, 1, STI, O);
307307 printAnnotation(O, Annot);
694694 const MCSubtargetInfo &STI,
695695 raw_ostream &O) {
696696 unsigned val = MI->getOperand(OpNum).getImm();
697 O << ARM_MB::MemBOptToString(val, (STI.getFeatureBits() & ARM::HasV8Ops));
697 O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
698698 }
699699
700700 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
794794 const MCOperand &Op = MI->getOperand(OpNum);
795795 unsigned SpecRegRBit = Op.getImm() >> 4;
796796 unsigned Mask = Op.getImm() & 0xf;
797 uint64_t FeatureBits = STI.getFeatureBits();
798
799 if (FeatureBits & ARM::FeatureMClass) {
797 const FeatureBitset &FeatureBits = STI.getFeatureBits();
798
799 if (FeatureBits[ARM::FeatureMClass]) {
800800 unsigned SYSm = Op.getImm();
801801 unsigned Opcode = MI->getOpcode();
802802
803803 // For writes, handle extended mask bits if the DSP extension is present.
804 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
804 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) {
805805 switch (SYSm) {
806806 case 0x400:
807807 O << "apsr_g";
833833 // Handle the basic 8-bit mask.
834834 SYSm &= 0xff;
835835
836 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
836 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) {
837837 // ARMv7-M deprecates using MSR APSR without a _ qualifier as an
838838 // alias for MSR APSR_nzcvq.
839839 switch (SYSm) {
153153 } // end anonymous namespace
154154
155155 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
156 bool HasThumb2 = STI->getFeatureBits() & ARM::FeatureThumb2;
156 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
157157
158158 switch (Op) {
159159 default:
3232 return ARM::NumTargetFixupKinds;
3333 }
3434
35 bool hasNOP() const { return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; }
35 bool hasNOP() const { return STI->getFeatureBits()[ARM::HasV6T2Ops]; }
3636
3737 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
3838
5050 ~ARMMCCodeEmitter() override {}
5151
5252 bool isThumb(const MCSubtargetInfo &STI) const {
53 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
53 return STI.getFeatureBits()[ARM::ModeThumb];
5454 }
5555 bool isThumb2(const MCSubtargetInfo &STI) const {
56 return isThumb(STI) && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
56 return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
5757 }
5858 bool isTargetMachO(const MCSubtargetInfo &STI) const {
5959 Triple TT(STI.getTargetTriple());
3232
3333 static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
3434 std::string &Info) {
35 if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
35 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
3636 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
3737 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
3838 // Checks for the deprecated CP15ISB encoding:
6464
6565 static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
6666 std::string &Info) {
67 if (STI.getFeatureBits() & llvm::ARM::HasV8Ops && MI.getOperand(1).isImm() &&
67 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
6868 MI.getOperand(1).getImm() != 8) {
6969 Info = "applying IT instruction to more than one subsequent instruction is "
7070 "deprecated";
7676
7777 static bool getARMStoreDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
7878 std::string &Info) {
79 assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
79 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
8080 "cannot predicate thumb instructions");
8181
8282 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
9393
9494 static bool getARMLoadDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
9595 std::string &Info) {
96 assert((~STI.getFeatureBits() & llvm::ARM::ModeThumb) &&
96 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
9797 "cannot predicate thumb instructions");
9898
9999 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
7777 // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
7878 // The reason we need this mask is explained in the selectArch function.
7979 // FIXME: Ideally we would like TableGen to generate this information.
80 static const uint64_t AllArchRelatedMask =
81 Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 |
82 Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 |
83 Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 |
84 Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 |
85 Mips::FeatureMips32r3 | Mips::FeatureMips32r5 | Mips::FeatureMips32r6 |
86 Mips::FeatureMips64 | Mips::FeatureMips64r2 | Mips::FeatureMips64r3 |
87 Mips::FeatureMips64r5 | Mips::FeatureMips64r6 | Mips::FeatureCnMips |
88 Mips::FeatureFP64Bit | Mips::FeatureGP64Bit | Mips::FeatureNaN2008;
80 static const FeatureBitset AllArchRelatedMask;
8981
9082 private:
9183 unsigned ATReg;
9486 uint64_t Features;
9587 };
9688 }
89
90 const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
91 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
92 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
93 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
94 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
95 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
96 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
97 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
98 Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
99 };
97100
98101 namespace {
99102 class MipsAsmParser : public MCTargetAsmParser {
308311 // FeatureMipsGP64 | FeatureMips1)
309312 // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
310313 void selectArch(StringRef ArchFeature) {
311 uint64_t FeatureBits = STI.getFeatureBits();
314 FeatureBitset FeatureBits = STI.getFeatureBits();
312315 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
313316 STI.setFeatureBits(FeatureBits);
314317 setAvailableFeatures(
317320 }
318321
319322 void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
320 if (!(STI.getFeatureBits() & Feature)) {
323 if (!(STI.getFeatureBits()[Feature])) {
321324 setAvailableFeatures(
322325 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
323326 }
325328 }
326329
327330 void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
328 if (STI.getFeatureBits() & Feature) {
331 if (STI.getFeatureBits()[Feature]) {
329332 setAvailableFeatures(
330333 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
331334 }
372375 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
373376 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
374377
375 bool isGP64bit() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
376 bool isFP64bit() const { return STI.getFeatureBits() & Mips::FeatureFP64Bit; }
378 bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
379 bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
377380 const MipsABIInfo &getABI() const { return ABI; }
378381 bool isABI_N32() const { return ABI.IsN32(); }
379382 bool isABI_N64() const { return ABI.IsN64(); }
380383 bool isABI_O32() const { return ABI.IsO32(); }
381 bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; }
384 bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
382385
383386 bool useOddSPReg() const {
384 return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
387 return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
385388 }
386389
387390 bool inMicroMipsMode() const {
388 return STI.getFeatureBits() & Mips::FeatureMicroMips;
389 }
390 bool hasMips1() const { return STI.getFeatureBits() & Mips::FeatureMips1; }
391 bool hasMips2() const { return STI.getFeatureBits() & Mips::FeatureMips2; }
392 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
393 bool hasMips4() const { return STI.getFeatureBits() & Mips::FeatureMips4; }
394 bool hasMips5() const { return STI.getFeatureBits() & Mips::FeatureMips5; }
391 return STI.getFeatureBits()[Mips::FeatureMicroMips];
392 }
393 bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
394 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
395 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
396 bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
397 bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
395398 bool hasMips32() const {
396 return (STI.getFeatureBits() & Mips::FeatureMips32);
399 return STI.getFeatureBits()[Mips::FeatureMips32];
397400 }
398401 bool hasMips64() const {
399 return (STI.getFeatureBits() & Mips::FeatureMips64);
402 return STI.getFeatureBits()[Mips::FeatureMips64];
400403 }
401404 bool hasMips32r2() const {
402 return (STI.getFeatureBits() & Mips::FeatureMips32r2);
405 return STI.getFeatureBits()[Mips::FeatureMips32r2];
403406 }
404407 bool hasMips64r2() const {
405 return (STI.getFeatureBits() & Mips::FeatureMips64r2);
408 return STI.getFeatureBits()[Mips::FeatureMips64r2];
406409 }
407410 bool hasMips32r3() const {
408 return (STI.getFeatureBits() & Mips::FeatureMips32r3);
411 return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
409412 }
410413 bool hasMips64r3() const {
411 return (STI.getFeatureBits() & Mips::FeatureMips64r3);
414 return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
412415 }
413416 bool hasMips32r5() const {
414 return (STI.getFeatureBits() & Mips::FeatureMips32r5);
417 return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
415418 }
416419 bool hasMips64r5() const {
417 return (STI.getFeatureBits() & Mips::FeatureMips64r5);
420 return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
418421 }
419422 bool hasMips32r6() const {
420 return (STI.getFeatureBits() & Mips::FeatureMips32r6);
423 return STI.getFeatureBits()[Mips::FeatureMips32r6];
421424 }
422425 bool hasMips64r6() const {
423 return (STI.getFeatureBits() & Mips::FeatureMips64r6);
424 }
426 return STI.getFeatureBits()[Mips::FeatureMips64r6];
427 }
428
429 bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
430 bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
431 bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
425432 bool hasCnMips() const {
426 return (STI.getFeatureBits() & Mips::FeatureCnMips);
427 }
428 bool hasDSP() const { return (STI.getFeatureBits() & Mips::FeatureDSP); }
429 bool hasDSPR2() const { return (STI.getFeatureBits() & Mips::FeatureDSPR2); }
430 bool hasMSA() const { return (STI.getFeatureBits() & Mips::FeatureMSA); }
433 return (STI.getFeatureBits()[Mips::FeatureCnMips]);
434 }
431435
432436 bool inMips16Mode() const {
433 return STI.getFeatureBits() & Mips::FeatureMips16;
437 return STI.getFeatureBits()[Mips::FeatureMips16];
434438 }
435439
436440 bool useSoftFloat() const {
437 return (STI.getFeatureBits() & Mips::FeatureSoftFloat);
441 return STI.getFeatureBits()[Mips::FeatureSoftFloat];
438442 }
439443
440444 /// Warn if RegIndex is the same as the current AT.
3535 public:
3636 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
3737 : MCDisassembler(STI, Ctx),
38 IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
38 IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
3939 IsBigEndian(IsBigEndian) {}
4040
41 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
42 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
41 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
42 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
4343 bool hasMips32r6() const {
44 return STI.getFeatureBits() & Mips::FeatureMips32r6;
45 }
46
47 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
44 return STI.getFeatureBits()[Mips::FeatureMips32r6];
45 }
46
47 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
4848
4949 bool hasCOP3() const {
5050 // Only present in MIPS-I and MIPS-II
111111 }
112112
113113 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
114 return STI.getFeatureBits() & Mips::FeatureMicroMips;
114 return STI.getFeatureBits()[Mips::FeatureMicroMips];
115115 }
116116
117117 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
118 return STI.getFeatureBits() & Mips::FeatureMips32r6;
118 return STI.getFeatureBits()[Mips::FeatureMips32r6];
119119 }
120120
121121 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
385385 MCAssembler &MCA = getStreamer().getAssembler();
386386 Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
387387
388 uint64_t Features = STI.getFeatureBits();
388 const FeatureBitset &Features = STI.getFeatureBits();
389389
390390 // Set the header flags that we can in the constructor.
391391 // FIXME: This is a fairly terrible hack. We set the rest
401401 unsigned EFlags = MCA.getELFHeaderEFlags();
402402
403403 // Architecture
404 if (Features & Mips::FeatureMips64r6)
404 if (Features[Mips::FeatureMips64r6])
405405 EFlags |= ELF::EF_MIPS_ARCH_64R6;
406 else if (Features & Mips::FeatureMips64r2 ||
407 Features & Mips::FeatureMips64r3 ||
408 Features & Mips::FeatureMips64r5)
406 else if (Features[Mips::FeatureMips64r2] ||
407 Features[Mips::FeatureMips64r3] ||
408 Features[Mips::FeatureMips64r5])
409409 EFlags |= ELF::EF_MIPS_ARCH_64R2;
410 else if (Features & Mips::FeatureMips64)
410 else if (Features[Mips::FeatureMips64])
411411 EFlags |= ELF::EF_MIPS_ARCH_64;
412 else if (Features & Mips::FeatureMips5)
412 else if (Features[Mips::FeatureMips5])
413413 EFlags |= ELF::EF_MIPS_ARCH_5;
414 else if (Features & Mips::FeatureMips4)
414 else if (Features[Mips::FeatureMips4])
415415 EFlags |= ELF::EF_MIPS_ARCH_4;
416 else if (Features & Mips::FeatureMips3)
416 else if (Features[Mips::FeatureMips3])
417417 EFlags |= ELF::EF_MIPS_ARCH_3;
418 else if (Features & Mips::FeatureMips32r6)
418 else if (Features[Mips::FeatureMips32r6])
419419 EFlags |= ELF::EF_MIPS_ARCH_32R6;
420 else if (Features & Mips::FeatureMips32r2 ||
421 Features & Mips::FeatureMips32r3 ||
422 Features & Mips::FeatureMips32r5)
420 else if (Features[Mips::FeatureMips32r2] ||
421 Features[Mips::FeatureMips32r3] ||
422 Features[Mips::FeatureMips32r5])
423423 EFlags |= ELF::EF_MIPS_ARCH_32R2;
424 else if (Features & Mips::FeatureMips32)
424 else if (Features[Mips::FeatureMips32])
425425 EFlags |= ELF::EF_MIPS_ARCH_32;
426 else if (Features & Mips::FeatureMips2)
426 else if (Features[Mips::FeatureMips2])
427427 EFlags |= ELF::EF_MIPS_ARCH_2;
428428 else
429429 EFlags |= ELF::EF_MIPS_ARCH_1;
430430
431431 // Other options.
432 if (Features & Mips::FeatureNaN2008)
432 if (Features[Mips::FeatureNaN2008])
433433 EFlags |= ELF::EF_MIPS_NAN2008;
434434
435435 // -mabicalls and -mplt are not implemented but we should act as if they were
469469 DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment()));
470470 BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment()));
471471
472 uint64_t Features = STI.getFeatureBits();
472 const FeatureBitset &Features = STI.getFeatureBits();
473473
474474 // Update e_header flags. See the FIXME and comment above in
475475 // the constructor for a full rundown on this.
482482 else if (getABI().IsN32())
483483 EFlags |= ELF::EF_MIPS_ABI2;
484484
485 if (Features & Mips::FeatureGP64Bit) {
485 if (Features[Mips::FeatureGP64Bit]) {
486486 if (getABI().IsO32())
487487 EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
488 } else if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64)
488 } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
489489 EFlags |= ELF::EF_MIPS_32BITMODE;
490490
491491 // If we've set the cpic eflag and we're n64, go ahead and set the pic
16791679 // where th can be omitted when it is 0. dcbtst is the same. We take the
16801680 // server form to be the default, so swap the operands if we're parsing for
16811681 // an embedded core (they'll be swapped again upon printing).
1682 if ((STI.getFeatureBits() & PPC::FeatureBookE) != 0 &&
1682 if (STI.getFeatureBits()[PPC::FeatureBookE] &&
16831683 Operands.size() == 4 &&
16841684 (Name == "dcbt" || Name == "dcbtst")) {
16851685 std::swap(Operands[1], Operands[3]);
386386 uint32_t Inst =
387387 (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
388388
389 if ((STI.getFeatureBits() & PPC::FeatureQPX) != 0) {
389 if (STI.getFeatureBits()[PPC::FeatureQPX]) {
390390 DecodeStatus result =
391391 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
392392 if (result != MCDisassembler::Fail)
118118 O << "t";
119119 O << " ";
120120
121 bool IsBookE = (STI.getFeatureBits() & PPC::FeatureBookE) != 0;
121 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
122122 if (IsBookE && TH != 0 && TH != 16)
123123 O << (unsigned int) TH << ", ";
124124
320320 : MCTargetAsmParser(), STI(STI), MII(MII), Parser(_Parser),
321321 ForcedEncodingSize(0){
322322
323 if (!STI.getFeatureBits()) {
323 if (STI.getFeatureBits().none()) {
324324 // Set default features.
325325 STI.ToggleFeature("SOUTHERN_ISLANDS");
326326 }
9898 } else if (IS_VTX(Desc)) {
9999 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
100100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
101 if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) {
101 if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
102102 InstWord2 |= 1 << 19; // Mega-Fetch bit
103103 }
104104
131131 Emit((uint32_t) 0, OS);
132132 } else {
133133 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
134 if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
134 if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
135135 ((Desc.TSFlags & R600_InstFlag::OP1) ||
136136 Desc.TSFlags & R600_InstFlag::OP2)) {
137137 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
3434 #include "SparcGenAsmWriter.inc"
3535
3636 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
37 return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
37 return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
3838 }
3939
4040 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
260260 MCContext &Ctx, int64_t *Residue);
261261
262262 bool is64BitMode() const {
263 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
263 return STI.getFeatureBits()[X86::Mode64Bit];
264264 }
265265 bool is32BitMode() const {
266 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
266 return STI.getFeatureBits()[X86::Mode32Bit];
267267 }
268268 bool is16BitMode() const {
269 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
269 return STI.getFeatureBits()[X86::Mode16Bit];
270270 }
271271
272272 unsigned getPointerWidth() {
10711071 const bool hasCompilerRTSupport = T.isOSLinux();
10721072 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
10731073 MCOptions.SanitizeAddress) {
1074 if ((STI.getFeatureBits() & X86::Mode32Bit) != 0)
1074 if (STI.getFeatureBits()[X86::Mode32Bit] != 0)
10751075 return new X86AddressSanitizer32(STI);
1076 if ((STI.getFeatureBits() & X86::Mode64Bit) != 0)
1076 if (STI.getFeatureBits()[X86::Mode64Bit] != 0)
10771077 return new X86AddressSanitizer64(STI);
10781078 }
10791079 return new X86AsmInstrumentation(STI);
728728
729729 bool is64BitMode() const {
730730 // FIXME: Can tablegen auto-generate this?
731 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
731 return STI.getFeatureBits()[X86::Mode64Bit];
732732 }
733733 bool is32BitMode() const {
734734 // FIXME: Can tablegen auto-generate this?
735 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
735 return STI.getFeatureBits()[X86::Mode32Bit];
736736 }
737737 bool is16BitMode() const {
738738 // FIXME: Can tablegen auto-generate this?
739 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
740 }
741 void SwitchMode(uint64_t mode) {
742 uint64_t oldMode = STI.getFeatureBits() &
743 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit);
744 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(oldMode | mode));
739 return STI.getFeatureBits()[X86::Mode16Bit];
740 }
741 void SwitchMode(unsigned mode) {
742 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
743 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
744 unsigned FB = ComputeAvailableFeatures(
745 STI.ToggleFeature(OldMode.flip(mode)));
745746 setAvailableFeatures(FB);
746 assert(mode == (STI.getFeatureBits() &
747 (X86::Mode64Bit | X86::Mode32Bit | X86::Mode16Bit)));
747
748 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
748749 }
749750
750751 unsigned getPointerWidth() {
16951696 }
16961697
16971698 // rounding mode token
1698 if (STI.getFeatureBits() & X86::FeatureAVX512 &&
1699 if (STI.getFeatureBits()[X86::FeatureAVX512] &&
16991700 getLexer().is(AsmToken::LCurly))
17001701 return ParseRoundingModeOp(Start, End);
17011702
17531754 }
17541755 case AsmToken::LCurly:{
17551756 SMLoc Start = Parser.getTok().getLoc(), End;
1756 if (STI.getFeatureBits() & X86::FeatureAVX512)
1757 if (STI.getFeatureBits()[X86::FeatureAVX512])
17571758 return ParseRoundingModeOp(Start, End);
17581759 return ErrorOperand(Start, "unknown token in expression");
17591760 }
17631764 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
17641765 const MCParsedAsmOperand &Op) {
17651766 MCAsmParser &Parser = getParser();
1766 if(STI.getFeatureBits() & X86::FeatureAVX512) {
1767 if(STI.getFeatureBits()[X86::FeatureAVX512]) {
17671768 if (getLexer().is(AsmToken::LCurly)) {
17681769 // Eat "{" and mark the current place.
17691770 const SMLoc consumedToken = consumeToken();
7979 MCContext &Ctx,
8080 std::unique_ptr MII)
8181 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
82 switch (STI.getFeatureBits() &
83 (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {
84 case X86::Mode16Bit:
82 const FeatureBitset &FB = STI.getFeatureBits();
83 if (FB[X86::Mode16Bit]) {
8584 fMode = MODE_16BIT;
86 break;
87 case X86::Mode32Bit:
85 return;
86 } else if (FB[X86::Mode32Bit]) {
8887 fMode = MODE_32BIT;
89 break;
90 case X86::Mode64Bit:
88 return;
89 } else if (FB[X86::Mode64Bit]) {
9190 fMode = MODE_64BIT;
92 break;
93 default:
94 llvm_unreachable("Invalid CPU mode");
95 }
91 return;
92 }
93
94 llvm_unreachable("Invalid CPU mode");
9695 }
9796
9897 struct Region {
5656 // InstrInfo.td as soon as Requires clause is supported properly
5757 // for InstAlias.
5858 if (MI->getOpcode() == X86::CALLpcrel32 &&
59 (STI.getFeatureBits() & X86::Mode64Bit) != 0) {
59 (STI.getFeatureBits()[X86::Mode64Bit])) {
6060 OS << "\tcallq\t";
6161 printPCRelImm(MI, 0, OS);
6262 }
4141 ~X86MCCodeEmitter() override {}
4242
4343 bool is64BitMode(const MCSubtargetInfo &STI) const {
44 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
44 return STI.getFeatureBits()[X86::Mode64Bit];
4545 }
4646
4747 bool is32BitMode(const MCSubtargetInfo &STI) const {
48 return (STI.getFeatureBits() & X86::Mode32Bit) != 0;
48 return STI.getFeatureBits()[X86::Mode32Bit];
4949 }
5050
5151 bool is16BitMode(const MCSubtargetInfo &STI) const {
52 return (STI.getFeatureBits() & X86::Mode16Bit) != 0;
52 return STI.getFeatureBits()[X86::Mode16Bit];
5353 }
5454
5555 /// Is16BitMemOperand - Return true if the specified instruction has
2727 let Predicates = [Pred1, Pred2];
2828 }
2929
30 // CHECK: return ((Bits & arch::AssemblerCondition2));
30 // CHECK: return (Bits[arch::AssemblerCondition2]);
22472247 Info.AsmParser->getValueAsString("AsmParserClassName");
22482248
22492249 OS << "uint64_t " << Info.Target.getName() << ClassName << "::\n"
2250 << "ComputeAvailableFeatures(uint64_t FB) const {\n";
2250 << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
22512251 OS << " uint64_t Features = 0;\n";
22522252 for (const auto &SF : Info.SubtargetFeatures) {
22532253 const SubtargetFeatureInfo &SFI = SF.second;
22692269 Cond = Cond.substr(1);
22702270 }
22712271
2272 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")";
2272 OS << "(";
22732273 if (Neg)
2274 OS << " == 0";
2275 else
2276 OS << " != 0";
2277 OS << ")";
2274 OS << "!";
2275 OS << "FB[" << Info.Target.getName() << "::" << Cond << "])";
22782276
22792277 if (Comma.second.empty())
22802278 break;
26442642 OS << "#undef GET_ASSEMBLER_HEADER\n";
26452643 OS << " // This should be included into the middle of the declaration of\n";
26462644 OS << " // your subclasses implementation of MCTargetAsmParser.\n";
2647 OS << " uint64_t ComputeAvailableFeatures(uint64_t FeatureBits) const;\n";
2645 OS << " uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
26482646 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, "
26492647 << "unsigned Opcode,\n"
26502648 << " const OperandVector "
847847 // The predicate function is just a big switch statement based on the
848848 // input predicate index.
849849 OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, "
850 << "uint64_t Bits) {\n";
850 << "const FeatureBitset& Bits) {\n";
851851 Indentation += 2;
852852 if (!Predicates.empty()) {
853853 OS.indent(Indentation) << "switch (Idx) {\n";
11011101 static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
11021102 const std::string &PredicateNamespace) {
11031103 if (str[0] == '!')
1104 o << "!(Bits & " << PredicateNamespace << "::"
1105 << str.slice(1,str.size()) << ")";
1104 o << "!Bits[" << PredicateNamespace << "::"
1105 << str.slice(1,str.size()) << "]";
11061106 else
1107 o << "(Bits & " << PredicateNamespace << "::" << str << ")";
1107 o << "Bits[" << PredicateNamespace << "::" << str << "]";
11081108 }
11091109
11101110 bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
20112011 << " InsnType insn, uint64_t Address,\n"
20122012 << " const void *DisAsm,\n"
20132013 << " const MCSubtargetInfo &STI) {\n"
2014 << " uint64_t Bits = STI.getFeatureBits();\n"
2014 << " const FeatureBitset& Bits = STI.getFeatureBits();\n"
20152015 << "\n"
20162016 << " const uint8_t *Ptr = DecodeTable;\n"
20172017 << " uint32_t CurFieldValue = 0;\n"
548548 CodeGenTarget &Target = CDP.getTargetInfo();
549549 if (Inst.HasComplexDeprecationPredicate)
550550 // Emit a function pointer to the complex predicate method.
551 OS << ",0"
551 OS << ", { } "
552552 << ",&get" << Inst.DeprecatedReason << "DeprecationInfo";
553553 else if (!Inst.DeprecatedReason.empty())
554554 // Emit the Subtarget feature.
555 OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
556 << ",nullptr";
555 OS << ", { " << Target.getInstNamespace() << "::" << Inst.DeprecatedReason
556 << "} ,nullptr";
557557 else
558558 // Instruction isn't deprecated.
559 OS << ",0,nullptr";
559 OS << ", { } ,nullptr";
560560
561561 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
562562 }
1515 #include "llvm/ADT/STLExtras.h"
1616 #include "llvm/ADT/StringExtras.h"
1717 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/MC/SubtargetFeature.h"
1819 #include "llvm/Support/Debug.h"
1920 #include "llvm/Support/Format.h"
2021 #include "llvm/TableGen/Error.h"
6162 CodeGenSchedModels &SchedModels;
6263 std::string Target;
6364
64 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
65 void Enumeration(raw_ostream &OS, const char *ClassName);
6566 unsigned FeatureKeyValues(raw_ostream &OS);
6667 unsigned CPUKeyValues(raw_ostream &OS);
6768 void FormItineraryStageString(const std::string &Names,
111112 // Enumeration - Emit the specified class as an enumeration.
112113 //
113114 void SubtargetEmitter::Enumeration(raw_ostream &OS,
114 const char *ClassName,
115 bool isBits) {
115 const char *ClassName) {
116116 // Get all records of class and sort
117117 std::vector DefList = Records.getAllDerivedDefinitions(ClassName);
118118 std::sort(DefList.begin(), DefList.end(), LessRecord());
120120 unsigned N = DefList.size();
121121 if (N == 0)
122122 return;
123 if (N > 64)
124 PrintFatalError("Too many (> 64) subtarget features!");
123 if (N > MAX_SUBTARGET_FEATURES)
124 PrintFatalError("Too many subtarget features! Bump MAX_SUBTARGET_FEATURES.");
125125
126126 OS << "namespace " << Target << " {\n";
127127
134134 Record *Def = DefList[i];
135135
136136 // Get and emit name
137 OS << " " << Def->getName();
138
139 // If bit flags then emit expression (1 << i)
140 if (isBits) OS << " = " << " 1ULL << " << i;
141
142 // Depending on 'if more in the list' emit comma
137 OS << " " << Def->getName() << " = " << i;
143138 if (++i < N) OS << ",";
144139
145140 OS << "\n";
146141 }
147142
148 // Close enumeration
149 OS << "};\n";
150
151 OS << "}\n";
143 // Close enumeration and namespace
144 OS << "};\n}\n";
152145 }
153146
154147 //
182175
183176 if (CommandLineName.empty()) continue;
184177
185 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
178 // Emit as { "feature", "description", { featureEnum }, { i1 , i2 , ... , in } }
186179 OS << " { "
187180 << "\"" << CommandLineName << "\", "
188181 << "\"" << Desc << "\", "
189 << Target << "::" << Name << ", ";
182 << "{ " << Target << "::" << Name << " }, ";
190183
191184 const std::vector &ImpliesList =
192185 Feature->getValueAsListOfDefs("Implies");
193186
194187 if (ImpliesList.empty()) {
195 OS << "0ULL";
188 OS << "{ }";
196189 } else {
190 OS << "{ ";
197191 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
198192 OS << Target << "::" << ImpliesList[j]->getName();
199 if (++j < M) OS << " | ";
200 }
193 if (++j < M) OS << ", ";
194 }
195 OS << " }";
201196 }
202197
203198 OS << " }";
239234 const std::vector &FeatureList =
240235 Processor->getValueAsListOfDefs("Features");
241236
242 // Emit as { "cpu", "description", f1 | f2 | ... fn },
237 // Emit as { "cpu", "description", { f1 , f2 , ... fn } },
243238 OS << " { "
244239 << "\"" << Name << "\", "
245240 << "\"Select the " << Name << " processor\", ";
246241
247242 if (FeatureList.empty()) {
248 OS << "0ULL";
243 OS << "{ }";
249244 } else {
245 OS << "{ ";
250246 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
251247 OS << Target << "::" << FeatureList[j]->getName();
252 if (++j < M) OS << " | ";
253 }
254 }
255
256 // The "0" is for the "implies" section of this data structure.
257 OS << ", 0ULL }";
248 if (++j < M) OS << ", ";
249 }
250 OS << " }";
251 }
252
253 // The { } is for the "implies" section of this data structure.
254 OS << ", { } }";
258255
259256 // Depending on 'if more in the list' emit comma
260257 if (++i < N) OS << ",";
13821379 }
13831380
13841381 OS << " InitMCProcessorInfo(CPU, FS);\n"
1385 << " uint64_t Bits = getFeatureBits();\n";
1382 << " const FeatureBitset& Bits = getFeatureBits();\n";
13861383
13871384 for (unsigned i = 0; i < Features.size(); i++) {
13881385 // Next record
13921389 const std::string &Attribute = R->getValueAsString("Attribute");
13931390
13941391 if (Value=="true" || Value=="false")
1395 OS << " if ((Bits & " << Target << "::"
1396 << Instance << ") != 0) "
1392 OS << " if (Bits[" << Target << "::"
1393 << Instance << "]) "
13971394 << Attribute << " = " << Value << ";\n";
13981395 else
1399 OS << " if ((Bits & " << Target << "::"
1400 << Instance << ") != 0 && "
1396 OS << " if (Bits[" << Target << "::"
1397 << Instance << "] && "
14011398 << Attribute << " < " << Value << ") "
14021399 << Attribute << " = " << Value << ";\n";
14031400 }
14151412 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
14161413
14171414 OS << "namespace llvm {\n";
1418 Enumeration(OS, "SubtargetFeature", true);
1415 Enumeration(OS, "SubtargetFeature");
14191416 OS << "} // End llvm namespace \n";
14201417 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
14211418