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Merging r296645: (PR32253) Included an updated testcase ------------------------------------------------------------------------ [Hexagon] Fix lowering of formal arguments of type i1 On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@301550 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 2 years ago
3 changed file(s) with 28 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
255255 return false;
256256 }
257257
258 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
258 if (LocVT == MVT::i1) {
259 LocVT = MVT::i32;
260 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
259261 LocVT = MVT::i32;
260262 ValVT = MVT::i32;
261263 if (ArgFlags.isSExt())
11391141 EVT RegVT = VA.getLocVT();
11401142 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
11411143 RegVT == MVT::i32 || RegVT == MVT::f32) {
1142 unsigned VReg =
1144 unsigned VReg =
11431145 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
11441146 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1145 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1147 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1148 // Treat values of type MVT::i1 specially: they are passed in
1149 // registers of type i32, but they need to remain as values of
1150 // type i1 for consistency of the argument lowering.
1151 if (VA.getValVT() == MVT::i1) {
1152 // Generate a copy into a predicate register and use the value
1153 // of the register as the "InVal".
1154 unsigned PReg =
1155 RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
1156 SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1157 Copy.getValue(0));
1158 Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
1159 Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
1160 }
1161 InVals.push_back(Copy);
1162 Chain = Copy.getValue(1);
11461163 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
11471164 unsigned VReg =
11481165 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
0 ; RUN: llc -march=hexagon -debug-only=isel < %s
1 ; REQUIRES: asserts
2
3 define void @g(i1 %cond) {
4 ret void
5 }
66 ret i32 %1
77 }
88
9 ; CHECK: 00 40 00 85 85004000
9 ; CHECK: 00 40 40 85 85404000
1010 ; CHECK: 00 40 9f 52 529f4000
1111 ; CHECK: 00 60 01 74 74016000
12 ; CHECK: 00 e0 82 74 7482e000
12 ; CHECK: 00 e0 82 74 7482e000