llvm.org GIT mirror llvm / 129d6cd
[ARM] Add hardware build attributes in assembler In the assembler, we should emit build attributes based on the target selected with command-line options. This matches the GNU assembler's behaviour. We only do this for build attributes which describe the hardware that is expected to be available, not the ones that describe ABI compatibility. This is done by moving some of the attribute emission code to ARMTargetStreamer, so that it can be shared between the assembly and code-generation code paths. Since the assembler only creates a MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to check raw features, and not use the convenience functions in ARMSubtarget. If different attributes are later specified using the .eabi_attribute directive, then they will take precedence, as happens when the same .eabi_attribute is specified twice. This must be enabled by an option, because we don't want to do this when parsing inline assembly. The attributes would match the ones emitted at the start of the file, so wouldn't actually change the emitted object file, but the extra directives would be added to every inline assembly block when emitting assembly, which we'd like to avoid. The majority of the changes in the build-attributes.ll test are just re-ordering the directives, because the hardware attributes are now emitted before the ABI ones. However, I did fix one bug which I spotted: Tag_CPU_arch_profile was not being emitted for v6M. Differential revision: https://reviews.llvm.org/D31812 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300547 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 3 years ago
7 changed file(s) with 464 addition(s) and 398 deletion(s). Raw diff Collapse all Expand all
127127 virtual void emitArch(unsigned Arch);
128128 virtual void emitArchExtension(unsigned ArchExt);
129129 virtual void emitObjectArch(unsigned Arch);
130 void emitTargetAttributes(const MCSubtargetInfo &STI);
130131 virtual void finishAttributeSection();
131132 virtual void emitInst(uint32_t Inst, char Suffix = '\0');
132133
8383 ///
8484 void setFeatureBits(const FeatureBitset &FeatureBits_) {
8585 FeatureBits = FeatureBits_;
86 }
87
88 bool hasFeature(unsigned Feature) const {
89 return FeatureBits[Feature];
8690 }
8791
8892 protected:
588588 ATS.finishAttributeSection();
589589 }
590590
591 static bool isV8M(const ARMSubtarget *Subtarget) {
592 // Note that v8M Baseline is a subset of v6T2!
593 return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) ||
594 Subtarget->hasV8MMainlineOps();
595 }
596
597591 //===----------------------------------------------------------------------===//
598592 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
599593 // FIXME:
600594 // The following seem like one-off assembler flags, but they actually need
601595 // to appear in the .ARM.attributes section in ELF.
602596 // Instead of subclassing the MCELFStreamer, we do the work here.
603
604 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
605 const ARMSubtarget *Subtarget) {
606 if (CPU == "xscale")
607 return ARMBuildAttrs::v5TEJ;
608
609 if (Subtarget->hasV8Ops()) {
610 if (Subtarget->isRClass())
611 return ARMBuildAttrs::v8_R;
612 return ARMBuildAttrs::v8_A;
613 } else if (Subtarget->hasV8MMainlineOps())
614 return ARMBuildAttrs::v8_M_Main;
615 else if (Subtarget->hasV7Ops()) {
616 if (Subtarget->isMClass() && Subtarget->hasDSP())
617 return ARMBuildAttrs::v7E_M;
618 return ARMBuildAttrs::v7;
619 } else if (Subtarget->hasV6T2Ops())
620 return ARMBuildAttrs::v6T2;
621 else if (Subtarget->hasV8MBaselineOps())
622 return ARMBuildAttrs::v8_M_Base;
623 else if (Subtarget->hasV6MOps())
624 return ARMBuildAttrs::v6S_M;
625 else if (Subtarget->hasV6Ops())
626 return ARMBuildAttrs::v6;
627 else if (Subtarget->hasV5TEOps())
628 return ARMBuildAttrs::v5TE;
629 else if (Subtarget->hasV5TOps())
630 return ARMBuildAttrs::v5T;
631 else if (Subtarget->hasV4TOps())
632 return ARMBuildAttrs::v4T;
633 else
634 return ARMBuildAttrs::v4;
635 }
636597
637598 // Returns true if all functions have the same function attribute value.
638599 // It also returns true when the module has no functions.
670631 static_cast(TM);
671632 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
672633
673 const std::string &CPUString = STI.getCPUString();
674
675 if (!StringRef(CPUString).startswith("generic")) {
676 // FIXME: remove krait check when GNU tools support krait cpu
677 if (STI.isKrait()) {
678 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
679 // We consider krait as a "cortex-a9" + hwdiv CPU
680 // Enable hwdiv through ".arch_extension idiv"
681 if (STI.hasDivide() || STI.hasDivideInARMMode())
682 ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
683 } else
684 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
685 }
686
687 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
688
689 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
690 // profile is not applicable (e.g. pre v7, or cross-profile code)".
691 if (STI.hasV7Ops() || isV8M(&STI)) {
692 if (STI.isAClass()) {
693 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
694 ARMBuildAttrs::ApplicationProfile);
695 } else if (STI.isRClass()) {
696 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
697 ARMBuildAttrs::RealTimeProfile);
698 } else if (STI.isMClass()) {
699 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
700 ARMBuildAttrs::MicroControllerProfile);
701 }
702 }
703
704 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
705 STI.hasARMOps() ? ARMBuildAttrs::Allowed
706 : ARMBuildAttrs::Not_Allowed);
707 if (isV8M(&STI)) {
708 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
709 ARMBuildAttrs::AllowThumbDerived);
710 } else if (STI.isThumb1Only()) {
711 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
712 } else if (STI.hasThumb2()) {
713 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
714 ARMBuildAttrs::AllowThumb32);
715 }
716
717 if (STI.hasNEON()) {
718 /* NEON is not exactly a VFP architecture, but GAS emit one of
719 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
720 if (STI.hasFPARMv8()) {
721 if (STI.hasCrypto())
722 ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
723 else
724 ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
725 } else if (STI.hasVFP4())
726 ATS.emitFPU(ARM::FK_NEON_VFPV4);
727 else
728 ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
729 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
730 if (STI.hasV8Ops())
731 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
732 STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
733 ARMBuildAttrs::AllowNeonARMv8);
734 } else {
735 if (STI.hasFPARMv8())
736 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
737 // FPU, but there are two different names for it depending on the CPU.
738 ATS.emitFPU(STI.hasD16()
739 ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
740 : ARM::FK_FP_ARMV8);
741 else if (STI.hasVFP4())
742 ATS.emitFPU(STI.hasD16()
743 ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
744 : ARM::FK_VFPV4);
745 else if (STI.hasVFP3())
746 ATS.emitFPU(STI.hasD16()
747 // +d16
748 ? (STI.isFPOnlySP()
749 ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
750 : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
751 // -d16
752 : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
753 else if (STI.hasVFP2())
754 ATS.emitFPU(ARM::FK_VFPV2);
755 }
634 // Emit build attributes for the available hardware.
635 ATS.emitTargetAttributes(STI);
756636
757637 // RW data addressing.
758638 if (isPositionIndependent()) {
845725 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
846726 ARMBuildAttrs::AllowIEEE754);
847727
848 if (STI.allowsUnalignedMem())
849 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
850 ARMBuildAttrs::Allowed);
851 else
852 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
853 ARMBuildAttrs::Not_Allowed);
854
855728 // FIXME: add more flags to ARMBuildAttributes.h
856729 // 8-bytes alignment stuff.
857730 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
858731 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
859732
860 // ABI_HardFP_use attribute to indicate single precision FP.
861 if (STI.isFPOnlySP())
862 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
863 ARMBuildAttrs::HardFPSinglePrecision);
864
865733 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
866734 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
867735 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
868
869 // FIXME: Should we signal R9 usage?
870
871 if (STI.hasFP16())
872 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
873736
874737 // FIXME: To support emitting this build attribute as GCC does, the
875738 // -mfp16-format option and associated plumbing must be
877740 // attribute should be emitted with value 1.
878741 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
879742 ARMBuildAttrs::FP16FormatIEEE);
880
881 if (STI.hasMPExtension())
882 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
883
884 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
885 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
886 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
887 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
888 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
889 // otherwise, the default value (AllowDIVIfExists) applies.
890 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
891 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
892
893 if (STI.hasDSP() && isV8M(&STI))
894 ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
895743
896744 if (MMI) {
897745 if (const Module *SourceModule = MMI->getModule()) {
929777 else
930778 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
931779 ARMBuildAttrs::R9IsGPR);
932
933 if (STI.hasTrustZone() && STI.hasVirtualization())
934 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
935 ARMBuildAttrs::AllowTZVirtualization);
936 else if (STI.hasTrustZone())
937 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
938 ARMBuildAttrs::AllowTZ);
939 else if (STI.hasVirtualization())
940 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
941 ARMBuildAttrs::AllowVirtualization);
942780 }
943781
944782 //===----------------------------------------------------------------------===//
6666 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
6767 "Warn in ARM, emit implicit ITs in Thumb")));
6868
69 static cl::opt AddBuildAttributes("arm-add-build-attributes",
70 cl::init(false));
71
6972 class ARMOperand;
7073
7174 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
538541
539542 // Initialize the set of available features.
540543 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
544
545 // Add build attributes based on the selected target.
546 if (AddBuildAttributes)
547 getTargetStreamer().emitTargetAttributes(STI);
541548
542549 // Not in an ITBlock to start with.
543550 ITState.CurPosition = ~0U;
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "ARMTargetMachine.h"
1314 #include "llvm/MC/ConstantPools.h"
1415 #include "llvm/MC/MCExpr.h"
1516 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/Support/ARMBuildAttributes.h"
19 #include "llvm/Support/TargetParser.h"
1620
1721 using namespace llvm;
1822
7478 void
7579 ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
7680 void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
81
82 static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
83 if (STI.getCPU() == "xscale")
84 return ARMBuildAttrs::v5TEJ;
85
86 if (STI.hasFeature(ARM::HasV8Ops)) {
87 if (STI.hasFeature(ARM::FeatureRClass))
88 return ARMBuildAttrs::v8_R;
89 return ARMBuildAttrs::v8_A;
90 } else if (STI.hasFeature(ARM::HasV8MMainlineOps))
91 return ARMBuildAttrs::v8_M_Main;
92 else if (STI.hasFeature(ARM::HasV7Ops)) {
93 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
94 return ARMBuildAttrs::v7E_M;
95 return ARMBuildAttrs::v7;
96 } else if (STI.hasFeature(ARM::HasV6T2Ops))
97 return ARMBuildAttrs::v6T2;
98 else if (STI.hasFeature(ARM::HasV8MBaselineOps))
99 return ARMBuildAttrs::v8_M_Base;
100 else if (STI.hasFeature(ARM::HasV6MOps))
101 return ARMBuildAttrs::v6S_M;
102 else if (STI.hasFeature(ARM::HasV6Ops))
103 return ARMBuildAttrs::v6;
104 else if (STI.hasFeature(ARM::HasV5TEOps))
105 return ARMBuildAttrs::v5TE;
106 else if (STI.hasFeature(ARM::HasV5TOps))
107 return ARMBuildAttrs::v5T;
108 else if (STI.hasFeature(ARM::HasV4TOps))
109 return ARMBuildAttrs::v4T;
110 else
111 return ARMBuildAttrs::v4;
112 }
113
114 static bool isV8M(const MCSubtargetInfo &STI) {
115 // Note that v8M Baseline is a subset of v6T2!
116 return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
117 !STI.hasFeature(ARM::HasV6T2Ops)) ||
118 STI.hasFeature(ARM::HasV8MMainlineOps);
119 }
120
121 /// Emit the build attributes that only depend on the hardware that we expect
122 // /to be available, and not on the ABI, or any source-language choices.
123 void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
124 switchVendor("aeabi");
125
126 const StringRef CPUString = STI.getCPU();
127 if (!CPUString.empty() && !CPUString.startswith("generic")) {
128 // FIXME: remove krait check when GNU tools support krait cpu
129 if (STI.hasFeature(ARM::ProcKrait)) {
130 emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
131 // We consider krait as a "cortex-a9" + hwdiv CPU
132 // Enable hwdiv through ".arch_extension idiv"
133 if (STI.hasFeature(ARM::FeatureHWDiv) ||
134 STI.hasFeature(ARM::FeatureHWDivARM))
135 emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
136 } else {
137 emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
138 }
139 }
140
141 emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
142
143 if (STI.hasFeature(ARM::FeatureAClass)) {
144 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
145 ARMBuildAttrs::ApplicationProfile);
146 } else if (STI.hasFeature(ARM::FeatureRClass)) {
147 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
148 ARMBuildAttrs::RealTimeProfile);
149 } else if (STI.hasFeature(ARM::FeatureMClass)) {
150 emitAttribute(ARMBuildAttrs::CPU_arch_profile,
151 ARMBuildAttrs::MicroControllerProfile);
152 }
153
154 emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
155 ? ARMBuildAttrs::Not_Allowed
156 : ARMBuildAttrs::Allowed);
157
158 if (isV8M(STI)) {
159 emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
160 ARMBuildAttrs::AllowThumbDerived);
161 } else if (STI.hasFeature(ARM::FeatureThumb2)) {
162 emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
163 ARMBuildAttrs::AllowThumb32);
164 } else if (STI.hasFeature(ARM::HasV4TOps)) {
165 emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
166 }
167
168 if (STI.hasFeature(ARM::FeatureNEON)) {
169 /* NEON is not exactly a VFP architecture, but GAS emit one of
170 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
171 if (STI.hasFeature(ARM::FeatureFPARMv8)) {
172 if (STI.hasFeature(ARM::FeatureCrypto))
173 emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
174 else
175 emitFPU(ARM::FK_NEON_FP_ARMV8);
176 } else if (STI.hasFeature(ARM::FeatureVFP4))
177 emitFPU(ARM::FK_NEON_VFPV4);
178 else
179 emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
180 : ARM::FK_NEON);
181 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
182 if (STI.hasFeature(ARM::HasV8Ops))
183 emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
184 STI.hasFeature(ARM::HasV8_1aOps)
185 ? ARMBuildAttrs::AllowNeonARMv8_1a
186 : ARMBuildAttrs::AllowNeonARMv8);
187 } else {
188 if (STI.hasFeature(ARM::FeatureFPARMv8))
189 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
190 // FPU, but there are two different names for it depending on the CPU.
191 emitFPU(STI.hasFeature(ARM::FeatureD16)
192 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16
193 : ARM::FK_FPV5_D16)
194 : ARM::FK_FP_ARMV8);
195 else if (STI.hasFeature(ARM::FeatureVFP4))
196 emitFPU(STI.hasFeature(ARM::FeatureD16)
197 ? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16
198 : ARM::FK_VFPV4_D16)
199 : ARM::FK_VFPV4);
200 else if (STI.hasFeature(ARM::FeatureVFP3))
201 emitFPU(
202 STI.hasFeature(ARM::FeatureD16)
203 // +d16
204 ? (STI.hasFeature(ARM::FeatureVFPOnlySP)
205 ? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
206 : ARM::FK_VFPV3XD)
207 : (STI.hasFeature(ARM::FeatureFP16)
208 ? ARM::FK_VFPV3_D16_FP16
209 : ARM::FK_VFPV3_D16))
210 // -d16
211 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
212 : ARM::FK_VFPV3));
213 else if (STI.hasFeature(ARM::FeatureVFP2))
214 emitFPU(ARM::FK_VFPV2);
215 }
216
217 // ABI_HardFP_use attribute to indicate single precision FP.
218 if (STI.hasFeature(ARM::FeatureVFPOnlySP))
219 emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
220 ARMBuildAttrs::HardFPSinglePrecision);
221
222 if (STI.hasFeature(ARM::FeatureFP16))
223 emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
224
225 if (STI.hasFeature(ARM::FeatureMP))
226 emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
227
228 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
229 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
230 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
231 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
232 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
233 // otherwise, the default value (AllowDIVIfExists) applies.
234 if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
235 emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
236
237 if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
238 emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
239
240 if (STI.hasFeature(ARM::FeatureStrictAlign))
241 emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
242 ARMBuildAttrs::Not_Allowed);
243 else
244 emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
245 ARMBuildAttrs::Allowed);
246
247 if (STI.hasFeature(ARM::FeatureTrustZone) &&
248 STI.hasFeature(ARM::FeatureVirtualization))
249 emitAttribute(ARMBuildAttrs::Virtualization_use,
250 ARMBuildAttrs::AllowTZVirtualization);
251 else if (STI.hasFeature(ARM::FeatureTrustZone))
252 emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
253 else if (STI.hasFeature(ARM::FeatureVirtualization))
254 emitAttribute(ARMBuildAttrs::Virtualization_use,
255 ARMBuildAttrs::AllowVirtualization);
256 }
230230 ; V6: .eabi_attribute 6, 6
231231 ; V6: .eabi_attribute 8, 1
232232 ;; We assume round-to-nearest by default (matches GCC)
233 ; V6-NOT: .eabi_attribute 27
234 ; V6-NOT: .eabi_attribute 36
235 ; V6-NOT: .eabi_attribute 42
236 ; V6-NOT: .eabi_attribute 44
237 ; V6-NOT: .eabi_attribute 68
233238 ; V6-NOT: .eabi_attribute 19
234239 ;; The default choice made by llc is for a V6 CPU without an FPU.
235240 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
241246 ; V6: .eabi_attribute 23, 3
242247 ; V6: .eabi_attribute 24, 1
243248 ; V6: .eabi_attribute 25, 1
244 ; V6-NOT: .eabi_attribute 27
245249 ; V6-NOT: .eabi_attribute 28
246 ; V6-NOT: .eabi_attribute 36
247250 ; V6: .eabi_attribute 38, 1
248 ; V6-NOT: .eabi_attribute 42
249 ; V6-NOT: .eabi_attribute 44
250 ; V6-NOT: .eabi_attribute 68
251251
252252 ; V6-FAST-NOT: .eabi_attribute 19
253253 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
261261 ;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
262262 ;; V6-M, however we don't model the OS extension so this is fine.
263263 ; V6M: .eabi_attribute 6, 12
264 ; V6M-NOT: .eabi_attribute 7
264 ; V6M: .eabi_attribute 7, 77
265265 ; V6M: .eabi_attribute 8, 0
266266 ; V6M: .eabi_attribute 9, 1
267 ; V6M-NOT: .eabi_attribute 27
268 ; V6M-NOT: .eabi_attribute 36
269 ; V6M-NOT: .eabi_attribute 42
270 ; V6M-NOT: .eabi_attribute 44
271 ; V6M-NOT: .eabi_attribute 68
267272 ; V6M-NOT: .eabi_attribute 19
268273 ;; The default choice made by llc is for a V6M CPU without an FPU.
269274 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
275280 ; V6M: .eabi_attribute 23, 3
276281 ; V6M: .eabi_attribute 24, 1
277282 ; V6M: .eabi_attribute 25, 1
278 ; V6M-NOT: .eabi_attribute 27
279283 ; V6M-NOT: .eabi_attribute 28
280 ; V6M-NOT: .eabi_attribute 36
281284 ; V6M: .eabi_attribute 38, 1
282 ; V6M-NOT: .eabi_attribute 42
283 ; V6M-NOT: .eabi_attribute 44
284 ; V6M-NOT: .eabi_attribute 68
285285
286286 ; V6M-FAST-NOT: .eabi_attribute 19
287287 ;; Despite the V6M CPU having no FPU by default, we chose to flush to
297297 ; ARM1156T2F-S: .eabi_attribute 8, 1
298298 ; ARM1156T2F-S: .eabi_attribute 9, 2
299299 ; ARM1156T2F-S: .fpu vfpv2
300 ; ARM1156T2F-S-NOT: .eabi_attribute 27
301 ; ARM1156T2F-S-NOT: .eabi_attribute 36
302 ; ARM1156T2F-S-NOT: .eabi_attribute 42
303 ; ARM1156T2F-S-NOT: .eabi_attribute 44
304 ; ARM1156T2F-S-NOT: .eabi_attribute 68
300305 ; ARM1156T2F-S-NOT: .eabi_attribute 19
301306 ;; We default to IEEE 754 compliance
302307 ; ARM1156T2F-S: .eabi_attribute 20, 1
305310 ; ARM1156T2F-S: .eabi_attribute 23, 3
306311 ; ARM1156T2F-S: .eabi_attribute 24, 1
307312 ; ARM1156T2F-S: .eabi_attribute 25, 1
308 ; ARM1156T2F-S-NOT: .eabi_attribute 27
309313 ; ARM1156T2F-S-NOT: .eabi_attribute 28
310 ; ARM1156T2F-S-NOT: .eabi_attribute 36
311314 ; ARM1156T2F-S: .eabi_attribute 38, 1
312 ; ARM1156T2F-S-NOT: .eabi_attribute 42
313 ; ARM1156T2F-S-NOT: .eabi_attribute 44
314 ; ARM1156T2F-S-NOT: .eabi_attribute 68
315315
316316 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 19
317317 ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
326326 ; V7M: .eabi_attribute 7, 77
327327 ; V7M: .eabi_attribute 8, 0
328328 ; V7M: .eabi_attribute 9, 2
329 ; V7M-NOT: .eabi_attribute 27
330 ; V7M-NOT: .eabi_attribute 36
331 ; V7M-NOT: .eabi_attribute 42
332 ; V7M-NOT: .eabi_attribute 44
333 ; V7M-NOT: .eabi_attribute 68
329334 ; V7M-NOT: .eabi_attribute 19
330335 ;; The default choice made by llc is for a V7M CPU without an FPU.
331336 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
337342 ; V7M: .eabi_attribute 23, 3
338343 ; V7M: .eabi_attribute 24, 1
339344 ; V7M: .eabi_attribute 25, 1
340 ; V7M-NOT: .eabi_attribute 27
341345 ; V7M-NOT: .eabi_attribute 28
342 ; V7M-NOT: .eabi_attribute 36
343346 ; V7M: .eabi_attribute 38, 1
344 ; V7M-NOT: .eabi_attribute 42
345 ; V7M-NOT: .eabi_attribute 44
346 ; V7M-NOT: .eabi_attribute 68
347347
348348 ; V7M-FAST-NOT: .eabi_attribute 19
349349 ;; Despite the V7M CPU having no FPU by default, we chose to flush
356356
357357 ; V7: .syntax unified
358358 ; V7: .eabi_attribute 6, 10
359 ; V7-NOT: .eabi_attribute 27
360 ; V7-NOT: .eabi_attribute 36
361 ; V7-NOT: .eabi_attribute 42
362 ; V7-NOT: .eabi_attribute 44
363 ; V7-NOT: .eabi_attribute 68
359364 ; V7-NOT: .eabi_attribute 19
360365 ;; In safe-maths mode we default to an IEEE 754 compliant choice.
361366 ; V7: .eabi_attribute 20, 1
364369 ; V7: .eabi_attribute 23, 3
365370 ; V7: .eabi_attribute 24, 1
366371 ; V7: .eabi_attribute 25, 1
367 ; V7-NOT: .eabi_attribute 27
368372 ; V7-NOT: .eabi_attribute 28
369 ; V7-NOT: .eabi_attribute 36
370373 ; V7: .eabi_attribute 38, 1
371 ; V7-NOT: .eabi_attribute 42
372 ; V7-NOT: .eabi_attribute 44
373 ; V7-NOT: .eabi_attribute 68
374374
375375 ; V7-FAST-NOT: .eabi_attribute 19
376376 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
385385 ; V7VE: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
386386 ; V7VE: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
387387 ; V7VE: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
388 ; V7VE: .eabi_attribute 42, 1 @ Tag_MPextension_use
389 ; V7VE: .eabi_attribute 44, 2 @ Tag_DIV_use
390 ; V7VE: .eabi_attribute 68, 3 @ Tag_Virtualization_use
388391 ; V7VE: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use
389392 ; V7VE: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
390393 ; V7VE: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
392395 ; V7VE: .eabi_attribute 24, 1 @ Tag_ABI_align_needed
393396 ; V7VE: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
394397 ; V7VE: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
395 ; V7VE: .eabi_attribute 42, 1 @ Tag_MPextension_use
396 ; V7VE: .eabi_attribute 44, 2 @ Tag_DIV_use
397 ; V7VE: .eabi_attribute 68, 3 @ Tag_Virtualization_use
398398
399399 ; V8: .syntax unified
400400 ; V8: .eabi_attribute 67, "2.09"
401401 ; V8: .eabi_attribute 6, 14
402 ; V8-NOT: .eabi_attribute 44
402403 ; V8-NOT: .eabi_attribute 19
403404 ; V8: .eabi_attribute 20, 1
404405 ; V8: .eabi_attribute 21, 1
405406 ; V8-NOT: .eabi_attribute 22
406407 ; V8: .eabi_attribute 23, 3
407 ; V8-NOT: .eabi_attribute 44
408408
409409 ; V8-FAST-NOT: .eabi_attribute 19
410410 ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
495495 ; CORTEX-A7-FPUV4: .fpu vfpv4
496496
497497 ; CORTEX-A7-CHECK-NOT: .eabi_attribute 19
498
499 ; Tag_FP_HP_extension
500 ; CORTEX-A7-CHECK: .eabi_attribute 36, 1
501 ; CORTEX-A7-NOFPU-NOT: .eabi_attribute 36
502 ; CORTEX-A7-FPUV4: .eabi_attribute 36, 1
503
504 ; Tag_MPextension_use
505 ; CORTEX-A7-CHECK: .eabi_attribute 42, 1
506 ; CORTEX-A7-NOFPU: .eabi_attribute 42, 1
507 ; CORTEX-A7-FPUV4: .eabi_attribute 42, 1
508
509 ; Tag_DIV_use
510 ; CORTEX-A7-CHECK: .eabi_attribute 44, 2
511 ; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
512 ; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
513
514 ; Tag_DSP_extension
515 ; CORTEX-A7-CHECK-NOT: .eabi_attribute 46
516
517 ; Tag_Virtualization_use
518 ; CORTEX-A7-CHECK: .eabi_attribute 68, 3
519 ; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
520 ; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
521
498522 ; Tag_ABI_FP_denormal
499523 ;; We default to IEEE 754 compliance
500524 ; CORTEX-A7-CHECK: .eabi_attribute 20, 1
534558 ; CORTEX-A7-NOFPU: .eabi_attribute 25, 1
535559 ; CORTEX-A7-FPUV4: .eabi_attribute 25, 1
536560
537 ; Tag_FP_HP_extension
538 ; CORTEX-A7-CHECK: .eabi_attribute 36, 1
539 ; CORTEX-A7-NOFPU-NOT: .eabi_attribute 36
540 ; CORTEX-A7-FPUV4: .eabi_attribute 36, 1
541
542561 ; Tag_FP_16bit_format
543562 ; CORTEX-A7-CHECK: .eabi_attribute 38, 1
544563 ; CORTEX-A7-NOFPU: .eabi_attribute 38, 1
545564 ; CORTEX-A7-FPUV4: .eabi_attribute 38, 1
546
547 ; Tag_MPextension_use
548 ; CORTEX-A7-CHECK: .eabi_attribute 42, 1
549 ; CORTEX-A7-NOFPU: .eabi_attribute 42, 1
550 ; CORTEX-A7-FPUV4: .eabi_attribute 42, 1
551
552 ; Tag_DIV_use
553 ; CORTEX-A7-CHECK: .eabi_attribute 44, 2
554 ; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
555 ; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
556
557 ; Tag_DSP_extension
558 ; CORTEX-A7-CHECK-NOT: .eabi_attribute 46
559
560 ; Tag_Virtualization_use
561 ; CORTEX-A7-CHECK: .eabi_attribute 68, 3
562 ; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
563 ; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
564565
565566 ; CORTEX-A5-DEFAULT: .cpu cortex-a5
566567 ; CORTEX-A5-DEFAULT: .eabi_attribute 6, 10
568569 ; CORTEX-A5-DEFAULT: .eabi_attribute 8, 1
569570 ; CORTEX-A5-DEFAULT: .eabi_attribute 9, 2
570571 ; CORTEX-A5-DEFAULT: .fpu neon-vfpv4
572 ; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1
573 ; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44
574 ; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
571575 ; CORTEX-A5-NOT: .eabi_attribute 19
572576 ;; We default to IEEE 754 compliance
573577 ; CORTEX-A5-DEFAULT: .eabi_attribute 20, 1
576580 ; CORTEX-A5-DEFAULT: .eabi_attribute 23, 3
577581 ; CORTEX-A5-DEFAULT: .eabi_attribute 24, 1
578582 ; CORTEX-A5-DEFAULT: .eabi_attribute 25, 1
579 ; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1
580 ; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44
581 ; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
582583
583584 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19
584585 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
594595 ; CORTEX-A5-NONEON: .eabi_attribute 8, 1
595596 ; CORTEX-A5-NONEON: .eabi_attribute 9, 2
596597 ; CORTEX-A5-NONEON: .fpu vfpv4-d16
598 ; CORTEX-A5-NONEON: .eabi_attribute 42, 1
599 ; CORTEX-A5-NONEON: .eabi_attribute 68, 1
597600 ;; We default to IEEE 754 compliance
598601 ; CORTEX-A5-NONEON: .eabi_attribute 20, 1
599602 ; CORTEX-A5-NONEON: .eabi_attribute 21, 1
601604 ; CORTEX-A5-NONEON: .eabi_attribute 23, 3
602605 ; CORTEX-A5-NONEON: .eabi_attribute 24, 1
603606 ; CORTEX-A5-NONEON: .eabi_attribute 25, 1
604 ; CORTEX-A5-NONEON: .eabi_attribute 42, 1
605 ; CORTEX-A5-NONEON: .eabi_attribute 68, 1
606607
607608 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 19
608609 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
618619 ; CORTEX-A5-NOFPU: .eabi_attribute 8, 1
619620 ; CORTEX-A5-NOFPU: .eabi_attribute 9, 2
620621 ; CORTEX-A5-NOFPU-NOT: .fpu
622 ; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
623 ; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
621624 ; CORTEX-A5-NOFPU-NOT: .eabi_attribute 19
622625 ;; We default to IEEE 754 compliance
623626 ; CORTEX-A5-NOFPU: .eabi_attribute 20, 1
626629 ; CORTEX-A5-NOFPU: .eabi_attribute 23, 3
627630 ; CORTEX-A5-NOFPU: .eabi_attribute 24, 1
628631 ; CORTEX-A5-NOFPU: .eabi_attribute 25, 1
629 ; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
630 ; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
631632
632633 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 19
633634 ;; Despite there being no FPU, we chose to flush to zero preserving
644645 ; CORTEX-A8-SOFT: .eabi_attribute 8, 1
645646 ; CORTEX-A8-SOFT: .eabi_attribute 9, 2
646647 ; CORTEX-A8-SOFT: .fpu neon
648 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 27
649 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 36, 1
650 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 42, 1
651 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 44
652 ; CORTEX-A8-SOFT: .eabi_attribute 68, 1
647653 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 19
648654 ;; We default to IEEE 754 compliance
649655 ; CORTEX-A8-SOFT: .eabi_attribute 20, 1
652658 ; CORTEX-A8-SOFT: .eabi_attribute 23, 3
653659 ; CORTEX-A8-SOFT: .eabi_attribute 24, 1
654660 ; CORTEX-A8-SOFT: .eabi_attribute 25, 1
655 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 27
656661 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 28
657 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 36, 1
658662 ; CORTEX-A8-SOFT: .eabi_attribute 38, 1
659 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 42, 1
660 ; CORTEX-A8-SOFT-NOT: .eabi_attribute 44
661 ; CORTEX-A8-SOFT: .eabi_attribute 68, 1
662663
663664 ; CORTEX-A9-SOFT: .cpu cortex-a9
664665 ; CORTEX-A9-SOFT: .eabi_attribute 6, 10
666667 ; CORTEX-A9-SOFT: .eabi_attribute 8, 1
667668 ; CORTEX-A9-SOFT: .eabi_attribute 9, 2
668669 ; CORTEX-A9-SOFT: .fpu neon
670 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
671 ; CORTEX-A9-SOFT: .eabi_attribute 36, 1
672 ; CORTEX-A9-SOFT: .eabi_attribute 42, 1
673 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 44
674 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1
669675 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 19
670676 ;; We default to IEEE 754 compliance
671677 ; CORTEX-A9-SOFT: .eabi_attribute 20, 1
674680 ; CORTEX-A9-SOFT: .eabi_attribute 23, 3
675681 ; CORTEX-A9-SOFT: .eabi_attribute 24, 1
676682 ; CORTEX-A9-SOFT: .eabi_attribute 25, 1
677 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
678683 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
679 ; CORTEX-A9-SOFT: .eabi_attribute 36, 1
680684 ; CORTEX-A9-SOFT: .eabi_attribute 38, 1
681 ; CORTEX-A9-SOFT: .eabi_attribute 42, 1
682 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 44
683 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1
684685
685686 ; CORTEX-A8-SOFT-FAST-NOT: .eabi_attribute 19
686687 ; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19
698699 ; CORTEX-A8-HARD: .eabi_attribute 8, 1
699700 ; CORTEX-A8-HARD: .eabi_attribute 9, 2
700701 ; CORTEX-A8-HARD: .fpu neon
702 ; CORTEX-A8-HARD-NOT: .eabi_attribute 27
703 ; CORTEX-A8-HARD-NOT: .eabi_attribute 36, 1
704 ; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1
705 ; CORTEX-A8-HARD: .eabi_attribute 68, 1
701706 ; CORTEX-A8-HARD-NOT: .eabi_attribute 19
702707 ;; We default to IEEE 754 compliance
703708 ; CORTEX-A8-HARD: .eabi_attribute 20, 1
706711 ; CORTEX-A8-HARD: .eabi_attribute 23, 3
707712 ; CORTEX-A8-HARD: .eabi_attribute 24, 1
708713 ; CORTEX-A8-HARD: .eabi_attribute 25, 1
709 ; CORTEX-A8-HARD-NOT: .eabi_attribute 27
710714 ; CORTEX-A8-HARD: .eabi_attribute 28, 1
711 ; CORTEX-A8-HARD-NOT: .eabi_attribute 36, 1
712715 ; CORTEX-A8-HARD: .eabi_attribute 38, 1
713 ; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1
714 ; CORTEX-A8-HARD: .eabi_attribute 68, 1
715716
716717
717718
721722 ; CORTEX-A9-HARD: .eabi_attribute 8, 1
722723 ; CORTEX-A9-HARD: .eabi_attribute 9, 2
723724 ; CORTEX-A9-HARD: .fpu neon
725 ; CORTEX-A9-HARD-NOT: .eabi_attribute 27
726 ; CORTEX-A9-HARD: .eabi_attribute 36, 1
727 ; CORTEX-A9-HARD: .eabi_attribute 42, 1
728 ; CORTEX-A9-HARD: .eabi_attribute 68, 1
724729 ; CORTEX-A9-HARD-NOT: .eabi_attribute 19
725730 ;; We default to IEEE 754 compliance
726731 ; CORTEX-A9-HARD: .eabi_attribute 20, 1
729734 ; CORTEX-A9-HARD: .eabi_attribute 23, 3
730735 ; CORTEX-A9-HARD: .eabi_attribute 24, 1
731736 ; CORTEX-A9-HARD: .eabi_attribute 25, 1
732 ; CORTEX-A9-HARD-NOT: .eabi_attribute 27
733737 ; CORTEX-A9-HARD: .eabi_attribute 28, 1
734 ; CORTEX-A9-HARD: .eabi_attribute 36, 1
735738 ; CORTEX-A9-HARD: .eabi_attribute 38, 1
736 ; CORTEX-A9-HARD: .eabi_attribute 42, 1
737 ; CORTEX-A9-HARD: .eabi_attribute 68, 1
738739
739740 ; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 19
740741 ;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
758759 ; CORTEX-A12-DEFAULT: .eabi_attribute 8, 1
759760 ; CORTEX-A12-DEFAULT: .eabi_attribute 9, 2
760761 ; CORTEX-A12-DEFAULT: .fpu neon-vfpv4
762 ; CORTEX-A12-DEFAULT: .eabi_attribute 42, 1
763 ; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
764 ; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
761765 ; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 19
762766 ;; We default to IEEE 754 compliance
763767 ; CORTEX-A12-DEFAULT: .eabi_attribute 20, 1
766770 ; CORTEX-A12-DEFAULT: .eabi_attribute 23, 3
767771 ; CORTEX-A12-DEFAULT: .eabi_attribute 24, 1
768772 ; CORTEX-A12-DEFAULT: .eabi_attribute 25, 1
769 ; CORTEX-A12-DEFAULT: .eabi_attribute 42, 1
770 ; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
771 ; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
772773
773774 ; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19
774775 ;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
784785 ; CORTEX-A12-NOFPU: .eabi_attribute 8, 1
785786 ; CORTEX-A12-NOFPU: .eabi_attribute 9, 2
786787 ; CORTEX-A12-NOFPU-NOT: .fpu
788 ; CORTEX-A12-NOFPU: .eabi_attribute 42, 1
789 ; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
790 ; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
787791 ; CORTEX-A12-NOFPU-NOT: .eabi_attribute 19
788792 ;; We default to IEEE 754 compliance
789793 ; CORTEX-A12-NOFPU: .eabi_attribute 20, 1
792796 ; CORTEX-A12-NOFPU: .eabi_attribute 23, 3
793797 ; CORTEX-A12-NOFPU: .eabi_attribute 24, 1
794798 ; CORTEX-A12-NOFPU: .eabi_attribute 25, 1
795 ; CORTEX-A12-NOFPU: .eabi_attribute 42, 1
796 ; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
797 ; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
798799
799800 ; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 19
800801 ;; Despite there being no FPU, we chose to flush to zero preserving
811812 ; CORTEX-A15: .eabi_attribute 8, 1
812813 ; CORTEX-A15: .eabi_attribute 9, 2
813814 ; CORTEX-A15: .fpu neon-vfpv4
815 ; CORTEX-A15-NOT: .eabi_attribute 27
816 ; CORTEX-A15: .eabi_attribute 36, 1
817 ; CORTEX-A15: .eabi_attribute 42, 1
818 ; CORTEX-A15: .eabi_attribute 44, 2
819 ; CORTEX-A15: .eabi_attribute 68, 3
814820 ; CORTEX-A15-NOT: .eabi_attribute 19
815821 ;; We default to IEEE 754 compliance
816822 ; CORTEX-A15: .eabi_attribute 20, 1
819825 ; CORTEX-A15: .eabi_attribute 23, 3
820826 ; CORTEX-A15: .eabi_attribute 24, 1
821827 ; CORTEX-A15: .eabi_attribute 25, 1
822 ; CORTEX-A15-NOT: .eabi_attribute 27
823828 ; CORTEX-A15-NOT: .eabi_attribute 28
824 ; CORTEX-A15: .eabi_attribute 36, 1
825829 ; CORTEX-A15: .eabi_attribute 38, 1
826 ; CORTEX-A15: .eabi_attribute 42, 1
827 ; CORTEX-A15: .eabi_attribute 44, 2
828 ; CORTEX-A15: .eabi_attribute 68, 3
829830
830831 ; CORTEX-A15-FAST-NOT: .eabi_attribute 19
831832 ;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
841842 ; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1
842843 ; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2
843844 ; CORTEX-A17-DEFAULT: .fpu neon-vfpv4
845 ; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
846 ; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
847 ; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
844848 ; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 19
845849 ;; We default to IEEE 754 compliance
846850 ; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1
849853 ; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3
850854 ; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1
851855 ; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1
852 ; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
853 ; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
854 ; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
855856
856857 ; CORTEX-A17-FAST-NOT: .eabi_attribute 19
857858 ;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
867868 ; CORTEX-A17-NOFPU: .eabi_attribute 8, 1
868869 ; CORTEX-A17-NOFPU: .eabi_attribute 9, 2
869870 ; CORTEX-A17-NOFPU-NOT: .fpu
871 ; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
872 ; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
873 ; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
870874 ; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
871875 ;; We default to IEEE 754 compliance
872876 ; CORTEX-A17-NOFPU: .eabi_attribute 20, 1
875879 ; CORTEX-A17-NOFPU: .eabi_attribute 23, 3
876880 ; CORTEX-A17-NOFPU: .eabi_attribute 24, 1
877881 ; CORTEX-A17-NOFPU: .eabi_attribute 25, 1
878 ; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
879 ; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
880 ; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
881882
882883 ; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
883884 ;; Despite there being no FPU, we chose to flush to zero preserving
896897
897898 ; CORTEX-M0: .cpu cortex-m0
898899 ; CORTEX-M0: .eabi_attribute 6, 12
899 ; CORTEX-M0-NOT: .eabi_attribute 7
900 ; CORTEX-M0: .eabi_attribute 7, 77
900901 ; CORTEX-M0: .eabi_attribute 8, 0
901902 ; CORTEX-M0: .eabi_attribute 9, 1
903 ; CORTEX-M0-NOT: .eabi_attribute 27
904 ; CORTEX-M0-NOT: .eabi_attribute 36
905 ; CORTEX-M0: .eabi_attribute 34, 0
906 ; CORTEX-M0-NOT: .eabi_attribute 42
907 ; CORTEX-M0-NOT: .eabi_attribute 44
908 ; CORTEX-M0-NOT: .eabi_attribute 68
902909 ; CORTEX-M0-NOT: .eabi_attribute 19
903910 ;; We default to IEEE 754 compliance
904911 ; CORTEX-M0: .eabi_attribute 20, 1
905912 ; CORTEX-M0: .eabi_attribute 21, 1
906913 ; CORTEX-M0-NOT: .eabi_attribute 22
907914 ; CORTEX-M0: .eabi_attribute 23, 3
908 ; CORTEX-M0: .eabi_attribute 34, 0
909915 ; CORTEX-M0: .eabi_attribute 24, 1
910916 ; CORTEX-M0: .eabi_attribute 25, 1
911 ; CORTEX-M0-NOT: .eabi_attribute 27
912917 ; CORTEX-M0-NOT: .eabi_attribute 28
913 ; CORTEX-M0-NOT: .eabi_attribute 36
914918 ; CORTEX-M0: .eabi_attribute 38, 1
915 ; CORTEX-M0-NOT: .eabi_attribute 42
916 ; CORTEX-M0-NOT: .eabi_attribute 44
917 ; CORTEX-M0-NOT: .eabi_attribute 68
918919
919920 ; CORTEX-M0-FAST-NOT: .eabi_attribute 19
920921 ;; Despite the M0 CPU having no FPU in this scenario, we chose to
929930
930931 ; CORTEX-M0PLUS: .cpu cortex-m0plus
931932 ; CORTEX-M0PLUS: .eabi_attribute 6, 12
932 ; CORTEX-M0PLUS-NOT: .eabi_attribute 7
933 ; CORTEX-M0PLUS: .eabi_attribute 7, 77
933934 ; CORTEX-M0PLUS: .eabi_attribute 8, 0
934935 ; CORTEX-M0PLUS: .eabi_attribute 9, 1
936 ; CORTEX-M0PLUS-NOT: .eabi_attribute 27
937 ; CORTEX-M0PLUS-NOT: .eabi_attribute 36
938 ; CORTEX-M0PLUS-NOT: .eabi_attribute 42
939 ; CORTEX-M0PLUS-NOT: .eabi_attribute 44
940 ; CORTEX-M0PLUS-NOT: .eabi_attribute 68
935941 ; CORTEX-M0PLUS-NOT: .eabi_attribute 19
936942 ;; We default to IEEE 754 compliance
937943 ; CORTEX-M0PLUS: .eabi_attribute 20, 1
940946 ; CORTEX-M0PLUS: .eabi_attribute 23, 3
941947 ; CORTEX-M0PLUS: .eabi_attribute 24, 1
942948 ; CORTEX-M0PLUS: .eabi_attribute 25, 1
943 ; CORTEX-M0PLUS-NOT: .eabi_attribute 27
944949 ; CORTEX-M0PLUS-NOT: .eabi_attribute 28
945 ; CORTEX-M0PLUS-NOT: .eabi_attribute 36
946950 ; CORTEX-M0PLUS: .eabi_attribute 38, 1
947 ; CORTEX-M0PLUS-NOT: .eabi_attribute 42
948 ; CORTEX-M0PLUS-NOT: .eabi_attribute 44
949 ; CORTEX-M0PLUS-NOT: .eabi_attribute 68
950951
951952 ; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 19
952953 ;; Despite the M0+ CPU having no FPU in this scenario, we chose to
961962
962963 ; CORTEX-M1: .cpu cortex-m1
963964 ; CORTEX-M1: .eabi_attribute 6, 12
964 ; CORTEX-M1-NOT: .eabi_attribute 7
965 ; CORTEX-M1: .eabi_attribute 7, 77
965966 ; CORTEX-M1: .eabi_attribute 8, 0
966967 ; CORTEX-M1: .eabi_attribute 9, 1
968 ; CORTEX-M1-NOT: .eabi_attribute 27
969 ; CORTEX-M1-NOT: .eabi_attribute 36
970 ; CORTEX-M1-NOT: .eabi_attribute 42
971 ; CORTEX-M1-NOT: .eabi_attribute 44
972 ; CORTEX-M1-NOT: .eabi_attribute 68
967973 ; CORTEX-M1-NOT: .eabi_attribute 19
968974 ;; We default to IEEE 754 compliance
969975 ; CORTEX-M1: .eabi_attribute 20, 1
972978 ; CORTEX-M1: .eabi_attribute 23, 3
973979 ; CORTEX-M1: .eabi_attribute 24, 1
974980 ; CORTEX-M1: .eabi_attribute 25, 1
975 ; CORTEX-M1-NOT: .eabi_attribute 27
976981 ; CORTEX-M1-NOT: .eabi_attribute 28
977 ; CORTEX-M1-NOT: .eabi_attribute 36
978982 ; CORTEX-M1: .eabi_attribute 38, 1
979 ; CORTEX-M1-NOT: .eabi_attribute 42
980 ; CORTEX-M1-NOT: .eabi_attribute 44
981 ; CORTEX-M1-NOT: .eabi_attribute 68
982983
983984 ; CORTEX-M1-FAST-NOT: .eabi_attribute 19
984985 ;; Despite the M1 CPU having no FPU in this scenario, we chose to
993994
994995 ; SC000: .cpu sc000
995996 ; SC000: .eabi_attribute 6, 12
996 ; SC000-NOT: .eabi_attribute 7
997 ; SC000: .eabi_attribute 7, 77
997998 ; SC000: .eabi_attribute 8, 0
998999 ; SC000: .eabi_attribute 9, 1
1000 ; SC000-NOT: .eabi_attribute 27
1001 ; SC000-NOT: .eabi_attribute 42
1002 ; SC000-NOT: .eabi_attribute 44
1003 ; SC000-NOT: .eabi_attribute 68
9991004 ; SC000-NOT: .eabi_attribute 19
10001005 ;; We default to IEEE 754 compliance
10011006 ; SC000: .eabi_attribute 20, 1
10041009 ; SC000: .eabi_attribute 23, 3
10051010 ; SC000: .eabi_attribute 24, 1
10061011 ; SC000: .eabi_attribute 25, 1
1007 ; SC000-NOT: .eabi_attribute 27
10081012 ; SC000-NOT: .eabi_attribute 28
1009 ; SC000-NOT: .eabi_attribute 36
10101013 ; SC000: .eabi_attribute 38, 1
1011 ; SC000-NOT: .eabi_attribute 42
1012 ; SC000-NOT: .eabi_attribute 44
1013 ; SC000-NOT: .eabi_attribute 68
10141014
10151015 ; SC000-FAST-NOT: .eabi_attribute 19
10161016 ;; Despite the SC000 CPU having no FPU in this scenario, we chose to
10281028 ; CORTEX-M3: .eabi_attribute 7, 77
10291029 ; CORTEX-M3: .eabi_attribute 8, 0
10301030 ; CORTEX-M3: .eabi_attribute 9, 2
1031 ; CORTEX-M3-NOT: .eabi_attribute 27
1032 ; CORTEX-M3-NOT: .eabi_attribute 36
1033 ; CORTEX-M3-NOT: .eabi_attribute 42
1034 ; CORTEX-M3-NOT: .eabi_attribute 44
1035 ; CORTEX-M3-NOT: .eabi_attribute 68
10311036 ; CORTEX-M3-NOT: .eabi_attribute 19
10321037 ;; We default to IEEE 754 compliance
10331038 ; CORTEX-M3: .eabi_attribute 20, 1
10361041 ; CORTEX-M3: .eabi_attribute 23, 3
10371042 ; CORTEX-M3: .eabi_attribute 24, 1
10381043 ; CORTEX-M3: .eabi_attribute 25, 1
1039 ; CORTEX-M3-NOT: .eabi_attribute 27
10401044 ; CORTEX-M3-NOT: .eabi_attribute 28
1041 ; CORTEX-M3-NOT: .eabi_attribute 36
10421045 ; CORTEX-M3: .eabi_attribute 38, 1
1043 ; CORTEX-M3-NOT: .eabi_attribute 42
1044 ; CORTEX-M3-NOT: .eabi_attribute 44
1045 ; CORTEX-M3-NOT: .eabi_attribute 68
10461046
10471047 ; CORTEX-M3-FAST-NOT: .eabi_attribute 19
10481048 ;; Despite there being no FPU, we chose to flush to zero preserving
10581058 ; SC300: .eabi_attribute 7, 77
10591059 ; SC300: .eabi_attribute 8, 0
10601060 ; SC300: .eabi_attribute 9, 2
1061 ; SC300-NOT: .eabi_attribute 27
1062 ; SC300-NOT: .eabi_attribute 36
1063 ; SC300-NOT: .eabi_attribute 42
1064 ; SC300-NOT: .eabi_attribute 44
1065 ; SC300-NOT: .eabi_attribute 68
10611066 ; SC300-NOT: .eabi_attribute 19
10621067 ;; We default to IEEE 754 compliance
10631068 ; SC300: .eabi_attribute 20, 1
10661071 ; SC300: .eabi_attribute 23, 3
10671072 ; SC300: .eabi_attribute 24, 1
10681073 ; SC300: .eabi_attribute 25, 1
1069 ; SC300-NOT: .eabi_attribute 27
10701074 ; SC300-NOT: .eabi_attribute 28
1071 ; SC300-NOT: .eabi_attribute 36
10721075 ; SC300: .eabi_attribute 38, 1
1073 ; SC300-NOT: .eabi_attribute 42
1074 ; SC300-NOT: .eabi_attribute 44
1075 ; SC300-NOT: .eabi_attribute 68
10761076
10771077 ; SC300-FAST-NOT: .eabi_attribute 19
10781078 ;; Despite there being no FPU, we chose to flush to zero preserving
10891089 ; CORTEX-M4-SOFT: .eabi_attribute 8, 0
10901090 ; CORTEX-M4-SOFT: .eabi_attribute 9, 2
10911091 ; CORTEX-M4-SOFT: .fpu fpv4-sp-d16
1092 ; CORTEX-M4-SOFT: .eabi_attribute 27, 1
1093 ; CORTEX-M4-SOFT: .eabi_attribute 36, 1
1094 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
1095 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
1096 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
10921097 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 19
10931098 ;; We default to IEEE 754 compliance
10941099 ; CORTEX-M4-SOFT: .eabi_attribute 20, 1
10971102 ; CORTEX-M4-SOFT: .eabi_attribute 23, 3
10981103 ; CORTEX-M4-SOFT: .eabi_attribute 24, 1
10991104 ; CORTEX-M4-SOFT: .eabi_attribute 25, 1
1100 ; CORTEX-M4-SOFT: .eabi_attribute 27, 1
11011105 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
1102 ; CORTEX-M4-SOFT: .eabi_attribute 36, 1
11031106 ; CORTEX-M4-SOFT: .eabi_attribute 38, 1
1104 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
1105 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
1106 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
11071107
11081108 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19
11091109 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
11191119 ; CORTEX-M4-HARD: .eabi_attribute 8, 0
11201120 ; CORTEX-M4-HARD: .eabi_attribute 9, 2
11211121 ; CORTEX-M4-HARD: .fpu fpv4-sp-d16
1122 ; CORTEX-M4-HARD: .eabi_attribute 27, 1
1123 ; CORTEX-M4-HARD: .eabi_attribute 36, 1
1124 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42
1125 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44
1126 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68
11221127 ; CORTEX-M4-HARD-NOT: .eabi_attribute 19
11231128 ;; We default to IEEE 754 compliance
11241129 ; CORTEX-M4-HARD: .eabi_attribute 20, 1
11271132 ; CORTEX-M4-HARD: .eabi_attribute 23, 3
11281133 ; CORTEX-M4-HARD: .eabi_attribute 24, 1
11291134 ; CORTEX-M4-HARD: .eabi_attribute 25, 1
1130 ; CORTEX-M4-HARD: .eabi_attribute 27, 1
11311135 ; CORTEX-M4-HARD: .eabi_attribute 28, 1
1132 ; CORTEX-M4-HARD: .eabi_attribute 36, 1
11331136 ; CORTEX-M4-HARD: .eabi_attribute 38, 1
1134 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42
1135 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44
1136 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68
11371137
11381138 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19
11391139 ;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
11511151 ; CORTEX-M7-SOFT-NOT: .fpu
11521152 ; CORTEX-M7-SINGLE: .fpu fpv5-sp-d16
11531153 ; CORTEX-M7-DOUBLE: .fpu fpv5-d16
1154 ; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
1155 ; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
1156 ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
1157 ; CORTEX-M7: .eabi_attribute 36, 1
1158 ; CORTEX-M7-NOT: .eabi_attribute 44
11541159 ; CORTEX-M7: .eabi_attribute 17, 1
11551160 ; CORTEX-M7-NOT: .eabi_attribute 19
11561161 ;; We default to IEEE 754 compliance
11601165 ; CORTEX-M7: .eabi_attribute 23, 3
11611166 ; CORTEX-M7: .eabi_attribute 24, 1
11621167 ; CORTEX-M7: .eabi_attribute 25, 1
1163 ; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
1164 ; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
1165 ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
1166 ; CORTEX-M7: .eabi_attribute 36, 1
11671168 ; CORTEX-M7: .eabi_attribute 38, 1
1168 ; CORTEX-M7-NOT: .eabi_attribute 44
11691169 ; CORTEX-M7: .eabi_attribute 14, 0
11701170
11711171 ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19
11851185 ; CORTEX-R4: .eabi_attribute 8, 1
11861186 ; CORTEX-R4: .eabi_attribute 9, 2
11871187 ; CORTEX-R4-NOT: .fpu vfpv3-d16
1188 ; CORTEX-R4-NOT: .eabi_attribute 36
1189 ; CORTEX-R4-NOT: .eabi_attribute 42
1190 ; CORTEX-R4-NOT: .eabi_attribute 44
1191 ; CORTEX-R4-NOT: .eabi_attribute 68
11881192 ; CORTEX-R4-NOT: .eabi_attribute 19
11891193 ;; We default to IEEE 754 compliance
11901194 ; CORTEX-R4: .eabi_attribute 20, 1
11941198 ; CORTEX-R4: .eabi_attribute 24, 1
11951199 ; CORTEX-R4: .eabi_attribute 25, 1
11961200 ; CORTEX-R4-NOT: .eabi_attribute 28
1197 ; CORTEX-R4-NOT: .eabi_attribute 36
11981201 ; CORTEX-R4: .eabi_attribute 38, 1
1199 ; CORTEX-R4-NOT: .eabi_attribute 42
1200 ; CORTEX-R4-NOT: .eabi_attribute 44
1201 ; CORTEX-R4-NOT: .eabi_attribute 68
12021202
12031203 ; CORTEX-R4F: .cpu cortex-r4f
12041204 ; CORTEX-R4F: .eabi_attribute 6, 10
12061206 ; CORTEX-R4F: .eabi_attribute 8, 1
12071207 ; CORTEX-R4F: .eabi_attribute 9, 2
12081208 ; CORTEX-R4F: .fpu vfpv3-d16
1209 ; CORTEX-R4F-NOT: .eabi_attribute 27, 1
1210 ; CORTEX-R4F-NOT: .eabi_attribute 36
1211 ; CORTEX-R4F-NOT: .eabi_attribute 42
1212 ; CORTEX-R4F-NOT: .eabi_attribute 44
1213 ; CORTEX-R4F-NOT: .eabi_attribute 68
12091214 ; CORTEX-R4F-NOT: .eabi_attribute 19
12101215 ;; We default to IEEE 754 compliance
12111216 ; CORTEX-R4F: .eabi_attribute 20, 1
12141219 ; CORTEX-R4F: .eabi_attribute 23, 3
12151220 ; CORTEX-R4F: .eabi_attribute 24, 1
12161221 ; CORTEX-R4F: .eabi_attribute 25, 1
1217 ; CORTEX-R4F-NOT: .eabi_attribute 27, 1
12181222 ; CORTEX-R4F-NOT: .eabi_attribute 28
1219 ; CORTEX-R4F-NOT: .eabi_attribute 36
12201223 ; CORTEX-R4F: .eabi_attribute 38, 1
1221 ; CORTEX-R4F-NOT: .eabi_attribute 42
1222 ; CORTEX-R4F-NOT: .eabi_attribute 44
1223 ; CORTEX-R4F-NOT: .eabi_attribute 68
12241224
12251225 ; CORTEX-R5: .cpu cortex-r5
12261226 ; CORTEX-R5: .eabi_attribute 6, 10
12281228 ; CORTEX-R5: .eabi_attribute 8, 1
12291229 ; CORTEX-R5: .eabi_attribute 9, 2
12301230 ; CORTEX-R5: .fpu vfpv3-d16
1231 ; CORTEX-R5-NOT: .eabi_attribute 27, 1
1232 ; CORTEX-R5-NOT: .eabi_attribute 36
1233 ; CORTEX-R5: .eabi_attribute 44, 2
1234 ; CORTEX-R5-NOT: .eabi_attribute 42
1235 ; CORTEX-R5-NOT: .eabi_attribute 68
12311236 ; CORTEX-R5-NOT: .eabi_attribute 19
12321237 ;; We default to IEEE 754 compliance
12331238 ; CORTEX-R5: .eabi_attribute 20, 1
12361241 ; CORTEX-R5: .eabi_attribute 23, 3
12371242 ; CORTEX-R5: .eabi_attribute 24, 1
12381243 ; CORTEX-R5: .eabi_attribute 25, 1
1239 ; CORTEX-R5-NOT: .eabi_attribute 27, 1
12401244 ; CORTEX-R5-NOT: .eabi_attribute 28
1241 ; CORTEX-R5-NOT: .eabi_attribute 36
12421245 ; CORTEX-R5: .eabi_attribute 38, 1
1243 ; CORTEX-R5-NOT: .eabi_attribute 42
1244 ; CORTEX-R5: .eabi_attribute 44, 2
1245 ; CORTEX-R5-NOT: .eabi_attribute 68
12461246
12471247 ; CORTEX-R5-FAST-NOT: .eabi_attribute 19
12481248 ;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
12571257 ; CORTEX-R7: .eabi_attribute 8, 1
12581258 ; CORTEX-R7: .eabi_attribute 9, 2
12591259 ; CORTEX-R7: .fpu vfpv3-d16-fp16
1260 ; CORTEX-R7: .eabi_attribute 36, 1
1261 ; CORTEX-R7: .eabi_attribute 42, 1
1262 ; CORTEX-R7: .eabi_attribute 44, 2
1263 ; CORTEX-R7-NOT: .eabi_attribute 68
12601264 ; CORTEX-R7-NOT: .eabi_attribute 19
12611265 ;; We default to IEEE 754 compliance
12621266 ; CORTEX-R7: .eabi_attribute 20, 1
12661270 ; CORTEX-R7: .eabi_attribute 24, 1
12671271 ; CORTEX-R7: .eabi_attribute 25, 1
12681272 ; CORTEX-R7-NOT: .eabi_attribute 28
1269 ; CORTEX-R7: .eabi_attribute 36, 1
12701273 ; CORTEX-R7: .eabi_attribute 38, 1
1271 ; CORTEX-R7: .eabi_attribute 42, 1
1272 ; CORTEX-R7: .eabi_attribute 44, 2
1273 ; CORTEX-R7-NOT: .eabi_attribute 68
12741274
12751275 ; CORTEX-R7-FAST-NOT: .eabi_attribute 19
12761276 ;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
12851285 ; CORTEX-R8: .eabi_attribute 8, 1
12861286 ; CORTEX-R8: .eabi_attribute 9, 2
12871287 ; CORTEX-R8: .fpu vfpv3-d16-fp16
1288 ; CORTEX-R8: .eabi_attribute 36, 1
1289 ; CORTEX-R8: .eabi_attribute 42, 1
1290 ; CORTEX-R8: .eabi_attribute 44, 2
1291 ; CORTEX-R8-NOT: .eabi_attribute 68
12881292 ; CORTEX-R8-NOT: .eabi_attribute 19
12891293 ;; We default to IEEE 754 compliance
12901294 ; CORTEX-R8: .eabi_attribute 20, 1
12941298 ; CORTEX-R8: .eabi_attribute 24, 1
12951299 ; CORTEX-R8: .eabi_attribute 25, 1
12961300 ; CORTEX-R8-NOT: .eabi_attribute 28
1297 ; CORTEX-R8: .eabi_attribute 36, 1
12981301 ; CORTEX-R8: .eabi_attribute 38, 1
1299 ; CORTEX-R8: .eabi_attribute 42, 1
1300 ; CORTEX-R8: .eabi_attribute 44, 2
1301 ; CORTEX-R8-NOT: .eabi_attribute 68
13021302
13031303 ; CORTEX-R8-FAST-NOT: .eabi_attribute 19
13041304 ;; The R8 has the VFPv3 FP unit, which always flushes preserving sign.
13141314 ; CORTEX-A32: .eabi_attribute 9, 2
13151315 ; CORTEX-A32: .fpu crypto-neon-fp-armv8
13161316 ; CORTEX-A32: .eabi_attribute 12, 3
1317 ; CORTEX-A32-NOT: .eabi_attribute 27
1318 ; CORTEX-A32: .eabi_attribute 36, 1
1319 ; CORTEX-A32: .eabi_attribute 42, 1
1320 ; CORTEX-A32-NOT: .eabi_attribute 44
1321 ; CORTEX-A32: .eabi_attribute 68, 3
13171322 ; CORTEX-A32-NOT: .eabi_attribute 19
13181323 ;; We default to IEEE 754 compliance
13191324 ; CORTEX-A32: .eabi_attribute 20, 1
13221327 ; CORTEX-A32: .eabi_attribute 23, 3
13231328 ; CORTEX-A32: .eabi_attribute 24, 1
13241329 ; CORTEX-A32: .eabi_attribute 25, 1
1325 ; CORTEX-A32-NOT: .eabi_attribute 27
13261330 ; CORTEX-A32-NOT: .eabi_attribute 28
1327 ; CORTEX-A32: .eabi_attribute 36, 1
13281331 ; CORTEX-A32: .eabi_attribute 38, 1
1329 ; CORTEX-A32: .eabi_attribute 42, 1
1330 ; CORTEX-A32-NOT: .eabi_attribute 44
1331 ; CORTEX-A32: .eabi_attribute 68, 3
13321332
13331333 ; CORTEX-A32-FAST-NOT: .eabi_attribute 19
13341334 ;; The A32 has the ARMv8 FP unit, which always flushes preserving sign.
13421342 ; CORTEX-M23: .eabi_attribute 7, 77
13431343 ; CORTEX-M23: .eabi_attribute 8, 0
13441344 ; CORTEX-M23: .eabi_attribute 9, 3
1345 ; CORTEX-M23-NOT: .eabi_attribute 27
1346 ; CORTEX-M23: .eabi_attribute 34, 1
1347 ; CORTEX-M23-NOT: .eabi_attribute 44
13451348 ; CORTEX-M23: .eabi_attribute 17, 1
13461349 ;; We default to IEEE 754 compliance
13471350 ; CORTEX-M23-NOT: .eabi_attribute 19
13481351 ; CORTEX-M23: .eabi_attribute 20, 1
13491352 ; CORTEX-M23: .eabi_attribute 21, 1
13501353 ; CORTEX-M23: .eabi_attribute 23, 3
1351 ; CORTEX-M23: .eabi_attribute 34, 1
13521354 ; CORTEX-M23: .eabi_attribute 24, 1
1353 ; CORTEX-M23-NOT: .eabi_attribute 27
13541355 ; CORTEX-M23-NOT: .eabi_attribute 28
13551356 ; CORTEX-M23: .eabi_attribute 25, 1
13561357 ; CORTEX-M23: .eabi_attribute 38, 1
13571358 ; CORTEX-M23: .eabi_attribute 14, 0
1358 ; CORTEX-M23-NOT: .eabi_attribute 44
13591359
13601360 ; CORTEX-M33: .cpu cortex-m33
13611361 ; CORTEX-M33: .eabi_attribute 6, 17
13631363 ; CORTEX-M33: .eabi_attribute 8, 0
13641364 ; CORTEX-M33: .eabi_attribute 9, 3
13651365 ; CORTEX-M33: .fpu fpv5-sp-d16
1366 ; CORTEX-M33: .eabi_attribute 27, 1
1367 ; CORTEX-M33: .eabi_attribute 36, 1
1368 ; CORTEX-M33-NOT: .eabi_attribute 44
1369 ; CORTEX-M33: .eabi_attribute 46, 1
1370 ; CORTEX-M33: .eabi_attribute 34, 1
13661371 ; CORTEX-M33: .eabi_attribute 17, 1
13671372 ;; We default to IEEE 754 compliance
13681373 ; CORTEX-M23-NOT: .eabi_attribute 19
13691374 ; CORTEX-M33: .eabi_attribute 20, 1
13701375 ; CORTEX-M33: .eabi_attribute 21, 1
13711376 ; CORTEX-M33: .eabi_attribute 23, 3
1372 ; CORTEX-M33: .eabi_attribute 34, 1
13731377 ; CORTEX-M33: .eabi_attribute 24, 1
13741378 ; CORTEX-M33: .eabi_attribute 25, 1
1375 ; CORTEX-M33: .eabi_attribute 27, 1
13761379 ; CORTEX-M33-NOT: .eabi_attribute 28
1377 ; CORTEX-M33: .eabi_attribute 36, 1
13781380 ; CORTEX-M33: .eabi_attribute 38, 1
1379 ; CORTEX-M33: .eabi_attribute 46, 1
1380 ; CORTEX-M33-NOT: .eabi_attribute 44
13811381 ; CORTEX-M33: .eabi_attribute 14, 0
13821382
13831383 ; CORTEX-M33-FAST-NOT: .eabi_attribute 19
13931393 ; CORTEX-A35: .eabi_attribute 9, 2
13941394 ; CORTEX-A35: .fpu crypto-neon-fp-armv8
13951395 ; CORTEX-A35: .eabi_attribute 12, 3
1396 ; CORTEX-A35-NOT: .eabi_attribute 27
1397 ; CORTEX-A35: .eabi_attribute 36, 1
1398 ; CORTEX-A35: .eabi_attribute 42, 1
1399 ; CORTEX-A35-NOT: .eabi_attribute 44
1400 ; CORTEX-A35: .eabi_attribute 68, 3
13961401 ; CORTEX-A35-NOT: .eabi_attribute 19
13971402 ;; We default to IEEE 754 compliance
13981403 ; CORTEX-A35: .eabi_attribute 20, 1
14011406 ; CORTEX-A35: .eabi_attribute 23, 3
14021407 ; CORTEX-A35: .eabi_attribute 24, 1
14031408 ; CORTEX-A35: .eabi_attribute 25, 1
1404 ; CORTEX-A35-NOT: .eabi_attribute 27
14051409 ; CORTEX-A35-NOT: .eabi_attribute 28
1406 ; CORTEX-A35: .eabi_attribute 36, 1
14071410 ; CORTEX-A35: .eabi_attribute 38, 1
1408 ; CORTEX-A35: .eabi_attribute 42, 1
1409 ; CORTEX-A35-NOT: .eabi_attribute 44
1410 ; CORTEX-A35: .eabi_attribute 68, 3
14111411
14121412 ; CORTEX-A35-FAST-NOT: .eabi_attribute 19
14131413 ;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
14231423 ; CORTEX-A53: .eabi_attribute 9, 2
14241424 ; CORTEX-A53: .fpu crypto-neon-fp-armv8
14251425 ; CORTEX-A53: .eabi_attribute 12, 3
1426 ; CORTEX-A53-NOT: .eabi_attribute 27
1427 ; CORTEX-A53: .eabi_attribute 36, 1
1428 ; CORTEX-A53: .eabi_attribute 42, 1
1429 ; CORTEX-A53-NOT: .eabi_attribute 44
1430 ; CORTEX-A53: .eabi_attribute 68, 3
14261431 ; CORTEX-A53-NOT: .eabi_attribute 19
14271432 ;; We default to IEEE 754 compliance
14281433 ; CORTEX-A53: .eabi_attribute 20, 1
14311436 ; CORTEX-A53: .eabi_attribute 23, 3
14321437 ; CORTEX-A53: .eabi_attribute 24, 1
14331438 ; CORTEX-A53: .eabi_attribute 25, 1
1434 ; CORTEX-A53-NOT: .eabi_attribute 27
14351439 ; CORTEX-A53-NOT: .eabi_attribute 28
1436 ; CORTEX-A53: .eabi_attribute 36, 1
14371440 ; CORTEX-A53: .eabi_attribute 38, 1
1438 ; CORTEX-A53: .eabi_attribute 42, 1
1439 ; CORTEX-A53-NOT: .eabi_attribute 44
1440 ; CORTEX-A53: .eabi_attribute 68, 3
14411441
14421442 ; CORTEX-A53-FAST-NOT: .eabi_attribute 19
14431443 ;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
14531453 ; CORTEX-A57: .eabi_attribute 9, 2
14541454 ; CORTEX-A57: .fpu crypto-neon-fp-armv8
14551455 ; CORTEX-A57: .eabi_attribute 12, 3
1456 ; CORTEX-A57-NOT: .eabi_attribute 27
1457 ; CORTEX-A57: .eabi_attribute 36, 1
1458 ; CORTEX-A57: .eabi_attribute 42, 1
1459 ; CORTEX-A57-NOT: .eabi_attribute 44
1460 ; CORTEX-A57: .eabi_attribute 68, 3
14561461 ; CORTEX-A57-NOT: .eabi_attribute 19
14571462 ;; We default to IEEE 754 compliance
14581463 ; CORTEX-A57: .eabi_attribute 20, 1
14611466 ; CORTEX-A57: .eabi_attribute 23, 3
14621467 ; CORTEX-A57: .eabi_attribute 24, 1
14631468 ; CORTEX-A57: .eabi_attribute 25, 1
1464 ; CORTEX-A57-NOT: .eabi_attribute 27
14651469 ; CORTEX-A57-NOT: .eabi_attribute 28
1466 ; CORTEX-A57: .eabi_attribute 36, 1
14671470 ; CORTEX-A57: .eabi_attribute 38, 1
1468 ; CORTEX-A57: .eabi_attribute 42, 1
1469 ; CORTEX-A57-NOT: .eabi_attribute 44
1470 ; CORTEX-A57: .eabi_attribute 68, 3
14711471
14721472 ; CORTEX-A57-FAST-NOT: .eabi_attribute 19
14731473 ;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
14831483 ; CORTEX-A72: .eabi_attribute 9, 2
14841484 ; CORTEX-A72: .fpu crypto-neon-fp-armv8
14851485 ; CORTEX-A72: .eabi_attribute 12, 3
1486 ; CORTEX-A72-NOT: .eabi_attribute 27
1487 ; CORTEX-A72: .eabi_attribute 36, 1
1488 ; CORTEX-A72: .eabi_attribute 42, 1
1489 ; CORTEX-A72-NOT: .eabi_attribute 44
1490 ; CORTEX-A72: .eabi_attribute 68, 3
14861491 ; CORTEX-A72-NOT: .eabi_attribute 19
14871492 ;; We default to IEEE 754 compliance
14881493 ; CORTEX-A72: .eabi_attribute 20, 1
14911496 ; CORTEX-A72: .eabi_attribute 23, 3
14921497 ; CORTEX-A72: .eabi_attribute 24, 1
14931498 ; CORTEX-A72: .eabi_attribute 25, 1
1494 ; CORTEX-A72-NOT: .eabi_attribute 27
14951499 ; CORTEX-A72-NOT: .eabi_attribute 28
1496 ; CORTEX-A72: .eabi_attribute 36, 1
14971500 ; CORTEX-A72: .eabi_attribute 38, 1
1498 ; CORTEX-A72: .eabi_attribute 42, 1
1499 ; CORTEX-A72-NOT: .eabi_attribute 44
1500 ; CORTEX-A72: .eabi_attribute 68, 3
15011501
15021502 ; CORTEX-A72-FAST-NOT: .eabi_attribute 19
15031503 ;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
15131513 ; CORTEX-A73: .eabi_attribute 9, 2
15141514 ; CORTEX-A73: .fpu crypto-neon-fp-armv8
15151515 ; CORTEX-A73: .eabi_attribute 12, 3
1516 ; CORTEX-A73-NOT: .eabi_attribute 27
1517 ; CORTEX-A73: .eabi_attribute 36, 1
1518 ; CORTEX-A73: .eabi_attribute 42, 1
1519 ; CORTEX-A73-NOT: .eabi_attribute 44
1520 ; CORTEX-A73: .eabi_attribute 68, 3
15161521 ; CORTEX-A73-NOT: .eabi_attribute 19
15171522 ;; We default to IEEE 754 compliance
15181523 ; CORTEX-A73: .eabi_attribute 20, 1
15211526 ; CORTEX-A73: .eabi_attribute 23, 3
15221527 ; CORTEX-A73: .eabi_attribute 24, 1
15231528 ; CORTEX-A73: .eabi_attribute 25, 1
1524 ; CORTEX-A73-NOT: .eabi_attribute 27
15251529 ; CORTEX-A73-NOT: .eabi_attribute 28
1526 ; CORTEX-A73: .eabi_attribute 36, 1
15271530 ; CORTEX-A73: .eabi_attribute 38, 1
1528 ; CORTEX-A73: .eabi_attribute 42, 1
1529 ; CORTEX-A73-NOT: .eabi_attribute 44
15301531 ; CORTEX-A73: .eabi_attribute 14, 0
1531 ; CORTEX-A73: .eabi_attribute 68, 3
15321532
15331533 ; EXYNOS-M1: .cpu exynos-m1
15341534 ; EXYNOS-M1: .eabi_attribute 6, 14
15371537 ; EXYNOS-M1: .eabi_attribute 9, 2
15381538 ; EXYNOS-M1: .fpu crypto-neon-fp-armv8
15391539 ; EXYNOS-M1: .eabi_attribute 12, 3
1540 ; EXYNOS-M1-NOT: .eabi_attribute 27
1541 ; EXYNOS-M1: .eabi_attribute 36, 1
1542 ; EXYNOS-M1: .eabi_attribute 42, 1
1543 ; EXYNOS-M1-NOT: .eabi_attribute 44
1544 ; EXYNOS-M1: .eabi_attribute 68, 3
15401545 ; EXYNOS-M1-NOT: .eabi_attribute 19
15411546 ;; We default to IEEE 754 compliance
15421547 ; EXYNOS-M1: .eabi_attribute 20, 1
15451550 ; EXYNOS-M1: .eabi_attribute 23, 3
15461551 ; EXYNOS-M1: .eabi_attribute 24, 1
15471552 ; EXYNOS-M1: .eabi_attribute 25, 1
1548 ; EXYNOS-M1-NOT: .eabi_attribute 27
15491553 ; EXYNOS-M1-NOT: .eabi_attribute 28
1550 ; EXYNOS-M1: .eabi_attribute 36, 1
15511554 ; EXYNOS-M1: .eabi_attribute 38, 1
1552 ; EXYNOS-M1: .eabi_attribute 42, 1
1553 ; EXYNOS-M1-NOT: .eabi_attribute 44
1554 ; EXYNOS-M1: .eabi_attribute 68, 3
15551555
15561556 ; EXYNOS-M1-FAST-NOT: .eabi_attribute 19
15571557 ;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
15671567 ; EXYNOS-M2: .eabi_attribute 9, 2
15681568 ; EXYNOS-M2: .fpu crypto-neon-fp-armv8
15691569 ; EXYNOS-M2: .eabi_attribute 12, 3
1570 ; EXYNOS-M2-NOT: .eabi_attribute 27
1571 ; EXYNOS-M2: .eabi_attribute 36, 1
1572 ; EXYNOS-M2: .eabi_attribute 42, 1
1573 ; EXYNOS-M2-NOT: .eabi_attribute 44
1574 ; EXYNOS-M2: .eabi_attribute 68, 3
15701575 ; EXYNOS-M2-NOT: .eabi_attribute 19
15711576 ;; We default to IEEE 754 compliance
15721577 ; EXYNOS-M2: .eabi_attribute 20, 1
15751580 ; EXYNOS-M2: .eabi_attribute 23, 3
15761581 ; EXYNOS-M2: .eabi_attribute 24, 1
15771582 ; EXYNOS-M2: .eabi_attribute 25, 1
1578 ; EXYNOS-M2-NOT: .eabi_attribute 27
15791583 ; EXYNOS-M2-NOT: .eabi_attribute 28
1580 ; EXYNOS-M2: .eabi_attribute 36, 1
15811584 ; EXYNOS-M2: .eabi_attribute 38, 1
1582 ; EXYNOS-M2: .eabi_attribute 42, 1
1583 ; EXYNOS-M2-NOT: .eabi_attribute 44
1584 ; EXYNOS-M2: .eabi_attribute 68, 3
15851585
15861586 ; EXYNOS-M3: .cpu exynos-m3
15871587 ; EXYNOS-M3: .eabi_attribute 6, 14
15901590 ; EXYNOS-M3: .eabi_attribute 9, 2
15911591 ; EXYNOS-M3: .fpu crypto-neon-fp-armv8
15921592 ; EXYNOS-M3: .eabi_attribute 12, 3
1593 ; EXYNOS-M3-NOT: .eabi_attribute 27
1594 ; EXYNOS-M3: .eabi_attribute 36, 1
1595 ; EXYNOS-M3: .eabi_attribute 42, 1
1596 ; EXYNOS-M3-NOT: .eabi_attribute 44
1597 ; EXYNOS-M3: .eabi_attribute 68, 3
15931598 ; EXYNOS-M3-NOT: .eabi_attribute 19
15941599 ;; We default to IEEE 754 compliance
15951600 ; EXYNOS-M3: .eabi_attribute 20, 1
15981603 ; EXYNOS-M3: .eabi_attribute 23, 3
15991604 ; EXYNOS-M3: .eabi_attribute 24, 1
16001605 ; EXYNOS-M3: .eabi_attribute 25, 1
1601 ; EXYNOS-M3-NOT: .eabi_attribute 27
16021606 ; EXYNOS-M3-NOT: .eabi_attribute 28
1603 ; EXYNOS-M3: .eabi_attribute 36, 1
16041607 ; EXYNOS-M3: .eabi_attribute 38, 1
1605 ; EXYNOS-M3: .eabi_attribute 42, 1
1606 ; EXYNOS-M3-NOT: .eabi_attribute 44
1607 ; EXYNOS-M3: .eabi_attribute 68, 3
16081608
16091609 ; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
16101610 ; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
16181618 ; GENERIC-ARMV8_1-A: .eabi_attribute 9, 2
16191619 ; GENERIC-ARMV8_1-A: .fpu crypto-neon-fp-armv8
16201620 ; GENERIC-ARMV8_1-A: .eabi_attribute 12, 4
1621 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27
1622 ; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1
1623 ; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1
1624 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44
1625 ; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3
16211626 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 19
16221627 ;; We default to IEEE 754 compliance
16231628 ; GENERIC-ARMV8_1-A: .eabi_attribute 20, 1
16261631 ; GENERIC-ARMV8_1-A: .eabi_attribute 23, 3
16271632 ; GENERIC-ARMV8_1-A: .eabi_attribute 24, 1
16281633 ; GENERIC-ARMV8_1-A: .eabi_attribute 25, 1
1629 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 27
16301634 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 28
1631 ; GENERIC-ARMV8_1-A: .eabi_attribute 36, 1
16321635 ; GENERIC-ARMV8_1-A: .eabi_attribute 38, 1
1633 ; GENERIC-ARMV8_1-A: .eabi_attribute 42, 1
1634 ; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44
1635 ; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3
16361636
16371637 ; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 19
16381638 ;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
16691669 ; ARMv8R-SP-NOT: .eabi_attribute 12
16701670 ; ARMv8R-NEON: .fpu neon-fp-armv8
16711671 ; ARMv8R-NEON: .eabi_attribute 12, 3 @ Tag_Advanced_SIMD_arch
1672 ; ARMv8R: .eabi_attribute 17, 1 @ Tag_ABI_PCS_GOT_use
1673 ; ARMv8R: .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
1674 ; ARMv8R: .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
1675 ; ARMv8R: .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
1676 ; ARMv8R: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
1677 ; ARMv8R: .eabi_attribute 24, 1 @ Tag_ABI_align_needed
1678 ; ARMv8R: .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
16791672 ; ARMv8R-NOFPU-NOT: .eabi_attribute 27
16801673 ; ARMv8R-SP: .eabi_attribute 27, 1 @ Tag_ABI_HardFP_use
16811674 ; ARMv8R-NEON-NOT: .eabi_attribute 27
16821675 ; ARMv8R-NOFPU-NOT: .eabi_attribute 36
16831676 ; ARMv8R-SP: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
16841677 ; ARMv8R-NEON: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
1678 ; ARMv8R: .eabi_attribute 42, 1 @ Tag_MPextension_use
1679 ; ARMv8R: .eabi_attribute 68, 2 @ Tag_Virtualization_use
16851680 ; ARMv8R: .eabi_attribute 38, 1 @ Tag_ABI_FP_16bit_format
1686 ; ARMv8R: .eabi_attribute 42, 1 @ Tag_MPextension_use
16871681 ; ARMv8R: .eabi_attribute 14, 0 @ Tag_ABI_PCS_R9_use
1688 ; ARMv8R: .eabi_attribute 68, 2 @ Tag_Virtualization_use
16891682
16901683 define i32 @f(i64 %z) {
16911684 ret i32 0
0 // RUN: llvm-mc -triple armv7a < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7A
1 // RUN: llvm-mc -triple armv6m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v6M
2 // RUN: llvm-mc -triple armv7m < %s -arm-add-build-attributes | FileCheck %s --check-prefix=v7M
3 // RUN: llvm-mc -triple armv7a -mcpu=cortex-a15 < %s -arm-add-build-attributes | FileCheck %s --check-prefix=Cortex-A15
4
5 // This isn't intended to be a through check of the build attributes emitted
6 // for each target (that's tested elsewhere), but just to check that the
7 // hardware attributes are emitted by the assembler based on the selected
8 // target when requested.
9
10 // v7A-NOT: .cpu
11 // v7A: .eabi_attribute 6, 10 @ Tag_CPU_arch
12 // v7A: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
13 // v7A: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
14 // v7A: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
15 // v7A: .fpu neon
16 // v7A: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
17
18 // v6M-NOT: .cpu
19 // v6M: .eabi_attribute 6, 12 @ Tag_CPU_arch
20 // v6M: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
21 // v6M: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
22 // v6M: .eabi_attribute 9, 1 @ Tag_THUMB_ISA_use
23 // v6M: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
24
25 // v7M-NOT: .cpu
26 // v7M: .eabi_attribute 6, 10 @ Tag_CPU_arch
27 // v7M: .eabi_attribute 7, 77 @ Tag_CPU_arch_profile
28 // v7M: .eabi_attribute 8, 0 @ Tag_ARM_ISA_use
29 // v7M: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
30 // v7M: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
31
32 // Cortex-A15: .cpu cortex-a15
33 // Cortex-A15: .eabi_attribute 6, 10 @ Tag_CPU_arch
34 // Cortex-A15: .eabi_attribute 7, 65 @ Tag_CPU_arch_profile
35 // Cortex-A15: .eabi_attribute 8, 1 @ Tag_ARM_ISA_use
36 // Cortex-A15: .eabi_attribute 9, 2 @ Tag_THUMB_ISA_use
37 // Cortex-A15: .fpu neon-vfpv4
38 // Cortex-A15: .eabi_attribute 36, 1 @ Tag_FP_HP_extension
39 // Cortex-A15: .eabi_attribute 42, 1 @ Tag_MPextension_use
40 // Cortex-A15: .eabi_attribute 44, 2 @ Tag_DIV_use
41 // Cortex-A15: .eabi_attribute 34, 1 @ Tag_CPU_unaligned_access
42 // Cortex-A15: .eabi_attribute 68, 3 @ Tag_Virtualization_use