llvm.org GIT mirror llvm / 124c86e
[C++11] Add 'override' keyword to virtual methods that override their base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203418 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
12 changed file(s) with 69 addition(s) and 72 deletion(s). Raw diff Collapse all Expand all
652652 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
653653 SmallVectorImpl &Operands,
654654 MCStreamer &Out, unsigned &ErrorInfo,
655 bool MatchingInlineAsm);
655 bool MatchingInlineAsm) override;
656656
657657 /// doSrcDstMatch - Returns true if operands are matching in their
658658 /// word size (%si and %di, %esi and %edi, etc.). Order depends on
706706 // Initialize the set of available features.
707707 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
708708 }
709 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
710
711 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
712 SMLoc NameLoc,
713 SmallVectorImpl &Operands);
714
715 virtual bool ParseDirective(AsmToken DirectiveID);
709 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
710
711 bool
712 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
713 SmallVectorImpl &Operands) override;
714
715 bool ParseDirective(AsmToken DirectiveID) override;
716716 };
717717 } // end anonymous namespace
718718
6363 X86Operand(KindTy K, SMLoc Start, SMLoc End)
6464 : Kind(K), StartLoc(Start), EndLoc(End) {}
6565
66 StringRef getSymName() { return SymName; }
67 void *getOpDecl() { return OpDecl; }
66 StringRef getSymName() override { return SymName; }
67 void *getOpDecl() override { return OpDecl; }
6868
6969 /// getStartLoc - Get the location of the first token of this operand.
70 SMLoc getStartLoc() const { return StartLoc; }
70 SMLoc getStartLoc() const override { return StartLoc; }
7171 /// getEndLoc - Get the location of the last token of this operand.
72 SMLoc getEndLoc() const { return EndLoc; }
72 SMLoc getEndLoc() const override { return EndLoc; }
7373 /// getLocRange - Get the range between the first and last token of this
7474 /// operand.
7575 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
7676 /// getOffsetOfLoc - Get the location of the offset operator.
77 SMLoc getOffsetOfLoc() const { return OffsetOfLoc; }
78
79 virtual void print(raw_ostream &OS) const {}
77 SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
78
79 void print(raw_ostream &OS) const override {}
8080
8181 StringRef getToken() const {
8282 assert(Kind == Token && "Invalid access!");
8888 Tok.Length = Value.size();
8989 }
9090
91 unsigned getReg() const {
91 unsigned getReg() const override {
9292 assert(Kind == Register && "Invalid access!");
9393 return Reg.RegNo;
9494 }
119119 return Mem.Scale;
120120 }
121121
122 bool isToken() const {return Kind == Token; }
123
124 bool isImm() const { return Kind == Immediate; }
122 bool isToken() const override {return Kind == Token; }
123
124 bool isImm() const override { return Kind == Immediate; }
125125
126126 bool isImmSExti16i8() const {
127127 if (!isImm())
194194 return isImmSExti64i32Value(CE->getValue());
195195 }
196196
197 bool isOffsetOf() const {
197 bool isOffsetOf() const override {
198198 return OffsetOfLoc.getPointer();
199199 }
200200
201 bool needAddressOf() const {
201 bool needAddressOf() const override {
202202 return AddressOf;
203203 }
204204
205 bool isMem() const { return Kind == Memory; }
205 bool isMem() const override { return Kind == Memory; }
206206 bool isMem8() const {
207207 return Kind == Memory && (!Mem.Size || Mem.Size == 8);
208208 }
314314 !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64);
315315 }
316316
317 bool isReg() const { return Kind == Register; }
317 bool isReg() const override { return Kind == Register; }
318318
319319 bool isGR32orGR64() const {
320320 return Kind == Register &&
110110 public:
111111
112112 /// getInstruction - See MCDisassembler.
113 DecodeStatus getInstruction(MCInst &instr,
114 uint64_t &size,
115 const MemoryObject ®ion,
116 uint64_t address,
113 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
114 const MemoryObject ®ion, uint64_t address,
117115 raw_ostream &vStream,
118 raw_ostream &cStream) const;
116 raw_ostream &cStream) const override;
119117
120118 private:
121119 DisassemblerMode fMode;
2626 const MCRegisterInfo &MRI)
2727 : MCInstPrinter(MAI, MII, MRI) {}
2828
29 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
30 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
31
29 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
30 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
31
3232 // Autogenerated by tblgen.
3333 void printInstruction(const MCInst *MI, raw_ostream &O);
3434 static const char *getRegisterName(unsigned RegNo);
7878 CPU != "c3" && CPU != "c3-2";
7979 }
8080
81 unsigned getNumFixupKinds() const {
81 unsigned getNumFixupKinds() const override {
8282 return X86::NumTargetFixupKinds;
8383 }
8484
85 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
85 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
8686 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
8787 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
8888 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
9999 }
100100
101101 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
102 uint64_t Value) const {
102 uint64_t Value) const override {
103103 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
104104
105105 assert(Fixup.getOffset() + Size <= DataSize &&
116116 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
117117 }
118118
119 bool mayNeedRelaxation(const MCInst &Inst) const;
120
121 bool fixupNeedsRelaxation(const MCFixup &Fixup,
122 uint64_t Value,
119 bool mayNeedRelaxation(const MCInst &Inst) const override;
120
121 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
123122 const MCRelaxableFragment *DF,
124 const MCAsmLayout &Layout) const;
125
126 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
127
128 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
123 const MCAsmLayout &Layout) const override;
124
125 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
126
127 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
129128 };
130129 } // end anonymous namespace
131130
354353 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
355354 : ELFX86AsmBackend(T, OSABI, CPU) {}
356355
357 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
356 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
358357 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
359358 }
360359 };
364363 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
365364 : ELFX86AsmBackend(T, OSABI, CPU) {}
366365
367 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
366 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
368367 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
369368 }
370369 };
378377 , Is64Bit(is64Bit) {
379378 }
380379
381 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
380 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
382381 return createX86WinCOFFObjectWriter(OS, Is64Bit);
383382 }
384383 };
717716 StringRef CPU, bool SupportsCU)
718717 : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {}
719718
720 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
719 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
721720 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
722721 MachO::CPU_TYPE_I386,
723722 MachO::CPU_SUBTYPE_I386_ALL);
724723 }
725724
726725 /// \brief Generate the compact unwind encoding for the CFI instructions.
727 virtual uint32_t
728 generateCompactUnwindEncoding(ArrayRef Instrs) const {
726 uint32_t generateCompactUnwindEncoding(
727 ArrayRef Instrs) const override {
729728 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
730729 }
731730 };
742741 HasReliableSymbolDifference = true;
743742 }
744743
745 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
744 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
746745 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
747746 MachO::CPU_TYPE_X86_64, Subtype);
748747 }
749748
750 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
749 bool doesSectionRequireSymbols(const MCSection &Section) const override {
751750 // Temporary labels in the string literals sections require symbols. The
752751 // issue is that the x86_64 relocation format does not allow symbol +
753752 // offset, and so the linker does not have enough information to resolve the
760759 return SMO.getType() == MachO::S_CSTRING_LITERALS;
761760 }
762761
763 virtual bool isSectionAtomizable(const MCSection &Section) const {
762 bool isSectionAtomizable(const MCSection &Section) const override {
764763 const MCSectionMachO &SMO = static_cast(Section);
765764 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
766765 switch (SMO.getType()) {
781780 }
782781
783782 /// \brief Generate the compact unwind encoding for the CFI instructions.
784 virtual uint32_t
785 generateCompactUnwindEncoding(ArrayRef Instrs) const {
783 uint32_t generateCompactUnwindEncoding(
784 ArrayRef Instrs) const override {
786785 return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0;
787786 }
788787 };
2323
2424 virtual ~X86ELFObjectWriter();
2525 protected:
26 virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
27 bool IsPCRel, bool IsRelocWithSymbol,
28 int64_t Addend) const;
26 unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
27 bool IsPCRel, bool IsRelocWithSymbol,
28 int64_t Addend) const override;
2929 };
3030 }
3131
2424 public:
2525 X86_64ELFRelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {}
2626
27 const MCExpr *createExprForRelocation(RelocationRef Rel) {
27 const MCExpr *createExprForRelocation(RelocationRef Rel) override {
2828 uint64_t RelType; Rel.getType(RelType);
2929 symbol_iterator SymI = Rel.getSymbol();
3030
2222 class Triple;
2323
2424 class X86MCAsmInfoDarwin : public MCAsmInfoDarwin {
25 virtual void anchor();
25 void anchor() override;
2626 public:
2727 explicit X86MCAsmInfoDarwin(const Triple &Triple);
2828 };
2929
3030 struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin {
3131 explicit X86_64MCAsmInfoDarwin(const Triple &Triple);
32 virtual const MCExpr *
33 getExprForPersonalitySymbol(const MCSymbol *Sym,
34 unsigned Encoding,
35 MCStreamer &Streamer) const;
32 const MCExpr *
33 getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
34 MCStreamer &Streamer) const override;
3635 };
3736
3837 class X86ELFMCAsmInfo : public MCAsmInfoELF {
39 virtual void anchor();
38 void anchor() override;
4039 public:
4140 explicit X86ELFMCAsmInfo(const Triple &Triple);
42 virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) const;
41 const MCSection *
42 getNonexecutableStackSection(MCContext &Ctx) const override;
4343 };
4444
4545 class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft {
46 virtual void anchor();
46 void anchor() override;
4747 public:
4848 explicit X86MCAsmInfoMicrosoft(const Triple &Triple);
4949 };
5050
5151 class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF {
52 virtual void anchor();
52 void anchor() override;
5353 public:
5454 explicit X86MCAsmInfoGNUCOFF(const Triple &Triple);
5555 };
149149
150150 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
151151 SmallVectorImpl &Fixups,
152 const MCSubtargetInfo &STI) const;
152 const MCSubtargetInfo &STI) const override;
153153
154154 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
155155 const MCInst &MI, const MCInstrDesc &Desc,
2323 public:
2424 X86_64MachORelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {}
2525
26 const MCExpr *createExprForRelocation(RelocationRef Rel) {
26 const MCExpr *createExprForRelocation(RelocationRef Rel) override {
2727 const MachOObjectFile *Obj = cast(Rel.getObjectFile());
2828
2929 uint64_t RelType; Rel.getType(RelType);
6262 void RecordRelocation(MachObjectWriter *Writer,
6363 const MCAssembler &Asm, const MCAsmLayout &Layout,
6464 const MCFragment *Fragment, const MCFixup &Fixup,
65 MCValue Target, uint64_t &FixedValue) {
65 MCValue Target, uint64_t &FixedValue) override {
6666 if (Writer->is64Bit())
6767 RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
6868 FixedValue);
26802680 << " const SmallVectorImpl "
26812681 << "&Operands);\n";
26822682 OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
2683 OS << " const SmallVectorImpl &Operands);\n";
2684 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n";
2683 OS << " const SmallVectorImpl &Operands) override;\n";
2684 OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n";
26852685 OS << " unsigned MatchInstructionImpl(\n";
26862686 OS.indent(27);
26872687 OS << "const SmallVectorImpl &Operands,\n"