llvm.org GIT mirror llvm / 122a970
[SystemZ] Move sign_extend optimization to PerformDAGCombine The target was marking SIGN_EXTEND as Custom because it wanted to optimize certain sign-extended shifts. In all other respects the extension is Legal, so it'd be better to do the optimization in PerformDAGCombine instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203234 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Sandiford 5 years ago
2 changed file(s) with 37 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
208208 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
209209 setOperationAction(ISD::OR, MVT::i64, Custom);
210210
211 // Give LowerOperation the chance to optimize SIGN_EXTEND sequences.
212 setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
213
214211 // FIXME: Can we support these natively?
215212 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
216213 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
291288 setOperationAction(ISD::VASTART, MVT::Other, Custom);
292289 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
293290 setOperationAction(ISD::VAEND, MVT::Other, Expand);
291
292 // Codes for which we want to perform some z-specific combinations.
293 setTargetDAGCombine(ISD::SIGN_EXTEND);
294294
295295 // We want to use MVC in preference to even a single load/store pair.
296296 MaxStoresPerMemcpy = 0;
21732173 MVT::i64, HighOp, Low32);
21742174 }
21752175
2176 SDValue SystemZTargetLowering::lowerSIGN_EXTEND(SDValue Op,
2177 SelectionDAG &DAG) const {
2178 // Convert (sext (ashr (shl X, C1), C2)) to
2179 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2180 // cheap as narrower ones.
2181 SDValue N0 = Op.getOperand(0);
2182 EVT VT = Op.getValueType();
2183 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2184 auto *SraAmt = dyn_cast(N0.getOperand(1));
2185 SDValue Inner = N0.getOperand(0);
2186 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2187 auto *ShlAmt = dyn_cast(Inner.getOperand(1));
2188 if (ShlAmt) {
2189 unsigned Extra = (VT.getSizeInBits() -
2190 N0.getValueType().getSizeInBits());
2191 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2192 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2193 EVT ShiftVT = N0.getOperand(1).getValueType();
2194 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2195 Inner.getOperand(0));
2196 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2197 DAG.getConstant(NewShlAmt, ShiftVT));
2198 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2199 DAG.getConstant(NewSraAmt, ShiftVT));
2200 }
2201 }
2202 }
2203 return SDValue();
2204 }
2205
22062176 // Op is an atomic load. Lower it into a normal volatile load.
22072177 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
22082178 SelectionDAG &DAG) const {
24552425 return lowerUDIVREM(Op, DAG);
24562426 case ISD::OR:
24572427 return lowerOR(Op, DAG);
2458 case ISD::SIGN_EXTEND:
2459 return lowerSIGN_EXTEND(Op, DAG);
24602428 case ISD::ATOMIC_SWAP:
24612429 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
24622430 case ISD::ATOMIC_STORE:
25472515 }
25482516 return NULL;
25492517 #undef OPCODE
2518 }
2519
2520 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
2521 DAGCombinerInfo &DCI) const {
2522 SelectionDAG &DAG = DCI.DAG;
2523 unsigned Opcode = N->getOpcode();
2524 if (Opcode == ISD::SIGN_EXTEND) {
2525 // Convert (sext (ashr (shl X, C1), C2)) to
2526 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2527 // cheap as narrower ones.
2528 SDValue N0 = N->getOperand(0);
2529 EVT VT = N->getValueType(0);
2530 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2531 auto *SraAmt = dyn_cast(N0.getOperand(1));
2532 SDValue Inner = N0.getOperand(0);
2533 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2534 if (auto *ShlAmt = dyn_cast(Inner.getOperand(1))) {
2535 unsigned Extra = (VT.getSizeInBits() -
2536 N0.getValueType().getSizeInBits());
2537 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2538 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2539 EVT ShiftVT = N0.getOperand(1).getValueType();
2540 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2541 Inner.getOperand(0));
2542 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2543 DAG.getConstant(NewShlAmt, ShiftVT));
2544 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2545 DAG.getConstant(NewSraAmt, ShiftVT));
2546 }
2547 }
2548 }
2549 }
2550 return SDValue();
25502551 }
25512552
25522553 //===----------------------------------------------------------------------===//
244244 SDLoc DL, SelectionDAG &DAG) const override;
245245 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
246246 SelectionDAG &DAG) const override;
247 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
247248
248249 private:
249250 const SystemZSubtarget &Subtarget;
270271 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
271272 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
272273 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
273 SDValue lowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
274274 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
275275 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
276276 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,