llvm.org GIT mirror llvm / 1209b72
AMDGPU: Fix getInstSizeInBytes Summary: Add some optional code to validate getInstSizeInBytes for emitted instructions. This flushed out some issues which are fixed by this patch: - Streamline getInstSizeInBytes - Properly define the VI readlane/writelane instruction as VOP3 - Fix the inline constant determination. Specifically, this change fixes an issue where a 32-bit value of 0xffffffff was recorded as unsigned. This is equal to -1 when restricting to a 32-bit comparison, and an inline constant can be used. Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D50629 Change-Id: Id87c3b7975839da0de8156a124b0ce98c5fb47f2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340903 91177308-0d34-0410-b5e6-96231b3b80d8 Nicolai Haehnle 1 year, 5 months ago
5 changed file(s) with 48 addition(s) and 37 deletion(s). Raw diff Collapse all Expand all
300300 MCInstLowering.lower(MI, TmpInst);
301301 EmitToStreamer(*OutStreamer, TmpInst);
302302
303 #ifdef EXPENSIVE_CHECKS
304 // Sanity-check getInstSizeInBytes on explicitly specified CPUs (it cannot
305 // work correctly for the generic CPU).
306 //
307 // The isPseudo check really shouldn't be here, but unfortunately there are
308 // some negative lit tests that depend on being able to continue through
309 // here even when pseudo instructions haven't been lowered.
310 if (!MI->isPseudo() && STI.isCPUStringValid(STI.getCPU())) {
311 SmallVector Fixups;
312 SmallVector CodeBytes;
313 raw_svector_ostream CodeStream(CodeBytes);
314
315 std::unique_ptr InstEmitter(createSIMCCodeEmitter(
316 *STI.getInstrInfo(), *OutContext.getRegisterInfo(), OutContext));
317 InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
318
319 assert(CodeBytes.size() == STI.getInstrInfo()->getInstSizeInBytes(*MI));
320 }
321 #endif
322
303323 if (STI.dumpCode()) {
304324 // Disassemble instruction/operands to text.
305325 DisasmLines.resize(DisasmLines.size() + 1);
23972397 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
23982398 case AMDGPU::OPERAND_REG_INLINE_C_FP32: {
23992399 int32_t Trunc = static_cast(Imm);
2400 return Trunc == Imm &&
2401 AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
2400 return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
24022401 }
24032402 case AMDGPU::OPERAND_REG_IMM_INT64:
24042403 case AMDGPU::OPERAND_REG_IMM_FP64:
49744973
49754974 // If we have a definitive size, we can use it. Otherwise we need to inspect
49764975 // the operands to know the size.
4977 //
4978 // FIXME: Instructions that have a base 32-bit encoding report their size as
4979 // 4, even though they are really 8 bytes if they have a literal operand.
4980 if (DescSize != 0 && DescSize != 4)
4981 return DescSize;
4982
49834976 if (isFixedSize(MI))
49844977 return DescSize;
49854978
49884981 if (isVALU(MI) || isSALU(MI)) {
49894982 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
49904983 if (Src0Idx == -1)
4991 return 4; // No operands.
4984 return DescSize; // No operands.
49924985
49934986 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
4994 return 8;
4987 return DescSize + 4;
49954988
49964989 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
49974990 if (Src1Idx == -1)
4998 return 4;
4991 return DescSize;
49994992
50004993 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
5001 return 8;
5002
5003 return 4;
5004 }
5005
5006 if (DescSize == 4)
5007 return 4;
4994 return DescSize + 4;
4995
4996 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
4997 if (Src2Idx == -1)
4998 return DescSize;
4999
5000 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
5001 return DescSize + 4;
5002
5003 return DescSize;
5004 }
50085005
50095006 switch (Opc) {
50105007 case TargetOpcode::IMPLICIT_DEF:
50205017 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
50215018 }
50225019 default:
5023 llvm_unreachable("unable to find instruction size");
5020 return DescSize;
50245021 }
50255022 }
50265023
715715
716716 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
717717
718 multiclass VOP32_Real_vi op> {
719 def _vi :
720 VOP2_Real(NAME), SIEncodingFamily.VI>,
721 VOP3e_vi(NAME).Pfl>;
722 }
723
724718 multiclass VOP2_Real_MADK_vi op> {
725719 def _vi : VOP2_Real(NAME), SIEncodingFamily.VI>,
726720 VOP2_MADKe(NAME).Pfl>;
898892 defm V_SUB_U32 : VOP2_Real_e32e64_gfx9 <0x35>;
899893 defm V_SUBREV_U32 : VOP2_Real_e32e64_gfx9 <0x36>;
900894
901 defm V_READLANE_B32 : VOP32_Real_vi <0x289>;
902 defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>;
903
904895 defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;
905896 defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>;
906897 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>;
650650 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
651651
652652 multiclass VOP3_Real_vi op> {
653 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
654 VOP3e_vi (NAME).Pfl>;
653 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
654 VOP3e_vi (NAME).Pfl>;
655655 }
656656
657657 multiclass VOP3be_Real_vi op> {
658 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
659 VOP3be_vi (NAME).Pfl>;
658 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
659 VOP3be_vi (NAME).Pfl>;
660660 }
661661
662662 multiclass VOP3OpSel_Real_gfx9 op> {
663 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
664 VOP3OpSel_gfx9 (NAME).Pfl>;
663 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
664 VOP3OpSel_gfx9 (NAME).Pfl>;
665665 }
666666
667667 multiclass VOP3Interp_Real_vi op> {
668 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
669 VOP3Interp_vi (NAME).Pfl>;
668 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
669 VOP3Interp_vi (NAME).Pfl>;
670670 }
671671
672672 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
812812 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
813813 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
814814
815 defm V_READLANE_B32 : VOP3_Real_vi <0x289>;
816 defm V_WRITELANE_B32 : VOP3_Real_vi <0x28a>;
817
815818 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
816819 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
817820 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
None ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
0 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s
11 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
22
33 declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0