llvm.org GIT mirror llvm / 1203fe7
Revert r141854 because it was causing failures: http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 9 years ago
7 changed file(s) with 5 addition(s) and 105 deletion(s). Raw diff Collapse all Expand all
103103 "Support 16-bit floating point conversion instructions">;
104104 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
105105 "Support LZCNT instruction">;
106 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
107 "Support BMI instructions">;
108106
109107 //===----------------------------------------------------------------------===//
110108 // X86 processors supported.
158156 def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
159157 FeatureAES, FeatureCLMUL,
160158 FeatureRDRAND, FeatureF16C]>;
161 // Haswell
162 def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
163 FeatureCLMUL, FeatureRDRAND, FeatureF16C,
164 FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
165 FeatureBMI]>;
166159
167160 def : Proc<"k6", [FeatureMMX]>;
168161 def : Proc<"k6-2", [Feature3DNow]>;
378378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
380380
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 } else {
384 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
385 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
386 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
387 if (Subtarget->is64Bit())
388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
389 }
381 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
383 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
390386
391387 if (Subtarget->hasLZCNT()) {
392388 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477477 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
478478 def HasF16C : Predicate<"Subtarget->hasF16C()">;
479479 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
480 def HasBMI : Predicate<"Subtarget->hasBMI()">;
481480 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
482481 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
483482 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
13731372 }
13741373
13751374 //===----------------------------------------------------------------------===//
1376 // BMI Instructions
1377 //
1378 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1379 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1380 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1381 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1382 OpSize;
1383 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1384 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1385 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1386 (implicit EFLAGS)]>, XS, OpSize;
1387
1388 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1389 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1390 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
1391 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1392 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1393 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1394 (implicit EFLAGS)]>, XS;
1395
1396 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1397 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1398 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1399 XS;
1400 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1401 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1402 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1403 (implicit EFLAGS)]>, XS;
1404 }
1405
1406 //===----------------------------------------------------------------------===//
14071375 // Subsystems.
14081376 //===----------------------------------------------------------------------===//
14091377
100100
101101 /// HasLZCNT - Processor has LZCNT instruction.
102102 bool HasLZCNT;
103
104 /// HasBMI - Processor has BMI1 instructions.
105 bool HasBMI;
106103
107104 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
108105 bool IsBTMemSlow;
190187 bool hasRDRAND() const { return HasRDRAND; }
191188 bool hasF16C() const { return HasF16C; }
192189 bool hasLZCNT() const { return HasLZCNT; }
193 bool hasBMI() const { return HasBMI; }
194190 bool isBTMemSlow() const { return IsBTMemSlow; }
195191 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
196192 bool hasVectorUAMem() const { return HasVectorUAMem; }
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test/CodeGen/X86/bmi.ll less more
None ; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
1
2 define i32 @t1(i32 %x) nounwind {
3 %tmp = tail call i32 @llvm.cttz.i32( i32 %x )
4 ret i32 %tmp
5 ; CHECK: t1:
6 ; CHECK: tzcntl
7 }
8
9 declare i32 @llvm.cttz.i32(i32) nounwind readnone
10
11 define i16 @t2(i16 %x) nounwind {
12 %tmp = tail call i16 @llvm.cttz.i16( i16 %x )
13 ret i16 %tmp
14 ; CHECK: t2:
15 ; CHECK: tzcntw
16 }
17
18 declare i16 @llvm.cttz.i16(i16) nounwind readnone
19
20 define i64 @t3(i64 %x) nounwind {
21 %tmp = tail call i64 @llvm.cttz.i64( i64 %x )
22 ret i64 %tmp
23 ; CHECK: t3:
24 ; CHECK: tzcntq
25 }
26
27 declare i64 @llvm.cttz.i64(i64) nounwind readnone
28
29 define i8 @t4(i8 %x) nounwind {
30 %tmp = tail call i8 @llvm.cttz.i8( i8 %x )
31 ret i8 %tmp
32 ; CHECK: t4:
33 ; CHECK: tzcntw
34 }
35
36 declare i8 @llvm.cttz.i8(i8) nounwind readnone
37
496496
497497 # CHECK: lzcntq %rax, %rax
498498 0xf3 0x48 0x0f 0xbd 0xc0
499
500 # CHECK: tzcntl %eax, %eax
501 0xf3 0x0f 0xbc 0xc0
502
503 # CHECK: tzcntw %ax, %ax
504 0x66 0xf3 0x0f 0xbc 0xc0
505
506 # CHECK: tzcntq %rax, %rax
507 0xf3 0x48 0x0f 0xbc 0xc0
476476
477477 # CHECK: lzcntw %ax, %ax
478478 0x66 0xf3 0x0f 0xbd 0xc0
479
480 # CHECK: tzcntl %eax, %eax
481 0xf3 0x0f 0xbc 0xc0
482
483 # CHECK: tzcntw %ax, %ax
484 0x66 0xf3 0x0f 0xbc 0xc0