llvm.org GIT mirror llvm / 11fad6e
Move Target{Instr,Register}Info.cpp into lib/CodeGen. The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168758 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
6 changed file(s) with 338 addition(s) and 338 deletion(s). Raw diff Collapse all Expand all
9898 StrongPHIElimination.cpp
9999 TailDuplication.cpp
100100 TargetFrameLoweringImpl.cpp
101 TargetInstrInfo.cpp
101102 TargetInstrInfoImpl.cpp
102103 TargetLoweringObjectFileImpl.cpp
103104 TargetOptionsImpl.cpp
105 TargetRegisterInfo.cpp
104106 TargetSchedule.cpp
105107 TwoAddressInstructionPass.cpp
106108 UnreachableBlockElim.cpp
0 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Target/TargetInstrInfo.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCInstrItineraries.h"
17 #include "llvm/Support/ErrorHandling.h"
18 #include
19 using namespace llvm;
20
21 //===----------------------------------------------------------------------===//
22 // TargetInstrInfo
23 //
24 // Methods that depend on CodeGen are implemented in
25 // TargetInstrInfoImpl.cpp. Invoking them without linking libCodeGen raises a
26 // link error.
27 // ===----------------------------------------------------------------------===//
28
29 TargetInstrInfo::~TargetInstrInfo() {
30 }
31
32 const TargetRegisterClass*
33 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
34 const TargetRegisterInfo *TRI,
35 const MachineFunction &MF) const {
36 if (OpNum >= MCID.getNumOperands())
37 return 0;
38
39 short RegClass = MCID.OpInfo[OpNum].RegClass;
40 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
41 return TRI->getPointerRegClass(MF, RegClass);
42
43 // Instructions like INSERT_SUBREG do not have fixed register classes.
44 if (RegClass < 0)
45 return 0;
46
47 // Otherwise just look it up normally.
48 return TRI->getRegClass(RegClass);
49 }
50
51 /// insertNoop - Insert a noop into the instruction stream at the specified
52 /// point.
53 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MI) const {
55 llvm_unreachable("Target didn't implement insertNoop!");
56 }
57
58 /// Measure the specified inline asm to determine an approximation of its
59 /// length.
60 /// Comments (which run till the next SeparatorString or newline) do not
61 /// count as an instruction.
62 /// Any other non-whitespace text is considered an instruction, with
63 /// multiple instructions separated by SeparatorString or newlines.
64 /// Variable-length instructions are not handled here; this function
65 /// may be overloaded in the target code to do that.
66 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
67 const MCAsmInfo &MAI) const {
68
69
70 // Count the number of instructions in the asm.
71 bool atInsnStart = true;
72 unsigned Length = 0;
73 for (; *Str; ++Str) {
74 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
75 strlen(MAI.getSeparatorString())) == 0)
76 atInsnStart = true;
77 if (atInsnStart && !std::isspace(*Str)) {
78 Length += MAI.getMaxInstLength();
79 atInsnStart = false;
80 }
81 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
82 strlen(MAI.getCommentString())) == 0)
83 atInsnStart = false;
84 }
85
86 return Length;
87 }
0 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Support/raw_ostream.h"
17
18 using namespace llvm;
19
20 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
21 regclass_iterator RCB, regclass_iterator RCE,
22 const char *const *SRINames,
23 const unsigned *SRILaneMasks)
24 : InfoDesc(ID), SubRegIndexNames(SRINames),
25 SubRegIndexLaneMasks(SRILaneMasks),
26 RegClassBegin(RCB), RegClassEnd(RCE) {
27 }
28
29 TargetRegisterInfo::~TargetRegisterInfo() {}
30
31 void PrintReg::print(raw_ostream &OS) const {
32 if (!Reg)
33 OS << "%noreg";
34 else if (TargetRegisterInfo::isStackSlot(Reg))
35 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
36 else if (TargetRegisterInfo::isVirtualRegister(Reg))
37 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
38 else if (TRI && Reg < TRI->getNumRegs())
39 OS << '%' << TRI->getName(Reg);
40 else
41 OS << "%physreg" << Reg;
42 if (SubIdx) {
43 if (TRI)
44 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 else
46 OS << ":sub(" << SubIdx << ')';
47 }
48 }
49
50 void PrintRegUnit::print(raw_ostream &OS) const {
51 // Generic printout when TRI is missing.
52 if (!TRI) {
53 OS << "Unit~" << Unit;
54 return;
55 }
56
57 // Check for invalid register units.
58 if (Unit >= TRI->getNumRegUnits()) {
59 OS << "BadUnit~" << Unit;
60 return;
61 }
62
63 // Normal units have at least one root.
64 MCRegUnitRootIterator Roots(Unit, TRI);
65 assert(Roots.isValid() && "Unit has no roots.");
66 OS << TRI->getName(*Roots);
67 for (++Roots; Roots.isValid(); ++Roots)
68 OS << '~' << TRI->getName(*Roots);
69 }
70
71 /// getAllocatableClass - Return the maximal subclass of the given register
72 /// class that is alloctable, or NULL.
73 const TargetRegisterClass *
74 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
75 if (!RC || RC->isAllocatable())
76 return RC;
77
78 const unsigned *SubClass = RC->getSubClassMask();
79 for (unsigned Base = 0, BaseE = getNumRegClasses();
80 Base < BaseE; Base += 32) {
81 unsigned Idx = Base;
82 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
83 unsigned Offset = CountTrailingZeros_32(Mask);
84 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
85 if (SubRC->isAllocatable())
86 return SubRC;
87 Mask >>= Offset;
88 Idx += Offset + 1;
89 }
90 }
91 return NULL;
92 }
93
94 /// getMinimalPhysRegClass - Returns the Register Class of a physical
95 /// register of the given type, picking the most sub register class of
96 /// the right type that contains this physreg.
97 const TargetRegisterClass *
98 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
99 assert(isPhysicalRegister(reg) && "reg must be a physical register");
100
101 // Pick the most sub register class of the right type that contains
102 // this physreg.
103 const TargetRegisterClass* BestRC = 0;
104 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
105 const TargetRegisterClass* RC = *I;
106 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
107 (!BestRC || BestRC->hasSubClass(RC)))
108 BestRC = RC;
109 }
110
111 assert(BestRC && "Couldn't find the register class");
112 return BestRC;
113 }
114
115 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
116 /// registers for the specific register class.
117 static void getAllocatableSetForRC(const MachineFunction &MF,
118 const TargetRegisterClass *RC, BitVector &R){
119 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
120 ArrayRef Order = RC->getRawAllocationOrder(MF);
121 for (unsigned i = 0; i != Order.size(); ++i)
122 R.set(Order[i]);
123 }
124
125 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
126 const TargetRegisterClass *RC) const {
127 BitVector Allocatable(getNumRegs());
128 if (RC) {
129 // A register class with no allocatable subclass returns an empty set.
130 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
131 if (SubClass)
132 getAllocatableSetForRC(MF, SubClass, Allocatable);
133 } else {
134 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
135 E = regclass_end(); I != E; ++I)
136 if ((*I)->isAllocatable())
137 getAllocatableSetForRC(MF, *I, Allocatable);
138 }
139
140 // Mask out the reserved registers
141 BitVector Reserved = getReservedRegs(MF);
142 Allocatable &= Reserved.flip();
143
144 return Allocatable;
145 }
146
147 static inline
148 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
149 const uint32_t *B,
150 const TargetRegisterInfo *TRI) {
151 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
152 if (unsigned Common = *A++ & *B++)
153 return TRI->getRegClass(I + CountTrailingZeros_32(Common));
154 return 0;
155 }
156
157 const TargetRegisterClass *
158 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
159 const TargetRegisterClass *B) const {
160 // First take care of the trivial cases.
161 if (A == B)
162 return A;
163 if (!A || !B)
164 return 0;
165
166 // Register classes are ordered topologically, so the largest common
167 // sub-class it the common sub-class with the smallest ID.
168 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
169 }
170
171 const TargetRegisterClass *
172 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
173 const TargetRegisterClass *B,
174 unsigned Idx) const {
175 assert(A && B && "Missing register class");
176 assert(Idx && "Bad sub-register index");
177
178 // Find Idx in the list of super-register indices.
179 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
180 if (RCI.getSubReg() == Idx)
181 // The bit mask contains all register classes that are projected into B
182 // by Idx. Find a class that is also a sub-class of A.
183 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
184 return 0;
185 }
186
187 const TargetRegisterClass *TargetRegisterInfo::
188 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
189 const TargetRegisterClass *RCB, unsigned SubB,
190 unsigned &PreA, unsigned &PreB) const {
191 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
192
193 // Search all pairs of sub-register indices that project into RCA and RCB
194 // respectively. This is quadratic, but usually the sets are very small. On
195 // most targets like X86, there will only be a single sub-register index
196 // (e.g., sub_16bit projecting into GR16).
197 //
198 // The worst case is a register class like DPR on ARM.
199 // We have indices dsub_0..dsub_7 projecting into that class.
200 //
201 // It is very common that one register class is a sub-register of the other.
202 // Arrange for RCA to be the larger register so the answer will be found in
203 // the first iteration. This makes the search linear for the most common
204 // case.
205 const TargetRegisterClass *BestRC = 0;
206 unsigned *BestPreA = &PreA;
207 unsigned *BestPreB = &PreB;
208 if (RCA->getSize() < RCB->getSize()) {
209 std::swap(RCA, RCB);
210 std::swap(SubA, SubB);
211 std::swap(BestPreA, BestPreB);
212 }
213
214 // Also terminate the search one we have found a register class as small as
215 // RCA.
216 unsigned MinSize = RCA->getSize();
217
218 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
219 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
220 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
221 // Check if a common super-register class exists for this index pair.
222 const TargetRegisterClass *RC =
223 firstCommonClass(IA.getMask(), IB.getMask(), this);
224 if (!RC || RC->getSize() < MinSize)
225 continue;
226
227 // The indexes must compose identically: PreA+SubA == PreB+SubB.
228 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
229 if (FinalA != FinalB)
230 continue;
231
232 // Is RC a better candidate than BestRC?
233 if (BestRC && RC->getSize() >= BestRC->getSize())
234 continue;
235
236 // Yes, RC is the smallest super-register seen so far.
237 BestRC = RC;
238 *BestPreA = IA.getSubReg();
239 *BestPreB = IB.getSubReg();
240
241 // Bail early if we reached MinSize. We won't find a better candidate.
242 if (BestRC->getSize() == MinSize)
243 return BestRC;
244 }
245 }
246 return BestRC;
247 }
0 add_llvm_library(LLVMTarget
11 Mangler.cpp
22 Target.cpp
3 TargetInstrInfo.cpp
43 TargetIntrinsicInfo.cpp
54 TargetJITInfo.cpp
65 TargetLibraryInfo.cpp
76 TargetLoweringObjectFile.cpp
87 TargetMachine.cpp
98 TargetMachineC.cpp
10 TargetRegisterInfo.cpp
119 TargetSubtargetInfo.cpp
1210 TargetTransformImpl.cpp
1311 )
+0
-88
lib/Target/TargetInstrInfo.cpp less more
None //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Target/TargetInstrInfo.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCInstrItineraries.h"
17 #include "llvm/Support/ErrorHandling.h"
18 #include
19 using namespace llvm;
20
21 //===----------------------------------------------------------------------===//
22 // TargetInstrInfo
23 //
24 // Methods that depend on CodeGen are implemented in
25 // TargetInstrInfoImpl.cpp. Invoking them without linking libCodeGen raises a
26 // link error.
27 // ===----------------------------------------------------------------------===//
28
29 TargetInstrInfo::~TargetInstrInfo() {
30 }
31
32 const TargetRegisterClass*
33 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
34 const TargetRegisterInfo *TRI,
35 const MachineFunction &MF) const {
36 if (OpNum >= MCID.getNumOperands())
37 return 0;
38
39 short RegClass = MCID.OpInfo[OpNum].RegClass;
40 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
41 return TRI->getPointerRegClass(MF, RegClass);
42
43 // Instructions like INSERT_SUBREG do not have fixed register classes.
44 if (RegClass < 0)
45 return 0;
46
47 // Otherwise just look it up normally.
48 return TRI->getRegClass(RegClass);
49 }
50
51 /// insertNoop - Insert a noop into the instruction stream at the specified
52 /// point.
53 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MI) const {
55 llvm_unreachable("Target didn't implement insertNoop!");
56 }
57
58 /// Measure the specified inline asm to determine an approximation of its
59 /// length.
60 /// Comments (which run till the next SeparatorString or newline) do not
61 /// count as an instruction.
62 /// Any other non-whitespace text is considered an instruction, with
63 /// multiple instructions separated by SeparatorString or newlines.
64 /// Variable-length instructions are not handled here; this function
65 /// may be overloaded in the target code to do that.
66 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
67 const MCAsmInfo &MAI) const {
68
69
70 // Count the number of instructions in the asm.
71 bool atInsnStart = true;
72 unsigned Length = 0;
73 for (; *Str; ++Str) {
74 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
75 strlen(MAI.getSeparatorString())) == 0)
76 atInsnStart = true;
77 if (atInsnStart && !std::isspace(*Str)) {
78 Length += MAI.getMaxInstLength();
79 atInsnStart = false;
80 }
81 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
82 strlen(MAI.getCommentString())) == 0)
83 atInsnStart = false;
84 }
85
86 return Length;
87 }
+0
-248
lib/Target/TargetRegisterInfo.cpp less more
None //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Support/raw_ostream.h"
17
18 using namespace llvm;
19
20 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
21 regclass_iterator RCB, regclass_iterator RCE,
22 const char *const *SRINames,
23 const unsigned *SRILaneMasks)
24 : InfoDesc(ID), SubRegIndexNames(SRINames),
25 SubRegIndexLaneMasks(SRILaneMasks),
26 RegClassBegin(RCB), RegClassEnd(RCE) {
27 }
28
29 TargetRegisterInfo::~TargetRegisterInfo() {}
30
31 void PrintReg::print(raw_ostream &OS) const {
32 if (!Reg)
33 OS << "%noreg";
34 else if (TargetRegisterInfo::isStackSlot(Reg))
35 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
36 else if (TargetRegisterInfo::isVirtualRegister(Reg))
37 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
38 else if (TRI && Reg < TRI->getNumRegs())
39 OS << '%' << TRI->getName(Reg);
40 else
41 OS << "%physreg" << Reg;
42 if (SubIdx) {
43 if (TRI)
44 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 else
46 OS << ":sub(" << SubIdx << ')';
47 }
48 }
49
50 void PrintRegUnit::print(raw_ostream &OS) const {
51 // Generic printout when TRI is missing.
52 if (!TRI) {
53 OS << "Unit~" << Unit;
54 return;
55 }
56
57 // Check for invalid register units.
58 if (Unit >= TRI->getNumRegUnits()) {
59 OS << "BadUnit~" << Unit;
60 return;
61 }
62
63 // Normal units have at least one root.
64 MCRegUnitRootIterator Roots(Unit, TRI);
65 assert(Roots.isValid() && "Unit has no roots.");
66 OS << TRI->getName(*Roots);
67 for (++Roots; Roots.isValid(); ++Roots)
68 OS << '~' << TRI->getName(*Roots);
69 }
70
71 /// getAllocatableClass - Return the maximal subclass of the given register
72 /// class that is alloctable, or NULL.
73 const TargetRegisterClass *
74 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
75 if (!RC || RC->isAllocatable())
76 return RC;
77
78 const unsigned *SubClass = RC->getSubClassMask();
79 for (unsigned Base = 0, BaseE = getNumRegClasses();
80 Base < BaseE; Base += 32) {
81 unsigned Idx = Base;
82 for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
83 unsigned Offset = CountTrailingZeros_32(Mask);
84 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
85 if (SubRC->isAllocatable())
86 return SubRC;
87 Mask >>= Offset;
88 Idx += Offset + 1;
89 }
90 }
91 return NULL;
92 }
93
94 /// getMinimalPhysRegClass - Returns the Register Class of a physical
95 /// register of the given type, picking the most sub register class of
96 /// the right type that contains this physreg.
97 const TargetRegisterClass *
98 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
99 assert(isPhysicalRegister(reg) && "reg must be a physical register");
100
101 // Pick the most sub register class of the right type that contains
102 // this physreg.
103 const TargetRegisterClass* BestRC = 0;
104 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
105 const TargetRegisterClass* RC = *I;
106 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
107 (!BestRC || BestRC->hasSubClass(RC)))
108 BestRC = RC;
109 }
110
111 assert(BestRC && "Couldn't find the register class");
112 return BestRC;
113 }
114
115 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
116 /// registers for the specific register class.
117 static void getAllocatableSetForRC(const MachineFunction &MF,
118 const TargetRegisterClass *RC, BitVector &R){
119 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
120 ArrayRef Order = RC->getRawAllocationOrder(MF);
121 for (unsigned i = 0; i != Order.size(); ++i)
122 R.set(Order[i]);
123 }
124
125 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
126 const TargetRegisterClass *RC) const {
127 BitVector Allocatable(getNumRegs());
128 if (RC) {
129 // A register class with no allocatable subclass returns an empty set.
130 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
131 if (SubClass)
132 getAllocatableSetForRC(MF, SubClass, Allocatable);
133 } else {
134 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
135 E = regclass_end(); I != E; ++I)
136 if ((*I)->isAllocatable())
137 getAllocatableSetForRC(MF, *I, Allocatable);
138 }
139
140 // Mask out the reserved registers
141 BitVector Reserved = getReservedRegs(MF);
142 Allocatable &= Reserved.flip();
143
144 return Allocatable;
145 }
146
147 static inline
148 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
149 const uint32_t *B,
150 const TargetRegisterInfo *TRI) {
151 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
152 if (unsigned Common = *A++ & *B++)
153 return TRI->getRegClass(I + CountTrailingZeros_32(Common));
154 return 0;
155 }
156
157 const TargetRegisterClass *
158 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
159 const TargetRegisterClass *B) const {
160 // First take care of the trivial cases.
161 if (A == B)
162 return A;
163 if (!A || !B)
164 return 0;
165
166 // Register classes are ordered topologically, so the largest common
167 // sub-class it the common sub-class with the smallest ID.
168 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
169 }
170
171 const TargetRegisterClass *
172 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
173 const TargetRegisterClass *B,
174 unsigned Idx) const {
175 assert(A && B && "Missing register class");
176 assert(Idx && "Bad sub-register index");
177
178 // Find Idx in the list of super-register indices.
179 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
180 if (RCI.getSubReg() == Idx)
181 // The bit mask contains all register classes that are projected into B
182 // by Idx. Find a class that is also a sub-class of A.
183 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
184 return 0;
185 }
186
187 const TargetRegisterClass *TargetRegisterInfo::
188 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
189 const TargetRegisterClass *RCB, unsigned SubB,
190 unsigned &PreA, unsigned &PreB) const {
191 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
192
193 // Search all pairs of sub-register indices that project into RCA and RCB
194 // respectively. This is quadratic, but usually the sets are very small. On
195 // most targets like X86, there will only be a single sub-register index
196 // (e.g., sub_16bit projecting into GR16).
197 //
198 // The worst case is a register class like DPR on ARM.
199 // We have indices dsub_0..dsub_7 projecting into that class.
200 //
201 // It is very common that one register class is a sub-register of the other.
202 // Arrange for RCA to be the larger register so the answer will be found in
203 // the first iteration. This makes the search linear for the most common
204 // case.
205 const TargetRegisterClass *BestRC = 0;
206 unsigned *BestPreA = &PreA;
207 unsigned *BestPreB = &PreB;
208 if (RCA->getSize() < RCB->getSize()) {
209 std::swap(RCA, RCB);
210 std::swap(SubA, SubB);
211 std::swap(BestPreA, BestPreB);
212 }
213
214 // Also terminate the search one we have found a register class as small as
215 // RCA.
216 unsigned MinSize = RCA->getSize();
217
218 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
219 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
220 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
221 // Check if a common super-register class exists for this index pair.
222 const TargetRegisterClass *RC =
223 firstCommonClass(IA.getMask(), IB.getMask(), this);
224 if (!RC || RC->getSize() < MinSize)
225 continue;
226
227 // The indexes must compose identically: PreA+SubA == PreB+SubB.
228 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
229 if (FinalA != FinalB)
230 continue;
231
232 // Is RC a better candidate than BestRC?
233 if (BestRC && RC->getSize() >= BestRC->getSize())
234 continue;
235
236 // Yes, RC is the smallest super-register seen so far.
237 BestRC = RC;
238 *BestPreA = IA.getSubReg();
239 *BestPreB = IB.getSubReg();
240
241 // Bail early if we reached MinSize. We won't find a better candidate.
242 if (BestRC->getSize() == MinSize)
243 return BestRC;
244 }
245 }
246 return BestRC;
247 }