llvm.org GIT mirror llvm / 11a3b12
[RISCV] Improve codegen for icmp {ne,eq} with a constant Adds two patterns to improve the codegen of GPR value comparisons with small constants. Instead of first loading the constant into another register and then doing an XOR of those registers, these patterns directly use the constant as an XORI immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356990 91177308-0d34-0410-b5e6-96231b3b80d8 Luis Marques 1 year, 8 months ago
2 changed file(s) with 26 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
770770 // handled by a RISC-V instruction.
771771 def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>;
772772 def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
773 def : Pat<(seteq GPR:$rs1, simm12:$imm12),
774 (SLTIU (XORI GPR:$rs1, simm12:$imm12), 1)>;
773775 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
774776 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
777 def : Pat<(setne GPR:$rs1, simm12:$imm12),
778 (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>;
775779 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
776780 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
777781 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
1111 ; RV32I-NEXT: seqz a0, a0
1212 ; RV32I-NEXT: ret
1313 %1 = icmp eq i32 %a, %b
14 %2 = zext i1 %1 to i32
15 ret i32 %2
16 }
17
18 define i32 @icmp_eq_constant(i32 %a) nounwind {
19 ; RV32I-LABEL: icmp_eq_constant:
20 ; RV32I: # %bb.0:
21 ; RV32I-NEXT: xori a0, a0, 42
22 ; RV32I-NEXT: seqz a0, a0
23 ; RV32I-NEXT: ret
24 %1 = icmp eq i32 %a, 42
1425 %2 = zext i1 %1 to i32
1526 ret i32 %2
1627 }
3243 ; RV32I-NEXT: snez a0, a0
3344 ; RV32I-NEXT: ret
3445 %1 = icmp ne i32 %a, %b
46 %2 = zext i1 %1 to i32
47 ret i32 %2
48 }
49
50 define i32 @icmp_ne_constant(i32 %a) nounwind {
51 ; RV32I-LABEL: icmp_ne_constant:
52 ; RV32I: # %bb.0:
53 ; RV32I-NEXT: xori a0, a0, 42
54 ; RV32I-NEXT: snez a0, a0
55 ; RV32I-NEXT: ret
56 %1 = icmp ne i32 %a, 42
3557 %2 = zext i1 %1 to i32
3658 ret i32 %2
3759 }