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ARM: disallow add/sub to sp unless Rn is also sp. The manual says that Thumb2 add/sub instructions are only allowed to modify sp if the first source is also sp. This is slightly different from the usual rGPR restriction since it's context-sensitive, so implement it in C++. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358987 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 1 year, 3 months ago
4 changed file(s) with 78 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
67896789 return Error(Operands[4]->getStartLoc(),
67906790 "source register must be the same as destination");
67916791 }
6792 break;
6793
6794 case ARM::t2ADDri:
6795 case ARM::t2ADDri12:
6796 case ARM::t2ADDrr:
6797 case ARM::t2ADDrs:
6798 case ARM::t2SUBri:
6799 case ARM::t2SUBri12:
6800 case ARM::t2SUBrr:
6801 case ARM::t2SUBrs:
6802 if (Inst.getOperand(0).getReg() == ARM::SP &&
6803 Inst.getOperand(1).getReg() != ARM::SP)
6804 return Error(Operands[4]->getStartLoc(),
6805 "source register must be sp if destination is sp");
67926806 break;
67936807
67946808 // Final range checking for Thumb unconditional branch instructions.
440440 return MCDisassembler::SoftFail;
441441 return Result;
442442 }
443 case ARM::t2ADDri:
444 case ARM::t2ADDri12:
445 case ARM::t2ADDrr:
446 case ARM::t2ADDrs:
447 case ARM::t2SUBri:
448 case ARM::t2SUBri12:
449 case ARM::t2SUBrr:
450 case ARM::t2SUBrs:
451 if (MI.getOperand(0).getReg() == ARM::SP &&
452 MI.getOperand(1).getReg() != ARM::SP)
453 return MCDisassembler::SoftFail;
454 return Result;
443455 default: return Result;
444456 }
445457 }
771783 if (Result != MCDisassembler::Fail) {
772784 Size = 4;
773785 Check(Result, AddThumbPredicate(MI));
774 return Result;
786 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result);
775787 }
776788
777789 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
0 @ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o - 2>&1 | FileCheck %s
1
2 @ CHECK: error: source register must be sp if destination is sp
3 @ CHECK: error: source register must be sp if destination is sp
4 @ CHECK: error: source register must be sp if destination is sp
5 @ CHECK: error: source register must be sp if destination is sp
6 add sp, r5, #1
7 addw sp, r7, #4
8 add sp, r3, r2
9 add sp, r3, r5, lsl #3
10
11
12 @ CHECK: error: source register must be sp if destination is sp
13 @ CHECK: error: source register must be sp if destination is sp
14 @ CHECK: error: source register must be sp if destination is sp
15 @ CHECK: error: source register must be sp if destination is sp
16 sub sp, r5, #1
17 subw sp, r7, #4
18 sub sp, r3, r2
19 sub sp, r3, r5, lsl #3
393393 [0xff,0xf3,0x30,0x80]
394394 # CHECK: invalid instruction encoding
395395 # CHECK-NEXT: [0xff,0xf3,0x30,0x80]
396
397 #------------------------------------------------------------------------------
398 # If dest is sp then source must be in T2 add/sub
399 #------------------------------------------------------------------------------
400
401 [0x05,0xf1,0x01,0x0d]
402 [0x07,0xf2,0x04,0x0d]
403 [0x03,0xeb,0x02,0x0d]
404 [0x03,0xeb,0xc5,0x0d]
405 # CHECK-V7: warning: potentially undefined instruction encoding
406 # CHECK-V7-NEXT: [0x05,0xf1,0x01,0x0d]
407 # CHECK-V7: warning: potentially undefined instruction encoding
408 # CHECK-V7-NEXT: [0x07,0xf2,0x04,0x0d]
409 # CHECK-V7: warning: potentially undefined instruction encoding
410 # CHECK-V7-NEXT: [0x03,0xeb,0x02,0x0d]
411 # CHECK-V7: warning: potentially undefined instruction encoding
412 # CHECK-V7-NEXT: [0x03,0xeb,0xc5,0x0d]
413
414
415 [0xa5,0xf1,0x01,0x0d]
416 [0xa7,0xf2,0x04,0x0d]
417 [0xa3,0xeb,0x02,0x0d]
418 [0xa3,0xeb,0xc5,0x0d]
419 # CHECK-V7: warning: potentially undefined instruction encoding
420 # CHECK-V7-NEXT: [0xa5,0xf1,0x01,0x0d]
421 # CHECK-V7: warning: potentially undefined instruction encoding
422 # CHECK-V7-NEXT: [0xa7,0xf2,0x04,0x0d]
423 # CHECK-V7: warning: potentially undefined instruction encoding
424 # CHECK-V7-NEXT: [0xa3,0xeb,0x02,0x0d]
425 # CHECK-V7: warning: potentially undefined instruction encoding
426 # CHECK-V7-NEXT: [0xa3,0xeb,0xc5,0x0d]