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[ARM] Fix assembly and disassembly for VMRS/VMSR This patch addresses two issues with assembly and disassembly for VMRS/VMSR: 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets. 2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC. This patch addresses those issues and adds tests for these cases. Differential Revision: https://reviews.llvm.org/D36306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310243 91177308-0d34-0410-b5e6-96231b3b80d8 Andre Vieira 3 years ago
9 changed file(s) with 436 addition(s) and 64 deletion(s). Raw diff Collapse all Expand all
21592159 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
21602160 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
21612161
2162 // Application level FPSCR -> GPR
2163 let hasSideEffects = 1, Uses = [FPSCR] in
2164 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
2165 "vmrs", "\t$Rt, fpscr",
2166 [(set GPR:$Rt, (int_arm_get_fpscr))]>;
2167
2168 // System level FPEXC, FPSID -> GPR
2169 let Uses = [FPSCR] in {
2170 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
2171 "vmrs", "\t$Rt, fpexc", []>;
2172 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
2173 "vmrs", "\t$Rt, fpsid", []>;
2174 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPR:$Rt), (ins),
2175 "vmrs", "\t$Rt, mvfr0", []>;
2176 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
2177 "vmrs", "\t$Rt, mvfr1", []>;
2178 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
2179 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
2180 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
2181 "vmrs", "\t$Rt, fpinst", []>;
2182 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
2183 "vmrs", "\t$Rt, fpinst2", []>;
2162 let DecoderMethod = "DecodeForVMRSandVMSR" in {
2163 // Application level FPSCR -> GPR
2164 let hasSideEffects = 1, Uses = [FPSCR] in
2165 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins),
2166 "vmrs", "\t$Rt, fpscr",
2167 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>;
2168
2169 // System level FPEXC, FPSID -> GPR
2170 let Uses = [FPSCR] in {
2171 let Predicates = [HasV8, HasVFP2] in {
2172 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins),
2173 "vmrs", "\t$Rt, fpexc", []>;
2174 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins),
2175 "vmrs", "\t$Rt, fpsid", []>;
2176 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins),
2177 "vmrs", "\t$Rt, mvfr0", []>;
2178 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins),
2179 "vmrs", "\t$Rt, mvfr1", []>;
2180 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),
2181 "vmrs", "\t$Rt, mvfr2", []>;
2182 }
2183 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins),
2184 "vmrs", "\t$Rt, fpinst", []>;
2185 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt),
2186 (ins), "vmrs", "\t$Rt, fpinst2", []>;
2187 }
21842188 }
21852189
21862190 //===----------------------------------------------------------------------===//
22042208 let Inst{4} = 1;
22052209 }
22062210
2207 let Defs = [FPSCR] in {
2208 // Application level GPR -> FPSCR
2209 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
2210 "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
2211 // System level GPR -> FPEXC
2212 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
2213 "vmsr", "\tfpexc, $src", []>;
2214 // System level GPR -> FPSID
2215 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
2216 "vmsr", "\tfpsid, $src", []>;
2217
2218 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
2211 let DecoderMethod = "DecodeForVMRSandVMSR" in {
2212 let Defs = [FPSCR] in {
2213 // Application level GPR -> FPSCR
2214 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$src),
2215 "vmsr", "\tfpscr, $src",
2216 [(int_arm_set_fpscr GPRnopc:$src)]>;
2217 let Predicates = [HasV8, HasVFP2] in {
2218 // System level GPR -> FPEXC
2219 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$src),
2220 "vmsr", "\tfpexc, $src", []>;
2221 // System level GPR -> FPSID
2222 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$src),
2223 "vmsr", "\tfpsid, $src", []>;
2224 }
2225 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$src),
22192226 "vmsr", "\tfpinst, $src", []>;
2220 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
2221 "vmsr", "\tfpinst2, $src", []>;
2227 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$src),
2228 "vmsr", "\tfpinst2, $src", []>;
2229 }
22222230 }
22232231
22242232 //===----------------------------------------------------------------------===//
87448744 Inst.getOperand(1).getReg() == ARM::SP))
87458745 return Match_RequiresV8;
87468746 }
8747
8748 // Use of SP for VMRS/VMSR is only allowed in ARM mode.
8749 if ((Inst.getOpcode() == ARM::VMRS || Inst.getOpcode() == ARM::VMSR) &&
8750 Inst.getOperand(0).getReg() == ARM::SP && (isThumb() && !hasV8Ops()))
8751 return Match_InvalidOperand;
87478752
87488753 for (unsigned I = 0; I < MCID.NumOperands; ++I)
87498754 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
397397 uint64_t Address, const void *Decoder);
398398 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
399399 uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
401 uint64_t Address, const void *Decoder);
400402
401403 #include "ARMGenDisassemblerTables.inc"
402404
52695271
52705272 return S;
52715273 }
5274
5275 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5276 uint64_t Address,
5277 const void *Decoder) {
5278 const FeatureBitset &featureBits =
5279 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5280 DecodeStatus S = MCDisassembler::Success;
5281
5282 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5283
5284 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5285 if (Rt == 13 || Rt == 15)
5286 S = MCDisassembler::SoftFail;
5287 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5288 } else
5289 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5290
5291 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5292 Inst.addOperand(MCOperand::createReg(0));
5293
5294 return S;
5295 }
1515
1616 .type fp,%function
1717 fp:
18 vmrs r0, mvfr2
19 @ CHECK-V7: error: instruction requires: FPARMv8
2018
2119 vselgt.f32 s0, s0, s0
2220 @ CHECK-V7: error: instruction requires: FPARMv8
151149
152150 .type nofp,%function
153151 nofp:
154 vmrs r0, mvfr2
155 @ CHECK: error: instruction requires: FPARMv8
156152
157153 vselgt.f32 s0, s0, s0
158154 @ CHECK: error: instruction requires: FPARMv8
131131 vmrs APSR_nzcv, fpscr
132132 vmrs apsr_nzcv, fpscr
133133 fmstat
134 vmrs r2, fpsid
135 vmrs r3, FPSID
136 vmrs r4, mvfr0
137 vmrs r5, MVFR1
138134
139135 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
140136 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
141137 @ CHECK: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
142 @ CHECK: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
143 @ CHECK: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
144 @ CHECK: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
145 @ CHECK: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
146138
147139 @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
148140 vnegne.f64 d16, d16
164156
165157 @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
166158 vmrs r0, fpscr
167 @ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]
168 vmrs r0, fpexc
169 @ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee]
170 vmrs r0, fpsid
171159 @ CHECK: vmrs r1, fpinst @ encoding: [0x10,0x1a,0xf9,0xee]
172160 vmrs r1, fpinst
173161 @ CHECK: vmrs r8, fpinst2 @ encoding: [0x10,0x8a,0xfa,0xee]
175163
176164 @ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
177165 vmsr fpscr, r0
178 @ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
179 vmsr fpexc, r0
180 @ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
181 vmsr fpsid, r0
182166 @ CHECK: vmsr fpinst, r3 @ encoding: [0x10,0x3a,0xe9,0xee]
183167 vmsr fpinst, r3
184168 @ CHECK: vmsr fpinst2, r4 @ encoding: [0x10,0x4a,0xea,0xee]
0 // RUN: not llvm-mc -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
1 // RUN: | FileCheck --check-prefix=CHECK-V7A-ARM %s
2 // RUN: FileCheck --check-prefix=ERROR-V7A-ARM < %t %s
3 // RUN: not llvm-mc -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
4 // RUN: | FileCheck --check-prefix=CHECK-V7A-THUMB %s
5 // RUN: FileCheck --check-prefix=ERROR-V7A-THUMB < %t %s
6 // RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
7 // RUN: | FileCheck --check-prefix=CHECK-V7M %s
8 // RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
9 // RUN: not llvm-mc -triple=armv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
10 // RUN: | FileCheck --check-prefix=CHECK-V8A-ARM %s
11 // RUN: FileCheck --check-prefix=ERROR-V8A-ARM < %t %s
12 // RUN: not llvm-mc -triple=thumbv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
13 // RUN: | FileCheck --check-prefix=CHECK-V8A-THUMB %s
14 // RUN: FileCheck --check-prefix=ERROR-V8A-THUMB < %t %s
15 // RUN: not llvm-mc -triple=thumbv8m.main-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
16 // RUN: | FileCheck --check-prefix=CHECK-V8M %s
17 // RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
18 // RUN: not llvm-mc -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
19 // RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
20
21 vmrs APSR_nzcv, fpscr
22 vmrs apsr_nzcv, fpscr
23 fmstat
24 vmrs r10, fpscr
25 vmrs r2, fpsid
26 vmrs r3, FPSID
27 vmrs r4, mvfr0
28 vmrs r5, MVFR1
29 vmrs r6, mvfr2
30 vmrs sp, fpscr
31 vmrs pc, fpscr
32
33 // CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
34 // CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
35 // CHECK-V7A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
36 // CHECK-V7A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
37 // ERROR-V7A-ARM: instruction requires: armv8
38 // ERROR-V7A-ARM: instruction requires: armv8
39 // ERROR-V7A-ARM: instruction requires: armv8
40 // ERROR-V7A-ARM: instruction requires: armv8
41 // ERROR-V7A-ARM: instruction requires: armv8
42 // CHECK-V7A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
43 // ERROR-V7A-ARM: invalid operand for instruction
44
45 // CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
46 // CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
47 // CHECK-V7A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
48 // CHECK-V7A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
49 // ERROR-V7A-THUMB: instruction requires: armv8
50 // ERROR-V7A-THUMB: instruction requires: armv8
51 // ERROR-V7A-THUMB: instruction requires: armv8
52 // ERROR-V7A-THUMB: instruction requires: armv8
53 // ERROR-V7A-THUMB: instruction requires: armv8
54 // ERROR-V7A-THUMB: invalid operand for instruction
55 // ERROR-V7A-THUMB: invalid operand for instruction
56
57 // CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
58 // CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
59 // CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
60 // CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
61 // ERROR-V7M: instruction requires: armv8
62 // ERROR-V7M: instruction requires: armv8
63 // ERROR-V7M: instruction requires: armv8
64 // ERROR-V7M: instruction requires: armv8
65 // ERROR-V7M: instruction requires: armv8
66 // ERROR-V7M: invalid operand for instruction
67 // ERROR-V7M: invalid operand for instruction
68
69 // CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
70 // CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
71 // CHECK-V8A-ARM: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
72 // CHECK-V8A-ARM: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
73 // CHECK-V8A-ARM: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
74 // CHECK-V8A-ARM: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
75 // CHECK-V8A-ARM: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
76 // CHECK-V8A-ARM: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
77 // CHECK-V8A-ARM: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
78 // CHECK-V8A-ARM: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
79 // ERROR-V8A-ARM: invalid operand for instruction
80
81 // CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
82 // CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
83 // CHECK-V8A-THUMB: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
84 // CHECK-V8A-THUMB: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
85 // CHECK-V8A-THUMB: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
86 // CHECK-V8A-THUMB: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
87 // CHECK-V8A-THUMB: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
88 // CHECK-V8A-THUMB: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
89 // CHECK-V8A-THUMB: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
90 // CHECK-V8A-THUMB: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
91 // ERROR-V8A-THUMB: invalid operand for instruction
92
93 // CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
94 // CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
95 // CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
96 // CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
97 // ERROR-V8M: instruction requires: armv8
98 // ERROR-V8M: instruction requires: armv8
99 // ERROR-V8M: instruction requires: armv8
100 // ERROR-V8M: instruction requires: armv8
101 // ERROR-V8M: instruction requires: armv8
102 // ERROR-V8M: invalid operand for instruction
103 // ERROR-V8M: invalid operand for instruction
104
105 // ERROR-NOVFP: instruction requires: VFP2
106 // ERROR-NOVFP: instruction requires: VFP2
107 // ERROR-NOVFP: instruction requires: VFP2
108 // ERROR-NOVFP: instruction requires: VFP2
109 // ERROR-NOVFP: instruction requires: armv8
110 // ERROR-NOVFP: instruction requires: armv8
111 // ERROR-NOVFP: instruction requires: armv8
112 // ERROR-NOVFP: instruction requires: armv8
113 // ERROR-NOVFP: instruction requires: armv8
114 // ERROR-NOVFP: instruction requires: VFP2
115 // ERROR-NOVFP: invalid operand for instruction
116
117 vmsr fpscr, APSR_nzcv
118 vmsr fpscr, r0
119 vmsr fpexc, r1
120 vmsr fpsid, r2
121 vmsr fpscr, r10
122 vmsr fpscr, sp
123 vmsr fpscr, pc
124
125 // ERROR-V7A-ARM: invalid operand for instruction
126 // CHECK-V7A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
127 // ERROR-V7A-ARM: instruction requires: armv8
128 // ERROR-V7A-ARM: instruction requires: armv8
129 // CHECK-V7A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
130 // CHECK-V7A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
131 // ERROR-V7A-ARM: invalid operand for instruction
132
133 // ERROR-V7A-THUMB: invalid operand for instruction
134 // CHECK-V7A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
135 // ERROR-V7A-THUMB: instruction requires: armv8
136 // ERROR-V7A-THUMB: instruction requires: armv8
137 // CHECK-V7A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
138 // ERROR-V7A-THUMB: invalid operand for instruction
139 // ERROR-V7A-THUMB: invalid operand for instruction
140
141 // ERROR-V7M: invalid operand for instruction
142 // CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
143 // ERROR-V7M: instruction requires: armv8
144 // ERROR-V7M: instruction requires: armv8
145 // CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
146 // ERROR-V7M: invalid operand for instruction
147 // ERROR-V7M: invalid operand for instruction
148
149 // ERROR-V8A-ARM: invalid operand for instruction
150 // CHECK-V8A-ARM: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
151 // CHECK-V8A-ARM: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
152 // CHECK-V8A-ARM: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
153 // CHECK-V8A-ARM: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
154 // CHECK-V8A-ARM: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
155 // ERROR-V8A-ARM: invalid operand for instruction
156
157 // ERROR-V8A-THUMB: invalid operand for instruction
158 // CHECK-V8A-THUMB: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
159 // CHECK-V8A-THUMB: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
160 // CHECK-V8A-THUMB: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
161 // CHECK-V8A-THUMB: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
162 // CHECK-V8A-THUMB: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
163 // ERROR-V8A-THUMB: invalid operand for instruction
164
165 // ERROR-V8M: invalid operand for instruction
166 // CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
167 // ERROR-V8M: instruction requires: armv8
168 // ERROR-V8M: instruction requires: armv8
169 // CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
170 // ERROR-V8M: invalid operand for instruction
171 // ERROR-V8M: invalid operand for instruction
172
173 // ERROR-NOVFP: invalid operand for instruction
174 // ERROR-NOVFP: instruction requires: VFP2
175 // ERROR-NOVFP: instruction requires: armv8
176 // ERROR-NOVFP: instruction requires: armv8
177 // ERROR-NOVFP: instruction requires: VFP2
178 // ERROR-NOVFP: instruction requires: VFP2
179 // ERROR-NOVFP: invalid operand for instruction
0 # RUN: not llvm-mc -disassemble -triple=armv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK-V7A %s
2 # RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
3 # RUN: llvm-mc -disassemble -triple=armv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
4 # RUN: | FileCheck --check-prefix=CHECK-V8A %s
5 # RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
6
7 [0x10,0xfa,0xf1,0xee]
8 [0x10,0xfa,0xf1,0xee]
9 [0x10,0xfa,0xf1,0xee]
10 [0x10,0xaa,0xf1,0xee]
11 [0x10,0x2a,0xf0,0xee]
12 [0x10,0x3a,0xf0,0xee]
13 [0x10,0x4a,0xf7,0xee]
14 [0x10,0x5a,0xf6,0xee]
15 [0x10,0x6a,0xf5,0xee]
16 [0x10,0xda,0xf1,0xee]
17
18 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
19 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
20 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
21 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
22 # ERROR-V7A: invalid instruction encoding
23 # ERROR-V7A: invalid instruction encoding
24 # ERROR-V7A: invalid instruction encoding
25 # ERROR-V7A: invalid instruction encoding
26 # ERROR-V7A: invalid instruction encoding
27 # CHECK-V7A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
28
29 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
30 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
31 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
32 # CHECK-V8A: vmrs r10, fpscr @ encoding: [0x10,0xaa,0xf1,0xee]
33 # CHECK-V8A: vmrs r2, fpsid @ encoding: [0x10,0x2a,0xf0,0xee]
34 # CHECK-V8A: vmrs r3, fpsid @ encoding: [0x10,0x3a,0xf0,0xee]
35 # CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0x10,0x4a,0xf7,0xee]
36 # CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0x10,0x5a,0xf6,0xee]
37 # CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0x10,0x6a,0xf5,0xee]
38 # CHECK-V8A: vmrs sp, fpscr @ encoding: [0x10,0xda,0xf1,0xee]
39
40 [0x10,0xfa,0xe1,0xee]
41 [0x10,0x0a,0xe1,0xee]
42 [0x10,0x1a,0xe8,0xee]
43 [0x10,0x2a,0xe0,0xee]
44 [0x10,0xaa,0xe1,0xee]
45 [0x10,0xda,0xe1,0xee]
46
47 # ERROR-V7A: potentially undefined instruction encoding
48 # CHECK-V7A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
49 # ERROR-V7A: invalid instruction encoding
50 # ERROR-V7A: invalid instruction encoding
51 # CHECK-V7A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
52 # CHECK-V7A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
53
54 # ERROR-V8A: potentially undefined instruction encoding
55 # CHECK-V8A: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
56 # CHECK-V8A: vmsr fpexc, r1 @ encoding: [0x10,0x1a,0xe8,0xee]
57 # CHECK-V8A: vmsr fpsid, r2 @ encoding: [0x10,0x2a,0xe0,0xee]
58 # CHECK-V8A: vmsr fpscr, r10 @ encoding: [0x10,0xaa,0xe1,0xee]
59 # CHECK-V8A: vmsr fpscr, sp @ encoding: [0x10,0xda,0xe1,0xee]
117117
118118 0x10 0x0a 0xf1 0xee
119119 # CHECK: vmrs r0, fpscr
120 0x10 0x0a 0xf8 0xee
121 # CHECK: vmrs r0, fpexc
122 0x10 0x0a 0xf0 0xee
123 # CHECK: vmrs r0, fpsid
124120 0x10 0x1a 0xf9 0xee
125121 # CHECK: vmrs r1, fpinst
126122 0x10 0x8a 0xfa 0xee
128124
129125 0x10 0x0a 0xe1 0xee
130126 # CHECK: vmsr fpscr, r0
131 0x10 0x0a 0xe8 0xee
132 # CHECK: vmsr fpexc, r0
133 0x10 0x0a 0xe0 0xee
134 # CHECK: vmsr fpsid, r0
135127 0x10 0x3a 0xe9 0xee
136128 # CHECK: vmsr fpinst, r3
137129 0x10 0x4a 0xea 0xee
0 # RUN: not llvm-mc -disassemble -triple=thumbv7a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK-V7A %s
2 # RUN: FileCheck --check-prefix=ERROR-V7A < %t %s
3 # RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
4 # RUN: | FileCheck --check-prefix=CHECK-V7M %s
5 # RUN: FileCheck --check-prefix=ERROR-V7M < %t %s
6 # RUN: llvm-mc -disassemble -triple=thumbv8a-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
7 # RUN: | FileCheck --check-prefix=CHECK-V8A %s
8 # RUN: FileCheck --check-prefix=ERROR-V8A < %t %s
9 # RUN: not llvm-mc -disassemble -triple=thumbv8m.main-arm-none-eabi -mattr=+vfp2 -show-encoding < %s 2>%t \
10 # RUN: | FileCheck --check-prefix=CHECK-V8M %s
11 # RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
12 # RUN: not llvm-mc -disassemble -triple=thumbv7m-arm-none-eabi -show-encoding < %s 2>%t
13 # RUN: FileCheck --check-prefix=ERROR-NOVFP < %t %s
14
15 [0xf1,0xee,0x10,0xfa]
16 [0xf1,0xee,0x10,0xfa]
17 [0xf1,0xee,0x10,0xfa]
18 [0xf1,0xee,0x10,0xaa]
19 [0xf0,0xee,0x10,0x2a]
20 [0xf0,0xee,0x10,0x3a]
21 [0xf7,0xee,0x10,0x4a]
22 [0xf6,0xee,0x10,0x5a]
23 [0xf5,0xee,0x10,0x6a]
24 [0xf1,0xee,0x10,0xda]
25
26 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
27 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
28 # CHECK-V7A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
29 # CHECK-V7A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
30 # ERROR-V7A: invalid instruction encoding
31 # ERROR-V7A: invalid instruction encoding
32 # ERROR-V7A: invalid instruction encoding
33 # ERROR-V7A: invalid instruction encoding
34 # ERROR-V7A: invalid instruction encoding
35 # ERROR-V7A: potentially undefined instruction encoding
36
37 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
38 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
39 # CHECK-V7M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
40 # CHECK-V7M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
41 # ERROR-V7M: invalid instruction encoding
42 # ERROR-V7M: invalid instruction encoding
43 # ERROR-V7M: invalid instruction encoding
44 # ERROR-V7M: invalid instruction encoding
45 # ERROR-V7M: invalid instruction encoding
46 # ERROR-V7M: potentially undefined instruction encoding
47
48 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
49 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
50 # CHECK-V8A: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
51 # CHECK-V8A: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
52 # CHECK-V8A: vmrs r2, fpsid @ encoding: [0xf0,0xee,0x10,0x2a]
53 # CHECK-V8A: vmrs r3, fpsid @ encoding: [0xf0,0xee,0x10,0x3a]
54 # CHECK-V8A: vmrs r4, mvfr0 @ encoding: [0xf7,0xee,0x10,0x4a]
55 # CHECK-V8A: vmrs r5, mvfr1 @ encoding: [0xf6,0xee,0x10,0x5a]
56 # CHECK-V8A: vmrs r6, mvfr2 @ encoding: [0xf5,0xee,0x10,0x6a]
57 # CHECK-V8A: vmrs sp, fpscr @ encoding: [0xf1,0xee,0x10,0xda]
58
59 # CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
60 # CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
61 # CHECK-V8M: vmrs APSR_nzcv, fpscr @ encoding: [0xf1,0xee,0x10,0xfa]
62 # CHECK-V8M: vmrs r10, fpscr @ encoding: [0xf1,0xee,0x10,0xaa]
63 # ERROR-V8M: invalid instruction encoding
64 # ERROR-V8M: invalid instruction encoding
65 # ERROR-V8M: invalid instruction encoding
66 # ERROR-V8M: invalid instruction encoding
67 # ERROR-V8M: invalid instruction encoding
68 # ERROR-V8M: potentially undefined instruction encoding
69
70 # ERROR-NOVFP: invalid instruction encoding
71 # ERROR-NOVFP: invalid instruction encoding
72 # ERROR-NOVFP: invalid instruction encoding
73 # ERROR-NOVFP: invalid instruction encoding
74 # ERROR-NOVFP: invalid instruction encoding
75 # ERROR-NOVFP: invalid instruction encoding
76 # ERROR-NOVFP: invalid instruction encoding
77 # ERROR-NOVFP: invalid instruction encoding
78 # ERROR-NOVFP: invalid instruction encoding
79 # ERROR-NOVFP: invalid instruction encoding
80
81 [0xe1,0xee,0x10,0xfa]
82 [0xe1,0xee,0x10,0x0a]
83 [0xe8,0xee,0x10,0x1a]
84 [0xe0,0xee,0x10,0x2a]
85 [0xe1,0xee,0x10,0xaa]
86 [0xe1,0xee,0x10,0xda]
87
88 # ERROR-V7A: potentially undefined instruction encoding
89 # CHECK-V7A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
90 # ERROR-V7A: invalid instruction encoding
91 # ERROR-V7A: invalid instruction encoding
92 # CHECK-V7A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
93 # ERROR-V7A: potentially undefined instruction encoding
94
95 # ERROR-V7M: potentially undefined instruction encoding
96 # CHECK-V7M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
97 # ERROR-V7M: invalid instruction encoding
98 # ERROR-V7M: invalid instruction encoding
99 # CHECK-V7M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
100 # ERROR-V7M: potentially undefined instruction encoding
101
102 # ERROR-V8A: potentially undefined instruction encoding
103 # CHECK-V8A: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
104 # CHECK-V8A: vmsr fpexc, r1 @ encoding: [0xe8,0xee,0x10,0x1a]
105 # CHECK-V8A: vmsr fpsid, r2 @ encoding: [0xe0,0xee,0x10,0x2a]
106 # CHECK-V8A: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
107 # CHECK-V8A: vmsr fpscr, sp @ encoding: [0xe1,0xee,0x10,0xda]
108
109 # ERROR-V8M: potentially undefined instruction encoding
110 # CHECK-V8M: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
111 # ERROR-V8M: invalid instruction encoding
112 # ERROR-V8M: invalid instruction encoding
113 # CHECK-V8M: vmsr fpscr, r10 @ encoding: [0xe1,0xee,0x10,0xaa]
114 # ERROR-V8M: potentially undefined instruction encoding
115
116 # ERROR-NOVFP: invalid instruction encoding
117 # ERROR-NOVFP: invalid instruction encoding
118 # ERROR-NOVFP: invalid instruction encoding
119 # ERROR-NOVFP: invalid instruction encoding
120 # ERROR-NOVFP: invalid instruction encoding
121 # ERROR-NOVFP: invalid instruction encoding
122