llvm.org GIT mirror llvm / 10d664f
Replace some assert(0)'s with llvm_unreachable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211141 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
19 changed file(s) with 28 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
9696 switch (Op.getEncoding()) {
9797 case BitCodeAbbrevOp::Array:
9898 case BitCodeAbbrevOp::Blob:
99 assert(0 && "Should not reach here");
99 llvm_unreachable("Should not reach here");
100100 case BitCodeAbbrevOp::Fixed:
101101 Vals.push_back(Read((unsigned)Op.getEncodingData()));
102102 break;
116116 switch (Op.getEncoding()) {
117117 case BitCodeAbbrevOp::Array:
118118 case BitCodeAbbrevOp::Blob:
119 assert(0 && "Should not reach here");
119 llvm_unreachable("Should not reach here");
120120 case BitCodeAbbrevOp::Fixed:
121121 (void)Read((unsigned)Op.getEncodingData());
122122 break;
11401140 // Perform the merge for standard behavior types.
11411141 switch (SrcBehaviorValue) {
11421142 case Module::Require:
1143 case Module::Override: assert(0 && "not possible"); break;
1143 case Module::Override: llvm_unreachable("not possible");
11441144 case Module::Error: {
11451145 // Emit an error if the values differ.
11461146 if (SrcOp->getOperand(2) != DstOp->getOperand(2)) {
210210 const MachineOperand &MO = MI->getOperand(OpNum);
211211 switch (MO.getType()) {
212212 default:
213 assert(0 && "");
213 llvm_unreachable("");
214214 case MachineOperand::MO_Register: {
215215 unsigned Reg = MO.getReg();
216216 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
290290 static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
291291 switch (MI->getOpcode()) {
292292 default:
293 assert(0 && "unexpected opcode!");
293 llvm_unreachable("unexpected opcode!");
294294 case AArch64::TBZW:
295295 case AArch64::TBNZW:
296296 case AArch64::TBZX:
308308 static unsigned getOppositeConditionOpcode(unsigned Opc) {
309309 switch (Opc) {
310310 default:
311 assert(0 && "unexpected opcode!");
311 llvm_unreachable("unexpected opcode!");
312312 case AArch64::TBNZW: return AArch64::TBZW;
313313 case AArch64::TBNZX: return AArch64::TBZX;
314314 case AArch64::TBZW: return AArch64::TBNZW;
324324 static unsigned getBranchDisplacementBits(unsigned Opc) {
325325 switch (Opc) {
326326 default:
327 assert(0 && "unexpected opcode!");
327 llvm_unreachable("unexpected opcode!");
328328 case AArch64::TBNZW:
329329 case AArch64::TBZW:
330330 case AArch64::TBNZX:
21072107 .getVectorElementType()
21082108 .getSizeInBits()) {
21092109 default:
2110 assert(0 && "Unexpected vector element type!");
2110 llvm_unreachable("Unexpected vector element type!");
21112111 case 64:
21122112 SubReg = AArch64::dsub;
21132113 break;
12721272 bool ExtraOp = false;
12731273 switch (Op.getOpcode()) {
12741274 default:
1275 assert(0 && "Invalid code");
1275 llvm_unreachable("Invalid code");
12761276 case ISD::ADDC:
12771277 Opc = AArch64ISD::ADDS;
12781278 break;
66736673 else if (Vec.getValueType() == MVT::v2i64)
66746674 VecResTy = MVT::v2f64;
66756675 else
6676 assert(0 && "unexpected vector type!");
6676 llvm_unreachable("unexpected vector type!");
66776677
66786678 SDValue Convert =
66796679 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
18401840 *OutUnscaledOp = 0;
18411841 switch (MI.getOpcode()) {
18421842 default:
1843 assert(0 && "unhandled opcode in rewriteAArch64FrameIndex");
1843 llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex");
18441844 // Vector spills/fills can't take an immediate offset.
18451845 case AArch64::LD1Twov2d:
18461846 case AArch64::LD1Threev2d:
5050 AArch64II::MO_PAGEOFF)
5151 RefKind = MCSymbolRefExpr::VK_GOTPAGEOFF;
5252 else
53 assert(0 && "Unexpected target flags with MO_GOT on GV operand");
53 llvm_unreachable("Unexpected target flags with MO_GOT on GV operand");
5454 } else if ((MO.getTargetFlags() & AArch64II::MO_TLS) != 0) {
5555 if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
5656 RefKind = MCSymbolRefExpr::VK_TLVPPAGE;
153153 MCOperand &MCOp) const {
154154 switch (MO.getType()) {
155155 default:
156 assert(0 && "unknown operand type");
156 llvm_unreachable("unknown operand type");
157157 case MachineOperand::MO_Register:
158158 // Ignore all implicit register operands.
159159 if (MO.isImplicit())
917917 else
918918 O << getRegisterName(Reg);
919919 } else
920 assert(0 && "unknown operand kind in printPostIncOperand64");
920 llvm_unreachable("unknown operand kind in printPostIncOperand64");
921921 }
922922
923923 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
11081108 while (Stride--) {
11091109 switch (Reg) {
11101110 default:
1111 assert(0 && "Vector register expected!");
1111 llvm_unreachable("Vector register expected!");
11121112 case AArch64::Q0: Reg = AArch64::Q1; break;
11131113 case AArch64::Q1: Reg = AArch64::Q2; break;
11141114 case AArch64::Q2: Reg = AArch64::Q3; break;
8585 static unsigned getFixupKindNumBytes(unsigned Kind) {
8686 switch (Kind) {
8787 default:
88 assert(0 && "Unknown fixup kind!");
88 llvm_unreachable("Unknown fixup kind!");
8989
9090 case AArch64::fixup_aarch64_tlsdesc_call:
9191 return 0;
7474 Log2Size = llvm::Log2_32(4);
7575 switch (Sym->getKind()) {
7676 default:
77 assert(0 && "Unexpected symbol reference variant kind!");
77 llvm_unreachable("Unexpected symbol reference variant kind!");
7878 case MCSymbolRefExpr::VK_PAGEOFF:
7979 RelocType = unsigned(MachO::ARM64_RELOC_PAGEOFF12);
8080 return true;
492492 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
493493 def rot_imm_XFORM: SDNodeXForm
494494 switch (N->getZExtValue()){
495 default: assert(0);
495 default: llvm_unreachable(nullptr);
496496 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
497497 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
498498 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
219219
220220 void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx) {
221221 if (!CPEClones.insert(std::make_pair(CPCloneIdx, CPIdx)).second)
222 assert(0 && "Duplicate entries!");
222 llvm_unreachable("Duplicate entries!");
223223 }
224224
225225 unsigned getOriginalCPIdx(unsigned CloneIdx) const {
14371437 O << "linear";
14381438 break;
14391439 case 2:
1440 assert(0 && "Anisotropic filtering is not supported");
1440 llvm_unreachable("Anisotropic filtering is not supported");
14411441 default:
14421442 O << "nearest";
14431443 break;
15611561 }
15621562 break;
15631563 default:
1564 assert(0 && "type not supported yet");
1564 llvm_unreachable("type not supported yet");
15651565 }
15661566
15671567 }
16811681 O << "]";
16821682 break;
16831683 default:
1684 assert(0 && "type not supported yet");
1684 llvm_unreachable("type not supported yet");
16851685 }
16861686 return;
16871687 }
329329 unsigned Reg = Op.getReg();
330330 unsigned regIdx = 0;
331331 switch (Op.Reg.Kind) {
332 default: assert(0 && "Unexpected register kind!");
332 default: llvm_unreachable("Unexpected register kind!");
333333 case rk_FloatReg:
334334 regIdx = Reg - Sparc::F0;
335335 if (regIdx % 4 || regIdx > 31)
200200 }
201201 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
202202 // FIXME.
203 assert(0 && "relaxInstruction() unimplemented");
203 llvm_unreachable("relaxInstruction() unimplemented");
204204 }
205205
206206 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
123123
124124 Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
125125 switch (Kind) {
126 default: assert(0 && "Unhandled SparcMCExpr::VariantKind");
126 default: llvm_unreachable("Unhandled SparcMCExpr::VariantKind");
127127 case VK_Sparc_LO: return Sparc::fixup_sparc_lo10;
128128 case VK_Sparc_HI: return Sparc::fixup_sparc_hi22;
129129 case VK_Sparc_H44: return Sparc::fixup_sparc_h44;
212212
213213
214214 void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
215 assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");
215 llvm_unreachable("FIXME: Implement SparcJITInfo::"
216 "replaceMachineCodeForFunction");
216217 }
217218
218219
379379 case 3: TypeSig.push_back(IIT_STRUCT3); break;
380380 case 4: TypeSig.push_back(IIT_STRUCT4); break;
381381 case 5: TypeSig.push_back(IIT_STRUCT5); break;
382 default: assert(0 && "Unhandled case in struct");
382 default: llvm_unreachable("Unhandled case in struct");
383383 }
384384
385385 for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i)