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llvm-mc/AsmParser: Match hard coded registers (e.g. 'shldl %cl, %eax, %eax') We now match all of 403.gcc (as emitted by clang). :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78750 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 10 years ago
2 changed file(s) with 106 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
5151 // FIXME: Check that this matches the correct instruction.
5252 // RUN: grep {MCInst(opcode=.*, operands=.reg:80.)} %t
5353 call *%rax
54
55 // FIXME: Check that this matches the correct instruction.
56 // RUN: grep {MCInst(opcode=.*, operands=.reg:21, reg:0, reg:19.)} %t
57 shldl %cl, %eax, %ebx
531531
532532 /// BuildRegisterClasses - Build the ClassInfo* instances for register
533533 /// classes.
534 void BuildRegisterClasses(CodeGenTarget &Target);
534 void BuildRegisterClasses(CodeGenTarget &Target,
535 std::set &SingletonRegisterNames);
535536
536537 /// BuildOperandClasses - Build the ClassInfo* instances for user defined
537538 /// operand classes.
564565 continue;
565566 }
566567
568 if (!Op.OperandInfo) {
569 errs() << "(singleton register)\n";
570 continue;
571 }
572
567573 const CodeGenInstruction::OperandInfo &OI = *Op.OperandInfo;
568574 errs() << OI.Name << " " << OI.Rec->getName()
569575 << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n";
589595 }
590596
591597 return Res;
598 }
599
600 /// getRegisterRecord - Get the register record for \arg name, or 0.
601 static Record *getRegisterRecord(CodeGenTarget &Target, const StringRef &Name) {
602 for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
603 const CodeGenRegister &Reg = Target.getRegisters()[i];
604 if (Name == Reg.TheDef->getValueAsString("AsmName"))
605 return Reg.TheDef;
606 }
607
608 return 0;
592609 }
593610
594611 ClassInfo *AsmMatcherInfo::getTokenClass(const StringRef &Token) {
634651 return CI;
635652 }
636653
637 void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target) {
654 void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
655 std::set
656 &SingletonRegisterNames) {
638657 std::vector RegisterClasses;
639658 std::vector Registers;
640659
649668 ie = RegisterClasses.end(); it != ie; ++it)
650669 RegisterSets.insert(std::set(it->Elements.begin(),
651670 it->Elements.end()));
652
671
672 // Add any required singleton sets.
673 for (std::set::iterator it = SingletonRegisterNames.begin(),
674 ie = SingletonRegisterNames.end(); it != ie; ++it)
675 if (Record *Rec = getRegisterRecord(Target, *it))
676 RegisterSets.insert(std::set(&Rec, &Rec + 1));
677
653678 // Introduce derived sets where necessary (when a register does not determine
654679 // a unique register set class), and build the mapping of registers to the set
655680 // they should classify to.
731756 for (std::map >::iterator it = RegisterMap.begin(),
732757 ie = RegisterMap.end(); it != ie; ++it)
733758 this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
759
760 // Name the register classes which correspond to singleton registers.
761 for (std::set::iterator it = SingletonRegisterNames.begin(),
762 ie = SingletonRegisterNames.end(); it != ie; ++it) {
763 if (Record *Rec = getRegisterRecord(Target, *it)) {
764 ClassInfo *CI = this->RegisterClasses[Rec];
765 assert(CI && "Missing singleton register class info!");
766
767 if (CI->ValueName.empty()) {
768 CI->ClassName = Rec->getName();
769 CI->Name = "MCK_" + Rec->getName();
770 CI->ValueName = Rec->getName();
771 } else
772 CI->ValueName = CI->ValueName + "," + Rec->getName();
773 }
774 }
734775 }
735776
736777 void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
789830 }
790831
791832 void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
792 // Build info for the register classes.
793 BuildRegisterClasses(Target);
794
795 // Build info for the user defined assembly operand classes.
796 BuildOperandClasses(Target);
797
798 // Build the instruction information.
833 // Parse the instructions; we need to do this first so that we can gather the
834 // singleton register classes.
835 std::set SingletonRegisterNames;
799836 for (std::map::const_iterator
800837 it = Target.getInstructions().begin(),
801838 ie = Target.getInstructions().end();
824861 if (!IsAssemblerInstruction(it->first, CGI, II->Tokens))
825862 continue;
826863
864 // Collect singleton registers, if used.
865 if (!RegisterPrefix.empty()) {
866 for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
867 if (II->Tokens[i].startswith(RegisterPrefix)) {
868 StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
869 Record *Rec = getRegisterRecord(Target, RegName);
870
871 if (!Rec) {
872 std::string Err = "unable to find register for '" + RegName.str() +
873 "' (which matches register prefix)";
874 throw TGError(CGI.TheDef->getLoc(), Err);
875 }
876
877 SingletonRegisterNames.insert(RegName);
878 }
879 }
880 }
881
882 Instructions.push_back(II.take());
883 }
884
885 // Build info for the register classes.
886 BuildRegisterClasses(Target, SingletonRegisterNames);
887
888 // Build info for the user defined assembly operand classes.
889 BuildOperandClasses(Target);
890
891 // Build the instruction information.
892 for (std::vector::iterator it = Instructions.begin(),
893 ie = Instructions.end(); it != ie; ++it) {
894 InstructionInfo *II = *it;
895
827896 for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
828897 StringRef Token = II->Tokens[i];
898
899 // Check for singleton registers.
900 if (!RegisterPrefix.empty() && Token.startswith(RegisterPrefix)) {
901 StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
902 InstructionInfo::Operand Op;
903 Op.Class = RegisterClasses[getRegisterRecord(Target, RegName)];
904 Op.OperandInfo = 0;
905 assert(Op.Class && Op.Class->Registers.size() == 1 &&
906 "Unexpected class for singleton register");
907 II->Operands.push_back(Op);
908 continue;
909 }
829910
830911 // Check for simple tokens.
831912 if (Token[0] != '$') {
846927 // Map this token to an operand. FIXME: Move elsewhere.
847928 unsigned Idx;
848929 try {
849 Idx = CGI.getOperandNamed(OperandName);
930 Idx = II->Instr->getOperandNamed(OperandName);
850931 } catch(...) {
851 errs() << "error: unable to find operand: '" << OperandName << "'!\n";
852 break;
932 throw std::string("error: unable to find operand: '" +
933 OperandName.str() + "'");
853934 }
854935
855 const CodeGenInstruction::OperandInfo &OI = CGI.OperandList[Idx];
936 const CodeGenInstruction::OperandInfo &OI = II->Instr->OperandList[Idx];
856937 InstructionInfo::Operand Op;
857938 Op.Class = getOperandClass(Token, OI);
858939 Op.OperandInfo = &OI;
859940 II->Operands.push_back(Op);
860941 }
861
862 // If we broke out, ignore the instruction.
863 if (II->Operands.size() != II->Tokens.size())
864 continue;
865
866 Instructions.push_back(II.take());
867942 }
868943
869944 // Reorder classes so that classes preceed super classes.
13201395 Record *AsmParser = Target.getAsmParser();
13211396 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName");
13221397
1323 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1324
1325 // Emit the function to match a register name to number.
1326 EmitMatchRegisterName(Target, AsmParser, OS);
1327
13281398 // Compute the information on the instructions to match.
13291399 AsmMatcherInfo Info(AsmParser);
13301400 Info.BuildInfo(Target);
13651435 << " ambiguous instructions!\n";
13661436 });
13671437
1438 // Write the output.
1439
1440 EmitSourceFileHeader("Assembly Matcher Source Fragment", OS);
1441
1442 // Emit the function to match a register name to number.
1443 EmitMatchRegisterName(Target, AsmParser, OS);
1444
13681445 // Generate the unified function to convert operands into an MCInst.
13691446 EmitConvertToMCInst(Target, Info.Instructions, OS);
13701447