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[PEI] Pass the frame index operand number to the eliminateFrameIndex function. Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 6 years ago
25 changed file(s) with 142 addition(s) and 179 deletion(s). Raw diff Collapse all Expand all
766766 /// referenced by the iterator contains an MO_FrameIndex operand which must be
767767 /// eliminated by this method. This method may modify or replace the
768768 /// specified instruction, as long as it keeps the iterator pointing at the
769 /// finished product. SPAdj is the SP adjustment due to call frame setup
770 /// instruction.
769 /// finished product. SPAdj is the SP adjustment due to call frame setup
770 /// instruction. FIOperandNum is the FI operand number.
771771 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
772 int SPAdj, RegScavenger *RS=NULL) const = 0;
772 int SPAdj, unsigned FIOperandNum,
773 RegScavenger *RS = NULL) const = 0;
773774
774775 //===--------------------------------------------------------------------===//
775776 /// Debug information queries.
765765 // If this instruction has a FrameIndex operand, we need to
766766 // use that target machine register info object to eliminate
767767 // it.
768 TRI.eliminateFrameIndex(MI, SPAdj,
768 TRI.eliminateFrameIndex(MI, SPAdj, i,
769769 FrameIndexVirtualScavenging ? NULL : RS);
770770
771771 // Reset the iterator if we were at the beginning of the BB.
315315 return Survivor;
316316 }
317317
318 static unsigned getFrameIndexOperandNum(MachineInstr *MI) {
319 unsigned i = 0;
320 while (!MI->getOperand(i).isFI()) {
321 ++i;
322 assert(i < MI->getNumOperands() &&
323 "Instr doesn't have FrameIndex operand!");
324 }
325 return i;
326 }
327
318328 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
319329 MachineBasicBlock::iterator I,
320330 int SPAdj) {
363373 "Cannot scavenge register without an emergency spill slot!");
364374 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
365375 MachineBasicBlock::iterator II = prior(I);
366 TRI->eliminateFrameIndex(II, SPAdj, this);
376
377 unsigned FIOperandNum = getFrameIndexOperandNum(II);
378 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
367379
368380 // Restore the scavenged register before its use (or first terminator).
369381 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
370382 II = prior(UseMI);
371 TRI->eliminateFrameIndex(II, SPAdj, this);
383
384 FIOperandNum = getFrameIndexOperandNum(II);
385 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
372386 }
373387
374388 ScavengeRestore = prior(UseMI);
716716
717717 void
718718 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
719 int SPAdj, RegScavenger *RS) const {
720 unsigned i = 0;
719 int SPAdj, unsigned FIOperandNum,
720 RegScavenger *RS) const {
721721 MachineInstr &MI = *II;
722722 MachineBasicBlock &MBB = *MI.getParent();
723723 MachineFunction &MF = *MBB.getParent();
726726 ARMFunctionInfo *AFI = MF.getInfo();
727727 assert(!AFI->isThumb1OnlyFunction() &&
728728 "This eliminateFrameIndex does not support Thumb1!");
729
730 while (!MI.getOperand(i).isFI()) {
731 ++i;
732 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
733 }
734
735 int FrameIndex = MI.getOperand(i).getIndex();
729 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
736730 unsigned FrameReg;
737731
738732 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
754748
755749 // Special handling of dbg_value instructions.
756750 if (MI.isDebugValue()) {
757 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
758 MI.getOperand(i+1).ChangeToImmediate(Offset);
751 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
752 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
759753 return;
760754 }
761755
762756 // Modify MI as necessary to handle as much of 'Offset' as possible
763757 bool Done = false;
764758 if (!AFI->isThumbFunction())
765 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
759 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
766760 else {
767761 assert(AFI->isThumb2Function());
768 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
762 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
769763 }
770764 if (Done)
771765 return;
785779 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
786780 if (Offset == 0)
787781 // Must be addrmode4/6.
788 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
782 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
789783 else {
790784 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
791785 if (!AFI->isThumbFunction())
797791 Offset, Pred, PredReg, TII);
798792 }
799793 // Update the original instruction to use the scratch register.
800 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
801 }
802 }
794 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
795 }
796 }
172172 MachineBasicBlock::iterator I) const;
173173
174174 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
175 int SPAdj, RegScavenger *RS = NULL) const;
175 int SPAdj, unsigned FIOperandNum,
176 RegScavenger *RS = NULL) const;
176177 };
177178
178179 } // end namespace llvm
592592
593593 void
594594 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
595 int SPAdj, RegScavenger *RS) const {
595 int SPAdj, unsigned FIOperandNum,
596 RegScavenger *RS) const {
596597 unsigned VReg = 0;
597 unsigned i = 0;
598598 MachineInstr &MI = *II;
599599 MachineBasicBlock &MBB = *MI.getParent();
600600 MachineFunction &MF = *MBB.getParent();
602602 DebugLoc dl = MI.getDebugLoc();
603603 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
604604
605 while (!MI.getOperand(i).isFI()) {
606 ++i;
607 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
608 }
609
610605 unsigned FrameReg = ARM::SP;
611 int FrameIndex = MI.getOperand(i).getIndex();
606 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
612607 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
613608 MF.getFrameInfo()->getStackSize() + SPAdj;
614609
645640
646641 // Special handling of dbg_value instructions.
647642 if (MI.isDebugValue()) {
648 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
649 MI.getOperand(i+1).ChangeToImmediate(Offset);
643 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
644 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
650645 return;
651646 }
652647
653648 // Modify MI as necessary to handle as much of 'Offset' as possible
654649 assert(AFI->isThumbFunction() &&
655650 "This eliminateFrameIndex only supports Thumb1!");
656 if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
651 if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
657652 return;
658653
659654 // If we get here, the immediate doesn't fit into the instruction. We folded
686681 }
687682
688683 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
689 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
684 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
690685 if (UseRR)
691686 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
692687 // register. The offset is already handled in the vreg value.
693 MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
688 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
689 false);
694690 } else if (MI.mayStore()) {
695691 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
696692 bool UseRR = false;
707703 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
708704 *this);
709705 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
710 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
706 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
711707 if (UseRR)
712708 // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
713709 // register. The offset is already handled in the vreg value.
714 MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
710 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
711 false);
715712 } else {
716713 llvm_unreachable("Unexpected opcode!");
717714 }
6161 const TargetRegisterClass *RC,
6262 unsigned Reg) const;
6363 void eliminateFrameIndex(MachineBasicBlock::iterator II,
64 int SPAdj, RegScavenger *RS = NULL) const;
64 int SPAdj, unsigned FIOperandNum,
65 RegScavenger *RS = NULL) const;
6566 };
6667 }
6768
132132 }
133133
134134 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
135 int SPAdj, RegScavenger *RS) const {
136
135 int SPAdj, unsigned FIOperandNum,
136 RegScavenger *RS) const {
137137 //
138138 // Hexagon_TODO: Do we need to enforce this for Hexagon?
139139 assert(SPAdj == 0 && "Unexpected");
140140
141
142 unsigned i = 0;
143141 MachineInstr &MI = *II;
144 while (!MI.getOperand(i).isFI()) {
145 ++i;
146 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
147 }
148
149 int FrameIndex = MI.getOperand(i).getIndex();
142 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
150143
151144 // Addressable stack objects are accessed using neg. offsets from %fp.
152145 MachineFunction &MF = *MI.getParent()->getParent();
166159 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
167160 !TII.isSpillPredRegOp(&MI)) {
168161 // Replace frame index with a stack pointer reference.
169 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
170 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
162 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
163 false, true);
164 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
171165 } else {
172166 // Replace frame index with a frame pointer reference.
173167 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
204198 dstReg).addReg(FrameReg).addImm(Offset);
205199 }
206200
207 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
208 MI.getOperand(i+1).ChangeToImmediate(0);
201 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
202 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
209203 } else if ((MI.getOpcode() == Hexagon::STriw_indexed) ||
210204 (MI.getOpcode() == Hexagon::STriw) ||
211205 (MI.getOpcode() == Hexagon::STrid) ||
232226 TII.get(Hexagon::ADD_ri),
233227 resReg).addReg(FrameReg).addImm(Offset);
234228 }
235 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
236 MI.getOperand(i+1).ChangeToImmediate(0);
229 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
230 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
237231 } else if (TII.isMemOp(&MI)) {
238232 unsigned resReg = HEXAGON_RESERVED_REG_1;
239233 if (!MFI.hasVarSizedObjects() &&
240234 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
241 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false,
242 true);
243 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
235 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(),
236 false, false, true);
237 MI.getOperand(FIOperandNum+1).ChangeToImmediate(FrameSize+Offset);
244238 } else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
245239 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
246240 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
247241 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
248242 TII.get(Hexagon::ADD_rr),
249243 resReg).addReg(FrameReg).addReg(resReg);
250 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
251 MI.getOperand(i+1).ChangeToImmediate(0);
244 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,
245 true);
246 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
252247 } else {
253248 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
254249 TII.get(Hexagon::ADD_ri),
255250 resReg).addReg(FrameReg).addImm(Offset);
256 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
257 MI.getOperand(i+1).ChangeToImmediate(0);
251 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,
252 true);
253 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
258254 }
259255 } else {
260256 unsigned dstReg = MI.getOperand(0).getReg();
264260 TII.get(Hexagon::ADD_rr),
265261 dstReg).addReg(FrameReg).addReg(dstReg);
266262 // Can we delete MI??? r2 = add (r2, #0).
267 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
268 MI.getOperand(i+1).ChangeToImmediate(0);
263 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
264 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
269265 }
270266 } else {
271267 // If the offset is small enough to fit in the immediate field, directly
272268 // encode it.
273 MI.getOperand(i).ChangeToRegister(FrameReg, false);
274 MI.getOperand(i+1).ChangeToImmediate(Offset);
269 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
270 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
275271 }
276272 }
277273
6060 MachineBasicBlock::iterator I) const;
6161
6262 void eliminateFrameIndex(MachineBasicBlock::iterator II,
63 int SPAdj, RegScavenger *RS = NULL) const;
63 int SPAdj, unsigned FIOperandNum,
64 RegScavenger *RS = NULL) const;
6465
6566 /// determineFrameLayout - Determine the size of the frame and maximum call
6667 /// frame size.
125125 // direct reference.
126126 void MBlazeRegisterInfo::
127127 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
128 RegScavenger *RS) const {
128 unsigned FIOperandNum, RegScavenger *RS) const {
129129 MachineInstr &MI = *II;
130130 MachineFunction &MF = *MI.getParent()->getParent();
131131 MachineFrameInfo *MFI = MF.getFrameInfo();
132
133 unsigned i = 0;
134 while (!MI.getOperand(i).isFI()) {
135 ++i;
136 assert(i < MI.getNumOperands() &&
137 "Instr doesn't have FrameIndex operand!");
138 }
139
140 unsigned oi = i == 2 ? 1 : 2;
132 unsigned OFIOperandNum = FIOperandNum == 2 ? 1 : 2;
141133
142134 DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n";
143135 dbgs() << "<--------->\n" << MI);
144136
145 int FrameIndex = MI.getOperand(i).getIndex();
137 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
146138 int stackSize = MFI->getStackSize();
147139 int spOffset = MFI->getObjectOffset(FrameIndex);
148140
158150 // as explained on LowerFormalArguments, detect negative offsets
159151 // and adjust SPOffsets considering the final stack size.
160152 int Offset = (spOffset < 0) ? (stackSize - spOffset) : spOffset;
161 Offset += MI.getOperand(oi).getImm();
153 Offset += MI.getOperand(OFIOperandNum).getImm();
162154
163155 DEBUG(dbgs() << "Offset : " << Offset << "\n" << "<--------->\n");
164156
165 MI.getOperand(oi).ChangeToImmediate(Offset);
166 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
157 MI.getOperand(OFIOperandNum).ChangeToImmediate(Offset);
158 MI.getOperand(FIOperandNum).ChangeToRegister(getFrameRegister(MF), false);
167159 }
168160
169161 void MBlazeRegisterInfo::
5555
5656 /// Stack Frame Processing Methods
5757 void eliminateFrameIndex(MachineBasicBlock::iterator II,
58 int SPAdj, RegScavenger *RS = NULL) const;
58 int SPAdj, unsigned FIOperandNum,
59 RegScavenger *RS = NULL) const;
5960
6061 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
6162
162162
163163 void
164164 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
165 int SPAdj, RegScavenger *RS) const {
165 int SPAdj, unsigned FIOperandNum,
166 RegScavenger *RS) const {
166167 assert(SPAdj == 0 && "Unexpected");
167168
168169 unsigned i = 0;
171172 MachineFunction &MF = *MBB.getParent();
172173 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
173174 DebugLoc dl = MI.getDebugLoc();
174 while (!MI.getOperand(i).isFI()) {
175 ++i;
176 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
177 }
178
179 int FrameIndex = MI.getOperand(i).getIndex();
175 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
180176
181177 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
182178 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
190186 Offset += 2; // Skip the saved FPW
191187
192188 // Fold imm into offset
193 Offset += MI.getOperand(i+1).getImm();
189 Offset += MI.getOperand(FIOperandNum + 1).getImm();
194190
195191 if (MI.getOpcode() == MSP430::ADD16ri) {
196192 // This is actually "load effective address" of the stack slot
198194 // expand it into mov + add
199195
200196 MI.setDesc(TII.get(MSP430::MOV16rr));
201 MI.getOperand(i).ChangeToRegister(BasePtr, false);
197 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
202198
203199 if (Offset == 0)
204200 return;
215211 return;
216212 }
217213
218 MI.getOperand(i).ChangeToRegister(BasePtr, false);
219 MI.getOperand(i+1).ChangeToImmediate(Offset);
214 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
215 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
220216 }
221217
222218 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
4646 MachineBasicBlock::iterator I) const;
4747
4848 void eliminateFrameIndex(MachineBasicBlock::iterator II,
49 int SPAdj, RegScavenger *RS = NULL) const;
49 int SPAdj, unsigned FIOperandNum,
50 RegScavenger *RS = NULL) const;
5051
5152 // Debug information queries.
5253 unsigned getFrameRegister(const MachineFunction &MF) const;
176176 // direct reference.
177177 void MipsRegisterInfo::
178178 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
179 RegScavenger *RS) const {
179 unsigned FIOperandNum, RegScavenger *RS) const {
180180 MachineInstr &MI = *II;
181181 MachineFunction &MF = *MI.getParent()->getParent();
182182
183 unsigned i = 0;
184 while (!MI.getOperand(i).isFI()) {
185 ++i;
186 assert(i < MI.getNumOperands() &&
187 "Instr doesn't have FrameIndex operand!");
188 }
189
190183 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
191184 errs() << "<--------->\n" << MI);
192185
193 int FrameIndex = MI.getOperand(i).getIndex();
186 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
194187 uint64_t stackSize = MF.getFrameInfo()->getStackSize();
195188 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
196189
198191 << "spOffset : " << spOffset << "\n"
199192 << "stackSize : " << stackSize << "\n");
200193
201 eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
194 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
202195 }
203196
204197 unsigned MipsRegisterInfo::
5454
5555 /// Stack Frame Processing Methods
5656 void eliminateFrameIndex(MachineBasicBlock::iterator II,
57 int SPAdj, RegScavenger *RS = NULL) const;
57 int SPAdj, unsigned FIOperandNum,
58 RegScavenger *RS = NULL) const;
5859
5960 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
6061
276276
277277 void NVPTXRegisterInfo::
278278 eliminateFrameIndex(MachineBasicBlock::iterator II,
279 int SPAdj,
279 int SPAdj, unsigned FIOperandNum,
280280 RegScavenger *RS) const {
281281 assert(SPAdj == 0 && "Unexpected");
282282
283 unsigned i = 0;
284283 MachineInstr &MI = *II;
285 while (!MI.getOperand(i).isFI()) {
286 ++i;
287 assert(i < MI.getNumOperands() &&
288 "Instr doesn't have FrameIndex operand!");
289 }
290
291 int FrameIndex = MI.getOperand(i).getIndex();
284 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
292285
293286 MachineFunction &MF = *MI.getParent()->getParent();
294287 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
295 MI.getOperand(i+1).getImm();
288 MI.getOperand(FIOperandNum+1).getImm();
296289
297290 // Using I0 as the frame pointer
298 MI.getOperand(i).ChangeToRegister(NVPTX::VRFrame, false);
299 MI.getOperand(i+1).ChangeToImmediate(Offset);
300 }
301
291 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
292 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
293 }
302294
303295 int NVPTXRegisterInfo::
304296 getDwarfRegNum(unsigned RegNum, bool isEH) const {
5454 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
5555
5656 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
57 int SPAdj,
57 int SPAdj, unsigned FIOperandNum,
5858 RegScavenger *RS=NULL) const;
5959
6060 void eliminateCallFramePseudoInstr(MachineFunction &MF,
509509
510510 void
511511 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
512 int SPAdj, RegScavenger *RS) const {
512 int SPAdj, unsigned FIOperandNum,
513 RegScavenger *RS) const {
513514 assert(SPAdj == 0 && "Unexpected");
514515
515516 // Get the instruction.
523524 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
524525 DebugLoc dl = MI.getDebugLoc();
525526
526 // Find out which operand is the frame index.
527 unsigned FIOperandNo = 0;
528 while (!MI.getOperand(FIOperandNo).isFI()) {
529 ++FIOperandNo;
530 assert(FIOperandNo != MI.getNumOperands() &&
531 "Instr doesn't have FrameIndex operand!");
532 }
533527 // Take into account whether it's an add or mem instruction
534 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
528 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
535529 if (MI.isInlineAsm())
536 OffsetOperandNo = FIOperandNo-1;
530 OffsetOperandNo = FIOperandNum-1;
537531
538532 // Get the frame index.
539 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
533 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
540534
541535 // Get the frame pointer save index. Users of this index are primarily
542536 // DYNALLOC instructions.
566560 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
567561
568562 bool is64Bit = Subtarget.isPPC64();
569 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
563 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
570564 (is64Bit ? PPC::X31 : PPC::R31) :
571565 (is64Bit ? PPC::X1 : PPC::R1),
572566 false);
648642 OperandBase = OffsetOperandNo;
649643 }
650644
651 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
645 unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
652646 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
653647 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
654648 }
6868 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
6969 int &FrameIdx) const;
7070 void eliminateFrameIndex(MachineBasicBlock::iterator II,
71 int SPAdj, RegScavenger *RS = NULL) const;
71 int SPAdj, unsigned FIOperandNum,
72 RegScavenger *RS = NULL) const;
7273
7374 // Debug information queries.
7475 unsigned getFrameRegister(const MachineFunction &MF) const;
7070
7171 void
7272 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
73 int SPAdj, RegScavenger *RS) const {
73 int SPAdj, unsigned FIOperandNum,
74 RegScavenger *RS) const {
7475 assert(SPAdj == 0 && "Unexpected");
7576
76 unsigned i = 0;
7777 MachineInstr &MI = *II;
7878 DebugLoc dl = MI.getDebugLoc();
79 while (!MI.getOperand(i).isFI()) {
80 ++i;
81 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
82 }
83
84 int FrameIndex = MI.getOperand(i).getIndex();
79 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
8580
8681 // Addressable stack objects are accessed using neg. offsets from %fp
8782 MachineFunction &MF = *MI.getParent()->getParent();
8883 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
89 MI.getOperand(i+1).getImm();
84 MI.getOperand(FIOperandNum + 1).getImm();
9085
9186 // Replace frame index with a frame pointer reference.
9287 if (Offset >= -4096 && Offset <= 4095) {
9388 // If the offset is small enough to fit in the immediate field, directly
9489 // encode it.
95 MI.getOperand(i).ChangeToRegister(SP::I6, false);
96 MI.getOperand(i+1).ChangeToImmediate(Offset);
90 MI.getOperand(FIOperandNum).ChangeToRegister(SP::I6, false);
91 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
9792 } else {
9893 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
9994 // scavenge a register here instead of reserving G1 all of the time.
10398 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
10499 .addReg(SP::I6);
105100 // Insert: G1+%lo(offset) into the user.
106 MI.getOperand(i).ChangeToRegister(SP::G1, false);
107 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
101 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
102 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
108103 }
109104 }
110105
4040 MachineBasicBlock::iterator I) const;
4141
4242 void eliminateFrameIndex(MachineBasicBlock::iterator II,
43 int SPAdj, RegScavenger *RS = NULL) const;
43 int SPAdj, unsigned FIOperandNum,
44 RegScavenger *RS = NULL) const;
4445
4546 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4647
543543
544544 void
545545 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
546 int SPAdj, RegScavenger *RS) const {
546 int SPAdj, unsigned FIOperandNum,
547 RegScavenger *RS) const {
547548 assert(SPAdj == 0 && "Unexpected");
548549
549 unsigned i = 0;
550550 MachineInstr &MI = *II;
551551 MachineFunction &MF = *MI.getParent()->getParent();
552552 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
553
554 while (!MI.getOperand(i).isFI()) {
555 ++i;
556 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
557 }
558
559 int FrameIndex = MI.getOperand(i).getIndex();
553 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
560554 unsigned BasePtr;
561555
562556 unsigned Opc = MI.getOpcode();
572566
573567 // This must be part of a four operand memory reference. Replace the
574568 // FrameIndex with base register with EBP. Add an offset to the offset.
575 MI.getOperand(i).ChangeToRegister(BasePtr, false);
569 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
576570
577571 // Now add the frame object offset to the offset from EBP.
578572 int FIOffset;
583577 } else
584578 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
585579
586 if (MI.getOperand(i+3).isImm()) {
580 if (MI.getOperand(FIOperandNum+3).isImm()) {
587581 // Offset is a 32-bit integer.
588 int Imm = (int)(MI.getOperand(i + 3).getImm());
582 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
589583 int Offset = FIOffset + Imm;
590584 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
591585 "Requesting 64-bit offset in 32-bit immediate!");
592 MI.getOperand(i + 3).ChangeToImmediate(Offset);
586 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
593587 } else {
594588 // Offset is symbolic. This is extremely rare.
595 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
596 MI.getOperand(i+3).setOffset(Offset);
589 uint64_t Offset = FIOffset +
590 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
591 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
597592 }
598593 }
599594
121121 MachineBasicBlock::iterator MI) const;
122122
123123 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
124 int SPAdj, RegScavenger *RS = NULL) const;
124 int SPAdj, unsigned FIOperandNum,
125 RegScavenger *RS = NULL) const;
125126
126127 // Debug information queries.
127128 unsigned getFrameRegister(const MachineFunction &MF) const;
154154
155155 void
156156 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
157 int SPAdj, RegScavenger *RS) const {
157 int SPAdj, unsigned FIOperandNum,
158 RegScavenger *RS) const {
158159 assert(SPAdj == 0 && "Unexpected");
159160 MachineInstr &MI = *II;
160161 DebugLoc dl = MI.getDebugLoc();
161 unsigned i = 0;
162
163 while (!MI.getOperand(i).isFI()) {
164 ++i;
165 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
166 }
167
168 MachineOperand &FrameOp = MI.getOperand(i);
162 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
169163 int FrameIndex = FrameOp.getIndex();
170164
171165 MachineFunction &MF = *MI.getParent()->getParent();
189183
190184 // Special handling of DBG_VALUE instructions.
191185 if (MI.isDebugValue()) {
192 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
193 MI.getOperand(i+1).ChangeToImmediate(Offset);
186 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
187 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
194188 return;
195189 }
196190
197191 // fold constant into offset.
198 Offset += MI.getOperand(i + 1).getImm();
199 MI.getOperand(i + 1).ChangeToImmediate(0);
192 Offset += MI.getOperand(FIOperandNum + 1).getImm();
193 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
200194
201195 assert(Offset%4 == 0 && "Misaligned stack offset");
202196
5858 MachineBasicBlock::iterator I) const;
5959
6060 void eliminateFrameIndex(MachineBasicBlock::iterator II,
61 int SPAdj, RegScavenger *RS = NULL) const;
61 int SPAdj, unsigned FIOperandNum,
62 RegScavenger *RS = NULL) const;
6263
6364 // Debug information queries.
6465 unsigned getFrameRegister(const MachineFunction &MF) const;