llvm.org GIT mirror llvm / 108934c
Instruction fixes, added instructions, and AsmString changes in the X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8 Sean Callanan 10 years ago
24 changed file(s) with 1437 addition(s) and 624 deletion(s). Raw diff Collapse all Expand all
6262 def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
6363 "Enable AVX instructions">;
6464 def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
65 "Enable three-operand fused multiple-add">;
65 "Enable three-operand fused multiple-add">;
6666 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
6767 "Enable four-operand fused multiple-add">;
6868
109109 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
110110 Requires<[In64BitMode]>;
111111 }
112
113 // Interrupt Instructions
114 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>;
112115
113116 //===----------------------------------------------------------------------===//
114117 // Call Instructions...
130133 // the 32-bit pcrel field that we have.
131134 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
132135 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
133 "call\t$dst", []>,
136 "call{q}\t$dst", []>,
134137 Requires<[In64BitMode, NotWin64]>;
135138 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
136 "call\t{*}$dst", [(X86call GR64:$dst)]>,
139 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
137140 Requires<[NotWin64]>;
138141 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
139 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
142 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
140143 Requires<[NotWin64]>;
141144
142145 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
143146 "lcall{q}\t{*}$dst", []>;
144147 }
145148
146 // FIXME: We need to teach codegen about single list of call-clobbered registers.
149 // FIXME: We need to teach codegen about single list of call-clobbered
150 // registers.
147151 let isCall = 1 in
148152 // All calls clobber the non-callee saved registers. RSP is marked as
149153 // a use to prevent stack-pointer assignments that appear immediately
161165 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
162166 "call\t{*}$dst",
163167 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
164 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
165 "call\t{*}$dst",
166 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
168 def WINCALL64m : I<0xFF, MRM2m, (outs),
169 (ins i64mem:$dst, variable_ops), "call\t{*}$dst",
170 [(X86call (loadi64 addr:$dst))]>,
171 Requires<[IsWin64]>;
167172 }
168173
169174
187192
188193 // Branches
189194 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
195 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
196 "jmp{q}\t$dst", []>;
190197 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
191198 [(brind GR64:$dst)]>;
192199 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
209216 //===----------------------------------------------------------------------===//
210217 // Miscellaneous Instructions...
211218 //
219
220 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
221 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
222 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
223 "popcnt{q}\t{$src, $dst|$dst, $src}", []>, XS;
224
212225 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
213226 def LEAVE64 : I<0xC9, RawFrm,
214227 (outs), (ins), "leave", []>;
237250 }
238251
239252 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
240 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
253 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf{q}", []>, REX_W;
241254 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
242 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
255 def PUSHFQ64 : I<0x9C, RawFrm, (outs), (ins), "pushf{q}", []>;
243256
244257 def LEA64_32r : I<0x8D, MRMSrcMem,
245258 (outs GR32:$dst), (ins lea64_32mem:$src),
308321 [(set GR64:$dst, i64immSExt32:$src)]>;
309322 }
310323
324 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
325 "mov{q}\t{$src, $dst|$dst, $src}", []>;
326
311327 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
312328 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
313329 "mov{q}\t{$src, $dst|$dst, $src}",
320336 "mov{q}\t{$src, $dst|$dst, $src}",
321337 [(store i64immSExt32:$src, addr:$dst)]>;
322338
323 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
339 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
324340 "mov{q}\t{$src, %rax|%rax, $src}", []>;
325 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
341 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
326342 "mov{q}\t{$src, %rax|%rax, $src}", []>;
327 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
343 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
328344 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
329 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
345 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
330346 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
331347
332348 // Moves to and from segment registers
333349 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
334 "mov{w}\t{$src, $dst|$dst, $src}", []>;
350 "mov{q}\t{$src, $dst|$dst, $src}", []>;
335351 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
336 "mov{w}\t{$src, $dst|$dst, $src}", []>;
352 "mov{q}\t{$src, $dst|$dst, $src}", []>;
337353 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
338 "mov{w}\t{$src, $dst|$dst, $src}", []>;
354 "mov{q}\t{$src, $dst|$dst, $src}", []>;
339355 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
340 "mov{w}\t{$src, $dst|$dst, $src}", []>;
356 "mov{q}\t{$src, $dst|$dst, $src}", []>;
357
358 // Moves to and from debug registers
359 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
360 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
361 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
362 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
363
364 // Moves to and from control registers
365 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG_64:$src),
366 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
367 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_64:$dst), (ins GR64:$src),
368 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
341369
342370 // Sign/Zero extenders
343371
364392 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
365393 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
366394
395 // movzbq and movzwq encodings for the disassembler
396 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
397 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
398 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
399 "movz{bq|x}\t{$src, $dst|$dst, $src}", []>, TB;
400 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
401 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
402 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
403 "movz{wq|x}\t{$src, $dst|$dst, $src}", []>, TB;
404
367405 // Use movzbl instead of movzbq when the destination is a register; it's
368406 // equivalent due to implicit zero-extending, and it has a smaller encoding.
369407 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
429467 let isConvertibleToThreeAddress = 1 in {
430468 let isCommutable = 1 in
431469 // Register-Register Addition
432 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
470 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
471 (ins GR64:$src1, GR64:$src2),
433472 "add{q}\t{$src2, $dst|$dst, $src2}",
434473 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
435474 (implicit EFLAGS)]>;
436475
437476 // Register-Integer Addition
438 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
477 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
478 (ins GR64:$src1, i64i8imm:$src2),
439479 "add{q}\t{$src2, $dst|$dst, $src2}",
440480 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
441481 (implicit EFLAGS)]>;
442 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
482 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
483 (ins GR64:$src1, i64i32imm:$src2),
443484 "add{q}\t{$src2, $dst|$dst, $src2}",
444485 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
445486 (implicit EFLAGS)]>;
446487 } // isConvertibleToThreeAddress
447488
448489 // Register-Memory Addition
449 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
490 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
491 (ins GR64:$src1, i64mem:$src2),
450492 "add{q}\t{$src2, $dst|$dst, $src2}",
451493 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
452494 (implicit EFLAGS)]>;
453495
454496 // Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
455497 // differently encoded.
456 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
498 def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
499 (ins GR64:$src1, GR64:$src2),
457500 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
458501
459502 } // isTwoAddress
479522
480523 let isTwoAddress = 1 in {
481524 let isCommutable = 1 in
482 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
525 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
526 (ins GR64:$src1, GR64:$src2),
483527 "adc{q}\t{$src2, $dst|$dst, $src2}",
484528 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
485529
486 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
530 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
531 (ins GR64:$src1, GR64:$src2),
532 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
533
534 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
535 (ins GR64:$src1, i64mem:$src2),
487536 "adc{q}\t{$src2, $dst|$dst, $src2}",
488537 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
489538
490 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
539 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
540 (ins GR64:$src1, i64i8imm:$src2),
491541 "adc{q}\t{$src2, $dst|$dst, $src2}",
492542 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
493 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
543 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
544 (ins GR64:$src1, i64i32imm:$src2),
494545 "adc{q}\t{$src2, $dst|$dst, $src2}",
495546 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
496547 } // isTwoAddress
500551 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
501552 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
502553 "adc{q}\t{$src2, $dst|$dst, $src2}",
503 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
554 [(store (adde (load addr:$dst), i64immSExt8:$src2),
555 addr:$dst)]>;
504556 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
505557 "adc{q}\t{$src2, $dst|$dst, $src2}",
506 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
558 [(store (adde (load addr:$dst), i64immSExt8:$src2),
559 addr:$dst)]>;
507560 } // Uses = [EFLAGS]
508561
509562 let isTwoAddress = 1 in {
510563 // Register-Register Subtraction
511 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
564 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
565 (ins GR64:$src1, GR64:$src2),
512566 "sub{q}\t{$src2, $dst|$dst, $src2}",
513567 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
514568 (implicit EFLAGS)]>;
515569
570 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
571 (ins GR64:$src1, GR64:$src2),
572 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
573
516574 // Register-Memory Subtraction
517 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
575 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
576 (ins GR64:$src1, i64mem:$src2),
518577 "sub{q}\t{$src2, $dst|$dst, $src2}",
519578 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
520579 (implicit EFLAGS)]>;
555614
556615 let Uses = [EFLAGS] in {
557616 let isTwoAddress = 1 in {
558 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
617 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
618 (ins GR64:$src1, GR64:$src2),
559619 "sbb{q}\t{$src2, $dst|$dst, $src2}",
560620 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
561621
562 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
622 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
623 (ins GR64:$src1, GR64:$src2),
624 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
625
626 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
627 (ins GR64:$src1, i64mem:$src2),
563628 "sbb{q}\t{$src2, $dst|$dst, $src2}",
564629 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
565630
566 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
631 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
632 (ins GR64:$src1, i64i8imm:$src2),
567633 "sbb{q}\t{$src2, $dst|$dst, $src2}",
568634 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
569 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
635 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
636 (ins GR64:$src1, i64i32imm:$src2),
570637 "sbb{q}\t{$src2, $dst|$dst, $src2}",
571638 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
572639 } // isTwoAddress
651718
652719 // Unsigned division / remainder
653720 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
654 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
721 // RDX:RAX/r64 = RAX,RDX
722 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
655723 "div{q}\t$src", []>;
656724 // Signed division / remainder
657 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
725 // RDX:RAX/r64 = RAX,RDX
726 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
658727 "idiv{q}\t$src", []>;
659728 let mayLoad = 1 in {
660 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
729 // RDX:RAX/[mem64] = RAX,RDX
730 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
661731 "div{q}\t$src", []>;
662 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
732 // RDX:RAX/[mem64] = RAX,RDX
733 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
663734 "idiv{q}\t$src", []>;
664735 }
665736 }
693764 // In 64-bit mode, single byte INC and DEC cannot be encoded.
694765 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
695766 // Can transform into LEA.
696 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
767 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src),
768 "inc{w}\t$dst",
697769 [(set GR16:$dst, (add GR16:$src, 1)),
698770 (implicit EFLAGS)]>,
699771 OpSize, Requires<[In64BitMode]>;
700 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
772 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src),
773 "inc{l}\t$dst",
701774 [(set GR32:$dst, (add GR32:$src, 1)),
702775 (implicit EFLAGS)]>,
703776 Requires<[In64BitMode]>;
704 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
777 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src),
778 "dec{w}\t$dst",
705779 [(set GR16:$dst, (add GR16:$src, -1)),
706780 (implicit EFLAGS)]>,
707781 OpSize, Requires<[In64BitMode]>;
708 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
782 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src),
783 "dec{l}\t$dst",
709784 [(set GR32:$dst, (add GR32:$src, -1)),
710785 (implicit EFLAGS)]>,
711786 Requires<[In64BitMode]>;
742817 "shl{q}\t{%cl, $dst|$dst, %CL}",
743818 [(set GR64:$dst, (shl GR64:$src, CL))]>;
744819 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
745 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
820 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
821 (ins GR64:$src1, i8imm:$src2),
746822 "shl{q}\t{$src2, $dst|$dst, $src2}",
747823 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
748824 // NOTE: We don't include patterns for shifts of a register by one, because
749825 // 'add reg,reg' is cheaper.
750826 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
751 "shr{q}\t$dst", []>;
827 "shl{q}\t$dst", []>;
752828 } // isTwoAddress
753829
754830 let Uses = [CL] in
791867 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
792868 "sar{q}\t{%cl, $dst|$dst, %CL}",
793869 [(set GR64:$dst, (sra GR64:$src, CL))]>;
794 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
795 "sar{q}\t{$src2, $dst|$dst, $src2}",
796 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
870 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
871 (ins GR64:$src1, i8imm:$src2),
872 "sar{q}\t{$src2, $dst|$dst, $src2}",
873 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
797874 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
798875 "sar{q}\t$dst",
799876 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
825902 }
826903 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
827904 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
828 def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
905 def RCL64mi : RIi8<0xC1, MRM2m, (outs i64mem:$dst),
906 (ins i64mem:$src, i8imm:$cnt),
829907 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
830908
831909 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src),
840918 }
841919 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt),
842920 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
843 def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst), (ins i64mem:$src, i8imm:$cnt),
921 def RCR64mi : RIi8<0xC1, MRM3m, (outs i64mem:$dst),
922 (ins i64mem:$src, i8imm:$cnt),
844923 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
845924 }
846925
849928 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
850929 "rol{q}\t{%cl, $dst|$dst, %CL}",
851930 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
852 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
931 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
932 (ins GR64:$src1, i8imm:$src2),
853933 "rol{q}\t{$src2, $dst|$dst, $src2}",
854934 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
855935 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
858938 } // isTwoAddress
859939
860940 let Uses = [CL] in
861 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
862 "rol{q}\t{%cl, $dst|$dst, %CL}",
863 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
941 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
942 "rol{q}\t{%cl, $dst|$dst, %CL}",
943 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
864944 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
865945 "rol{q}\t{$src, $dst|$dst, $src}",
866946 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
873953 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
874954 "ror{q}\t{%cl, $dst|$dst, %CL}",
875955 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
876 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
956 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
957 (ins GR64:$src1, i8imm:$src2),
877958 "ror{q}\t{$src2, $dst|$dst, $src2}",
878959 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
879960 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
895976 // Double shift instructions (generalizations of rotate)
896977 let isTwoAddress = 1 in {
897978 let Uses = [CL] in {
898 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
979 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
980 (ins GR64:$src1, GR64:$src2),
899981 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
900 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
901 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
982 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
983 TB;
984 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
985 (ins GR64:$src1, GR64:$src2),
902986 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
903 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
987 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
988 TB;
904989 }
905990
906991 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
907992 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
908 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
993 (outs GR64:$dst),
994 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
909995 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
910996 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
911997 (i8 imm:$src3)))]>,
912998 TB;
913999 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
914 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
1000 (outs GR64:$dst),
1001 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
9151002 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
9161003 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
9171004 (i8 imm:$src3)))]>,
9641051 "and{q}\t{$src2, $dst|$dst, $src2}",
9651052 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
9661053 (implicit EFLAGS)]>;
1054 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
1055 (ins GR64:$src1, GR64:$src2),
1056 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
9671057 def AND64rm : RI<0x23, MRMSrcMem,
9681058 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
9691059 "and{q}\t{$src2, $dst|$dst, $src2}",
9991089
10001090 let isTwoAddress = 1 in {
10011091 let isCommutable = 1 in
1002 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1092 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
1093 (ins GR64:$src1, GR64:$src2),
10031094 "or{q}\t{$src2, $dst|$dst, $src2}",
10041095 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
10051096 (implicit EFLAGS)]>;
1006 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1097 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
1098 (ins GR64:$src1, GR64:$src2),
1099 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
1100 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
1101 (ins GR64:$src1, i64mem:$src2),
10071102 "or{q}\t{$src2, $dst|$dst, $src2}",
10081103 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
10091104 (implicit EFLAGS)]>;
1010 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1105 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
1106 (ins GR64:$src1, i64i8imm:$src2),
10111107 "or{q}\t{$src2, $dst|$dst, $src2}",
10121108 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
10131109 (implicit EFLAGS)]>;
1014 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1110 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
1111 (ins GR64:$src1, i64i32imm:$src2),
10151112 "or{q}\t{$src2, $dst|$dst, $src2}",
10161113 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
10171114 (implicit EFLAGS)]>;
10351132
10361133 let isTwoAddress = 1 in {
10371134 let isCommutable = 1 in
1038 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1135 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
1136 (ins GR64:$src1, GR64:$src2),
10391137 "xor{q}\t{$src2, $dst|$dst, $src2}",
10401138 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
10411139 (implicit EFLAGS)]>;
1042 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1140 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
1141 (ins GR64:$src1, GR64:$src2),
1142 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
1143 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
1144 (ins GR64:$src1, i64mem:$src2),
10431145 "xor{q}\t{$src2, $dst|$dst, $src2}",
10441146 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
10451147 (implicit EFLAGS)]>;
1046 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1148 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1149 (ins GR64:$src1, i64i8imm:$src2),
10471150 "xor{q}\t{$src2, $dst|$dst, $src2}",
10481151 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
10491152 (implicit EFLAGS)]>;
11471250 // Unlike with the register+register form, the memory+register form of the
11481251 // bt instruction does not ignore the high bits of the index. From ISel's
11491252 // perspective, this is pretty bizarre. Disable these instructions for now.
1150 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1151 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1253 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1254 "bt{q}\t{$src2, $src1|$src1, $src2}",
11521255 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1153 // (implicit EFLAGS)]>, TB;
1256 // (implicit EFLAGS)]
1257 []
1258 >, TB;
11541259
11551260 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
11561261 "bt{q}\t{$src2, $src1|$src1, $src2}",
11631268 "bt{q}\t{$src2, $src1|$src1, $src2}",
11641269 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
11651270 (implicit EFLAGS)]>, TB;
1271
1272 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1273 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1274 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1275 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1276 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1277 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1278 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1279 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1280
1281 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1282 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1283 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1284 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1285 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1286 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1287 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1288 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1289
1290 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1291 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1292 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1293 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1294 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1295 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1296 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1297 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
11661298 } // Defs = [EFLAGS]
11671299
11681300 // Conditional moves
11701302 let isCommutable = 1 in {
11711303 def CMOVB64rr : RI<0x42, MRMSrcReg, // if
11721304 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1173 "cmovb\t{$src2, $dst|$dst, $src2}",
1305 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
11741306 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
11751307 X86_COND_B, EFLAGS))]>, TB;
11761308 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
11771309 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1178 "cmovae\t{$src2, $dst|$dst, $src2}",
1310 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
11791311 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
11801312 X86_COND_AE, EFLAGS))]>, TB;
11811313 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
11821314 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1183 "cmove\t{$src2, $dst|$dst, $src2}",
1315 "cmove{q}\t{$src2, $dst|$dst, $src2}",
11841316 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
11851317 X86_COND_E, EFLAGS))]>, TB;
11861318 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
11871319 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1188 "cmovne\t{$src2, $dst|$dst, $src2}",
1320 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
11891321 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
11901322 X86_COND_NE, EFLAGS))]>, TB;
11911323 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
11921324 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1193 "cmovbe\t{$src2, $dst|$dst, $src2}",
1325 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
11941326 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
11951327 X86_COND_BE, EFLAGS))]>, TB;
11961328 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
11971329 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1198 "cmova\t{$src2, $dst|$dst, $src2}",
1330 "cmova{q}\t{$src2, $dst|$dst, $src2}",
11991331 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12001332 X86_COND_A, EFLAGS))]>, TB;
12011333 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if
12021334 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1203 "cmovl\t{$src2, $dst|$dst, $src2}",
1335 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
12041336 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12051337 X86_COND_L, EFLAGS))]>, TB;
12061338 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
12071339 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1208 "cmovge\t{$src2, $dst|$dst, $src2}",
1340 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
12091341 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12101342 X86_COND_GE, EFLAGS))]>, TB;
12111343 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
12121344 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1213 "cmovle\t{$src2, $dst|$dst, $src2}",
1345 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
12141346 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12151347 X86_COND_LE, EFLAGS))]>, TB;
12161348 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
12171349 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1218 "cmovg\t{$src2, $dst|$dst, $src2}",
1350 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
12191351 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12201352 X86_COND_G, EFLAGS))]>, TB;
12211353 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
12221354 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1223 "cmovs\t{$src2, $dst|$dst, $src2}",
1355 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
12241356 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12251357 X86_COND_S, EFLAGS))]>, TB;
12261358 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
12271359 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1228 "cmovns\t{$src2, $dst|$dst, $src2}",
1360 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
12291361 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12301362 X86_COND_NS, EFLAGS))]>, TB;
12311363 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
12321364 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1233 "cmovp\t{$src2, $dst|$dst, $src2}",
1365 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
12341366 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12351367 X86_COND_P, EFLAGS))]>, TB;
12361368 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
12371369 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1238 "cmovnp\t{$src2, $dst|$dst, $src2}",
1370 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
12391371 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12401372 X86_COND_NP, EFLAGS))]>, TB;
12411373 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
12421374 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1243 "cmovo\t{$src2, $dst|$dst, $src2}",
1375 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
12441376 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12451377 X86_COND_O, EFLAGS))]>, TB;
12461378 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
12471379 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1248 "cmovno\t{$src2, $dst|$dst, $src2}",
1380 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
12491381 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
12501382 X86_COND_NO, EFLAGS))]>, TB;
12511383 } // isCommutable = 1
12521384
12531385 def CMOVB64rm : RI<0x42, MRMSrcMem, // if
12541386 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1255 "cmovb\t{$src2, $dst|$dst, $src2}",
1387 "cmovb{q}\t{$src2, $dst|$dst, $src2}",
12561388 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12571389 X86_COND_B, EFLAGS))]>, TB;
12581390 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
12591391 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1260 "cmovae\t{$src2, $dst|$dst, $src2}",
1392 "cmovae{q}\t{$src2, $dst|$dst, $src2}",
12611393 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12621394 X86_COND_AE, EFLAGS))]>, TB;
12631395 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
12641396 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1265 "cmove\t{$src2, $dst|$dst, $src2}",
1397 "cmove{q}\t{$src2, $dst|$dst, $src2}",
12661398 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12671399 X86_COND_E, EFLAGS))]>, TB;
12681400 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
12691401 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1270 "cmovne\t{$src2, $dst|$dst, $src2}",
1402 "cmovne{q}\t{$src2, $dst|$dst, $src2}",
12711403 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12721404 X86_COND_NE, EFLAGS))]>, TB;
12731405 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
12741406 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1275 "cmovbe\t{$src2, $dst|$dst, $src2}",
1407 "cmovbe{q}\t{$src2, $dst|$dst, $src2}",
12761408 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12771409 X86_COND_BE, EFLAGS))]>, TB;
12781410 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
12791411 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1280 "cmova\t{$src2, $dst|$dst, $src2}",
1412 "cmova{q}\t{$src2, $dst|$dst, $src2}",
12811413 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12821414 X86_COND_A, EFLAGS))]>, TB;
12831415 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if
12841416 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1285 "cmovl\t{$src2, $dst|$dst, $src2}",
1417 "cmovl{q}\t{$src2, $dst|$dst, $src2}",
12861418 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12871419 X86_COND_L, EFLAGS))]>, TB;
12881420 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
12891421 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1290 "cmovge\t{$src2, $dst|$dst, $src2}",
1422 "cmovge{q}\t{$src2, $dst|$dst, $src2}",
12911423 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12921424 X86_COND_GE, EFLAGS))]>, TB;
12931425 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
12941426 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1295 "cmovle\t{$src2, $dst|$dst, $src2}",
1427 "cmovle{q}\t{$src2, $dst|$dst, $src2}",
12961428 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
12971429 X86_COND_LE, EFLAGS))]>, TB;
12981430 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
12991431 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1300 "cmovg\t{$src2, $dst|$dst, $src2}",
1432 "cmovg{q}\t{$src2, $dst|$dst, $src2}",
13011433 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13021434 X86_COND_G, EFLAGS))]>, TB;
13031435 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
13041436 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1305 "cmovs\t{$src2, $dst|$dst, $src2}",
1437 "cmovs{q}\t{$src2, $dst|$dst, $src2}",
13061438 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13071439 X86_COND_S, EFLAGS))]>, TB;
13081440 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
13091441 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1310 "cmovns\t{$src2, $dst|$dst, $src2}",
1442 "cmovns{q}\t{$src2, $dst|$dst, $src2}",
13111443 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13121444 X86_COND_NS, EFLAGS))]>, TB;
13131445 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
13141446 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1315 "cmovp\t{$src2, $dst|$dst, $src2}",
1447 "cmovp{q}\t{$src2, $dst|$dst, $src2}",
13161448 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13171449 X86_COND_P, EFLAGS))]>, TB;
13181450 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
13191451 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1320 "cmovnp\t{$src2, $dst|$dst, $src2}",
1452 "cmovnp{q}\t{$src2, $dst|$dst, $src2}",
13211453 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13221454 X86_COND_NP, EFLAGS))]>, TB;
13231455 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
13241456 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1325 "cmovo\t{$src2, $dst|$dst, $src2}",
1457 "cmovo{q}\t{$src2, $dst|$dst, $src2}",
13261458 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13271459 X86_COND_O, EFLAGS))]>, TB;
13281460 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
13291461 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1330 "cmovno\t{$src2, $dst|$dst, $src2}",
1462 "cmovno{q}\t{$src2, $dst|$dst, $src2}",
13311463 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
13321464 X86_COND_NO, EFLAGS))]>, TB;
13331465 } // isTwoAddress
13461478 //
13471479
13481480 // f64 -> signed i64
1481 def CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1482 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
1483 def CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1484 "cvtsd2si{q}\t{$src, $dst|$dst, $src}", []>;
13491485 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
13501486 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
13511487 [(set GR64:$dst,
13521488 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1353 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1489 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst),
1490 (ins f128mem:$src),
13541491 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
13551492 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
13561493 (load addr:$src)))]>;
13641501 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
13651502 [(set GR64:$dst,
13661503 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1367 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1504 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst),
1505 (ins f128mem:$src),
13681506 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
13691507 [(set GR64:$dst,
13701508 (int_x86_sse2_cvttsd2si64
14091547 (int_x86_sse_cvtsi642ss VR128:$src1,
14101548 GR64:$src2))]>;
14111549 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1412 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1550 (outs VR128:$dst),
1551 (ins VR128:$src1, i64mem:$src2),
14131552 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
14141553 [(set VR128:$dst,
14151554 (int_x86_sse_cvtsi642ss VR128:$src1,
14171556 }
14181557
14191558 // f32 -> signed i64
1559 def CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1560 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
1561 def CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1562 "cvtss2si{q}\t{$src, $dst|$dst, $src}", []>;
14201563 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
14211564 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
14221565 [(set GR64:$dst,
14351578 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
14361579 [(set GR64:$dst,
14371580 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1438 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1581 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst),
1582 (ins f32mem:$src),
14391583 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
14401584 [(set GR64:$dst,
14411585 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1586
1587 // Descriptor-table support instructions
1588
1589 // LLDT is not interpreted specially in 64-bit mode because there is no sign
1590 // extension.
1591 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
1592 "sldt{q}\t$dst", []>, TB;
1593 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
1594 "sldt{q}\t$dst", []>, TB;
14421595
14431596 //===----------------------------------------------------------------------===//
14441597 // Alias Instructions
15041657
15051658 let Constraints = "$val = $dst" in {
15061659 let Defs = [EFLAGS] in
1507 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1660 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
15081661 "lock\n\t"
15091662 "xadd\t$val, $ptr",
15101663 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
15111664 TB, LOCK;
15121665
1513 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1514 "xchg\t$val, $ptr",
1666 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),
1667 (ins GR64:$val,i64mem:$ptr),
1668 "xchg{q}\t{$val, $ptr|$ptr, $val}",
15151669 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1516 }
1670
1671 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1672 "xchg{q}\t{$val, $src|$src, $val}", []>;
1673 }
1674
1675 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1676 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1677 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1678 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB;
1679
1680 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1681 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1682 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1683 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB;
1684
1685 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1686 "cmpxchg16b\t$dst", []>, TB;
1687
1688 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1689 "xchg{q}\t{$src, %rax|%rax, $src}", []>;
15171690
15181691 // Optimized codegen when the non-memory output is not used.
15191692 let Defs = [EFLAGS] in {
15841757 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
15851758 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
15861759
1760 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1761 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1762 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1763 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
1764
1765 def SWPGS : I<0x01, RawFrm, (outs), (ins), "swpgs", []>, TB;
1766
1767 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
1768 "push{q}\t%fs", []>, TB;
1769 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
1770 "push{q}\t%gs", []>, TB;
1771
1772 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
1773 "pop{q}\t%fs", []>, TB;
1774 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
1775 "pop{q}\t%gs", []>, TB;
1776
1777 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1778 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
1779 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1780 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1781 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
1782 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
1783
1784 // Specialized register support
1785
1786 // no m form encodable; use SMSW16m
1787 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
1788 "smsw{q}\t$dst", []>, TB;
1789
15871790 // String manipulation instructions
15881791
15891792 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
17211924 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
17221925
17231926 // extload
1724 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1725 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1726 // partial-register updates.
1927 // When extloading from 16-bit and smaller memory locations into 64-bit
1928 // registers, use zero-extending loads so that the entire 64-bit register is
1929 // defined, avoiding partial-register updates.
17271930 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
17281931 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
17291932 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
19942197 addr:$dst),
19952198 (implicit EFLAGS)),
19962199 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1997 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2200 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst),
2201 i64immSExt32:$src2),
19982202 addr:$dst),
19992203 (implicit EFLAGS)),
20002204 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
20242228 (SUB64mr addr:$dst, GR64:$src2)>;
20252229
20262230 // Memory-Integer Subtraction with EFLAGS result
2027 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2231 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2232 i64immSExt8:$src2),
20282233 addr:$dst),
20292234 (implicit EFLAGS)),
20302235 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
2031 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2236 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst),
2237 i64immSExt32:$src2),
20322238 addr:$dst),
20332239 (implicit EFLAGS)),
20342240 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
21522358 addr:$dst),
21532359 (implicit EFLAGS)),
21542360 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2155 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2361 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst),
2362 i64immSExt32:$src2),
21562363 addr:$dst),
21572364 (implicit EFLAGS)),
21582365 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
21842391 addr:$dst),
21852392 (implicit EFLAGS)),
21862393 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2187 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2394 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst),
2395 i64immSExt32:$src2),
21882396 addr:$dst),
21892397 (implicit EFLAGS)),
21902398 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
194194 // These instructions cannot address 80-bit memory.
195195 multiclass FPBinary {
196196 // ST(0) = ST(0) + [mem]
197 def _Fp32m : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
197 def _Fp32m : FpIf32<(outs RFP32:$dst),
198 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
198199 [(set RFP32:$dst,
199200 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
200 def _Fp64m : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
201 def _Fp64m : FpIf64<(outs RFP64:$dst),
202 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
201203 [(set RFP64:$dst,
202204 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
203 def _Fp64m32: FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
205 def _Fp64m32: FpIf64<(outs RFP64:$dst),
206 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
204207 [(set RFP64:$dst,
205208 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>;
206 def _Fp80m32: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
209 def _Fp80m32: FpI_<(outs RFP80:$dst),
210 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
207211 [(set RFP80:$dst,
208212 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>;
209 def _Fp80m64: FpI_<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
213 def _Fp80m64: FpI_<(outs RFP80:$dst),
214 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
210215 [(set RFP80:$dst,
211216 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>;
212217 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
213 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
218 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))> {
219 let mayLoad = 1;
220 }
214221 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
215 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
222 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))> {
223 let mayLoad = 1;
224 }
216225 // ST(0) = ST(0) + [memint]
217 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
226 def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),
227 OneArgFPRW,
218228 [(set RFP32:$dst, (OpNode RFP32:$src1,
219229 (X86fild addr:$src2, i16)))]>;
220 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
230 def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),
231 OneArgFPRW,
221232 [(set RFP32:$dst, (OpNode RFP32:$src1,
222233 (X86fild addr:$src2, i32)))]>;
223 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
234 def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),
235 OneArgFPRW,
224236 [(set RFP64:$dst, (OpNode RFP64:$src1,
225237 (X86fild addr:$src2, i16)))]>;
226 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
238 def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),
239 OneArgFPRW,
227240 [(set RFP64:$dst, (OpNode RFP64:$src1,
228241 (X86fild addr:$src2, i32)))]>;
229 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
242 def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),
243 OneArgFPRW,
230244 [(set RFP80:$dst, (OpNode RFP80:$src1,
231245 (X86fild addr:$src2, i16)))]>;
232 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
246 def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),
247 OneArgFPRW,
233248 [(set RFP80:$dst, (OpNode RFP80:$src1,
234249 (X86fild addr:$src2, i32)))]>;
235250 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
236 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> { let mayLoad = 1; }
251 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))> {
252 let mayLoad = 1;
253 }
237254 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
238 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> { let mayLoad = 1; }
255 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))> {
256 let mayLoad = 1;
257 }
239258 }
240259
241260 defm ADD : FPBinary_rr;
278297 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
279298 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
280299
300 def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">;
301 def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">;
302
281303 // Unary operations.
282304 multiclass FPUnary opcode, string asmstring> {
283305 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
304326
305327 // Versions of FP instructions that take a single memory operand. Added for the
306328 // disassembler; remove as they are included with patterns elsewhere.
307 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom\t$src">;
308 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp\t$src">;
329 def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{l}\t$src">;
330 def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{l}\t$src">;
309331
310332 def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
311 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fstenv\t$dst">;
333 def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">;
312334
313335 def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
314336 def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
315337
316 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom\t$src">;
317 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp\t$src">;
338 def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{ll}\t$src">;
339 def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{ll}\t$src">;
318340
319341 def FISTTP32m: FPI<0xDD, MRM1m, (outs i32mem:$dst), (ins), "fisttp{l}\t$dst">;
320342 def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">;
321 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fsave\t$dst">;
322 def FSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fstsw\t$dst">;
343 def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">;
344 def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
323345
324346 def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{w}\t$src">;
325347 def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{w}\t$src">;
492514 let mayStore = 1 in {
493515 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
494516 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
495 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
517 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst),
518 "fisttp{ll}\t$dst">;
496519 }
497520
498521 // FP Stack manipulation instructions.
560583 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
561584 }
562585
586 def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
587 "fcomi\t{$reg, %st(0)|%ST(0), $reg}">, DB;
588 def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg),
589 "fcomip\t{$reg, %st(0)|%ST(0), $reg}">, DF;
590
563591 // Floating point flag ops.
564592 let Defs = [AX] in
565593 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
566 (outs), (ins), "fnstsw", []>, DF;
594 (outs), (ins), "fnstsw %ax", []>, DF;
567595
568596 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
569597 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
573601 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
574602 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
575603
604 // Register free
605
606 def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
607 "ffree\t$reg">, DD;
608
609 // Clear exceptions
610
611 def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
612
613 // Operandless floating-point instructions for the disassembler
614
615 def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
616 def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
617 def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", []>, D9;
618 def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", []>, D9;
619 def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", []>, D9;
620 def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", []>, D9;
621 def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", []>, D9;
622 def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", []>, D9;
623 def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", []>, D9;
624 def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", []>, D9;
625 def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", []>, D9;
626 def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", []>, D9;
627 def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", []>, D9;
628 def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", []>, D9;
629 def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", []>, D9;
630 def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", []>, D9;
631 def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", []>, D9;
632 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
633 def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", []>, D9;
634 def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", []>, D9;
635 def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", []>, DE;
636
637 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
638 "fxsave\t$dst", []>, TB;
639 def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src),
640 "fxrstor\t$src", []>, TB;
641
576642 //===----------------------------------------------------------------------===//
577643 // Non-Instruction Patterns
578644 //===----------------------------------------------------------------------===//
584650
585651 // Required for CALL which return f32 / f64 / f80 values.
586652 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
587 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
653 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op,
654 RFP64:$src)>;
588655 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
589 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
590 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
591 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
656 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op,
657 RFP80:$src)>;
658 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op,
659 RFP80:$src)>;
660 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op,
661 RFP80:$src)>;
592662
593663 // Floating point constant -0.0 and -1.0
594664 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
114114 let Pattern = pattern;
115115 let CodeSize = 3;
116116 }
117 class Ii8 o, Format f, dag outs, dag ins, string asm, list pattern>
117 class Ii8 o, Format f, dag outs, dag ins, string asm,
118 list pattern>
118119 : X86Inst {
119120 let Pattern = pattern;
120121 let CodeSize = 3;
121122 }
122 class Ii16 o, Format f, dag outs, dag ins, string asm, list pattern>
123 class Ii16 o, Format f, dag outs, dag ins, string asm,
124 list pattern>
123125 : X86Inst {
124126 let Pattern = pattern;
125127 let CodeSize = 3;
126128 }
127 class Ii32 o, Format f, dag outs, dag ins, string asm, list pattern>
129 class Ii32 o, Format f, dag outs, dag ins, string asm,
130 list pattern>
128131 : X86Inst {
129132 let Pattern = pattern;
130133 let CodeSize = 3;
168171
169172 class SSI o, Format F, dag outs, dag ins, string asm, list pattern>
170173 : I, XS, Requires<[HasSSE1]>;
171 class SSIi8 o, Format F, dag outs, dag ins, string asm, list pattern>
174 class SSIi8 o, Format F, dag outs, dag ins, string asm,
175 list pattern>
172176 : Ii8, XS, Requires<[HasSSE1]>;
173177 class PSI o, Format F, dag outs, dag ins, string asm, list pattern>
174178 : I, TB, Requires<[HasSSE1]>;
204208 // S3SI - SSE3 instructions with XS prefix.
205209 // S3DI - SSE3 instructions with XD prefix.
206210
207 class S3SI o, Format F, dag outs, dag ins, string asm, list pattern>
211 class S3SI o, Format F, dag outs, dag ins, string asm,
212 list pattern>
208213 : I, XS, Requires<[HasSSE3]>;
209 class S3DI o, Format F, dag outs, dag ins, string asm, list pattern>
214 class S3DI o, Format F, dag outs, dag ins, string asm,
215 list pattern>
210216 : I, XD, Requires<[HasSSE3]>;
211217 class S3I o, Format F, dag outs, dag ins, string asm, list pattern>
212218 : I, TB, OpSize, Requires<[HasSSE3]>;
254260
255261 // SS42AI = SSE 4.2 instructions with TA prefix
256262 class SS42AI o, Format F, dag outs, dag ins, string asm,
257 list pattern>
263 list pattern>
258264 : I, TA, Requires<[HasSSE42]>;
259265
260266 // X86-64 Instruction templates...
296302 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
297303 // MMXID - MMX instructions with XD prefix.
298304 // MMXIS - MMX instructions with XS prefix.
299 class MMXI o, Format F, dag outs, dag ins, string asm, list pattern>
305 class MMXI o, Format F, dag outs, dag ins, string asm,
306 list pattern>
300307 : I, TB, Requires<[HasMMX]>;
301 class MMXI64 o, Format F, dag outs, dag ins, string asm, list pattern>
308 class MMXI64 o, Format F, dag outs, dag ins, string asm,
309 list pattern>
302310 : I, TB, Requires<[HasMMX,In64BitMode]>;
303 class MMXRI o, Format F, dag outs, dag ins, string asm, list pattern>
311 class MMXRI o, Format F, dag outs, dag ins, string asm,
312 list pattern>
304313 : I, TB, REX_W, Requires<[HasMMX]>;
305 class MMX2I o, Format F, dag outs, dag ins, string asm, list pattern>
314 class MMX2I o, Format F, dag outs, dag ins, string asm,
315 list pattern>
306316 : I, TB, OpSize, Requires<[HasMMX]>;
307 class MMXIi8 o, Format F, dag outs, dag ins, string asm, list pattern>
317 class MMXIi8 o, Format F, dag outs, dag ins, string asm,
318 list pattern>
308319 : Ii8, TB, Requires<[HasMMX]>;
309 class MMXID o, Format F, dag outs, dag ins, string asm, list pattern>
320 class MMXID o, Format F, dag outs, dag ins, string asm,
321 list pattern>
310322 : Ii8, XD, Requires<[HasMMX]>;
311 class MMXIS o, Format F, dag outs, dag ins, string asm, list pattern>
323 class MMXIS o, Format F, dag outs, dag ins, string asm,
324 list pattern>
312325 : Ii8, XS, Requires<[HasMMX]>;
18791879 if (SrcReg != X86::EFLAGS)
18801880 return false;
18811881 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1882 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1882 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
18831883 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
18841884 return true;
18851885 } else if (DestRC == &X86::GR32RegClass ||
None //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
0
11 //
22 // The LLVM Compiler Infrastructure
33 //
198198 def opaque32mem : X86MemOperand<"printopaquemem">;
199199 def opaque48mem : X86MemOperand<"printopaquemem">;
200200 def opaque80mem : X86MemOperand<"printopaquemem">;
201 def opaque512mem : X86MemOperand<"printopaquemem">;
202
203 def offset8 : Operand { let PrintMethod = "print_pcrel_imm"; }
204 def offset16 : Operand { let PrintMethod = "print_pcrel_imm"; }
205 def offset32 : Operand { let PrintMethod = "print_pcrel_imm"; }
206 def offset64 : Operand { let PrintMethod = "print_pcrel_imm"; }
201207
202208 def i8mem : X86MemOperand<"printi8mem">;
203209 def i16mem : X86MemOperand<"printi16mem">;
353359 return false;
354360 }]>;
355361
356 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
362 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
363 [{
357364 LoadSDNode *LD = cast(N);
358365 if (const Value *Src = LD->getSrcValue())
359366 if (const PointerType *PT = dyn_cast(Src->getType()))
541548 // Nop
542549 let neverHasSideEffects = 1 in {
543550 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
551 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
552 "nop{w}\t$zero", []>, TB, OpSize;
544553 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
545 "nopl\t$zero", []>, TB;
554 "nop{l}\t$zero", []>, TB;
546555 }
547556
548557 // Trap
549558 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
550559 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
560 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
561 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
551562
552563 // PIC base construction. This expands to code that looks like this:
553564 // call $next_inst
711722 // Tail call stuff.
712723
713724 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
714 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
725 def TCRETURNdi : I<0, Pseudo, (outs),
726 (ins i32imm:$dst, i32imm:$offset, variable_ops),
715727 "#TC_RETURN $dst $offset",
716728 []>;
717729
718730 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
719 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
731 def TCRETURNri : I<0, Pseudo, (outs),
732 (ins GR32:$dst, i32imm:$offset, variable_ops),
720733 "#TC_RETURN $dst $offset",
721734 []>;
722735
724737 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
725738 []>;
726739 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
727 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
740 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst),
741 "jmp{l}\t{*}$dst # TAILCALL",
728742 []>;
729743 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
730744 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
736750 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
737751 def LEAVE : I<0xC9, RawFrm,
738752 (outs), (ins), "leave", []>;
753
754 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
755 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
756 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
757 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
758 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
759 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
760 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
761 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
739762
740763 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
741764 let mayLoad = 1 in {
772795 "push{l}\t$imm", []>;
773796 }
774797
775 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
776 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
777 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
778 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
798 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
799 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
800 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
801 }
802 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
803 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
804 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
805 }
779806
780807 let isTwoAddress = 1 in // GR32 = bswap GR32
781808 def BSWAP32r : I<0xC8, AddRegFrm,
917944 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
918945 "out{l}\t{%eax, $port|$port, %EAX}", []>;
919946
947 def IN8 : I<0x6C, RawFrm, (outs), (ins),
948 "ins{b}", []>;
949 def IN16 : I<0x6D, RawFrm, (outs), (ins),
950 "ins{w}", []>, OpSize;
951 def IN32 : I<0x6D, RawFrm, (outs), (ins),
952 "ins{l}", []>;
953
920954 //===----------------------------------------------------------------------===//
921955 // Move Instructions...
922956 //
949983 "mov{l}\t{$src, $dst|$dst, $src}",
950984 [(store (i32 imm:$src), addr:$dst)]>;
951985
952 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins i8imm:$src),
986 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
953987 "mov{b}\t{$src, %al|%al, $src}", []>;
954 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins i16imm:$src),
988 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
955989 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
956 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins i32imm:$src),
990 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
957991 "mov{l}\t{$src, %eax|%eax, $src}", []>;
958992
959 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs i8imm:$dst), (ins),
993 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
960994 "mov{b}\t{%al, $dst|$dst, %al}", []>;
961 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs i16imm:$dst), (ins),
995 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
962996 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
963 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs i32imm:$dst), (ins),
997 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
964998 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
965999
9661000 // Moves to and from segment registers
9721006 "mov{w}\t{$src, $dst|$dst, $src}", []>;
9731007 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
9741008 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1009
1010 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1011 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1012 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1014 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1015 "mov{l}\t{$src, $dst|$dst, $src}", []>;
9751016
9761017 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
9771018 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
10111052 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
10121053 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
10131054 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1055
1056 // Moves to and from debug registers
1057 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1059 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1061
1062 // Moves to and from control registers
1063 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1064 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1065 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1066 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
10141067
10151068 //===----------------------------------------------------------------------===//
10161069 // Fixed-Register Multiplication and Division Instructions...
10811134
10821135 // unsigned division/remainder
10831136 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1084 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1137 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
10851138 "div{b}\t$src", []>;
10861139 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1087 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1140 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
10881141 "div{w}\t$src", []>, OpSize;
10891142 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1090 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1143 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
10911144 "div{l}\t$src", []>;
10921145 let mayLoad = 1 in {
10931146 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1094 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1147 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
10951148 "div{b}\t$src", []>;
10961149 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1097 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1150 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
10981151 "div{w}\t$src", []>, OpSize;
10991152 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1100 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1153 // EDX:EAX/[mem32] = EAX,EDX
1154 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
11011155 "div{l}\t$src", []>;
11021156 }
11031157
11041158 // Signed division/remainder.
11051159 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1106 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1160 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
11071161 "idiv{b}\t$src", []>;
11081162 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1109 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1163 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
11101164 "idiv{w}\t$src", []>, OpSize;
11111165 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1112 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1166 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
11131167 "idiv{l}\t$src", []>;
11141168 let mayLoad = 1, mayLoad = 1 in {
11151169 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1116 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1170 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
11171171 "idiv{b}\t$src", []>;
11181172 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1119 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1173 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
11201174 "idiv{w}\t$src", []>, OpSize;
11211175 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1122 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
1176 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1177 // EDX:EAX/[mem32] = EAX,EDX
11231178 "idiv{l}\t$src", []>;
11241179 }
11251180
11471202 let isCommutable = 1 in {
11481203 def CMOVB16rr : I<0x42, MRMSrcReg, // if
11491204 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1150 "cmovb\t{$src2, $dst|$dst, $src2}",
1205 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
11511206 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
11521207 X86_COND_B, EFLAGS))]>,
11531208 TB, OpSize;
11541209 def CMOVB32rr : I<0x42, MRMSrcReg, // if
11551210 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1156 "cmovb\t{$src2, $dst|$dst, $src2}",
1211 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
11571212 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
11581213 X86_COND_B, EFLAGS))]>,
11591214 TB;
11601215 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
11611216 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1162 "cmovae\t{$src2, $dst|$dst, $src2}",
1217 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
11631218 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
11641219 X86_COND_AE, EFLAGS))]>,
11651220 TB, OpSize;
11661221 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
11671222 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1168 "cmovae\t{$src2, $dst|$dst, $src2}",
1223 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
11691224 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
11701225 X86_COND_AE, EFLAGS))]>,
11711226 TB;
11721227 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
11731228 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1174 "cmove\t{$src2, $dst|$dst, $src2}",
1229 "cmove{w}\t{$src2, $dst|$dst, $src2}",
11751230 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
11761231 X86_COND_E, EFLAGS))]>,
11771232 TB, OpSize;
11781233 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
11791234 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1180 "cmove\t{$src2, $dst|$dst, $src2}",
1235 "cmove{l}\t{$src2, $dst|$dst, $src2}",
11811236 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
11821237 X86_COND_E, EFLAGS))]>,
11831238 TB;
11841239 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
11851240 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1186 "cmovne\t{$src2, $dst|$dst, $src2}",
1241 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
11871242 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
11881243 X86_COND_NE, EFLAGS))]>,
11891244 TB, OpSize;
11901245 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
11911246 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1192 "cmovne\t{$src2, $dst|$dst, $src2}",
1247 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
11931248 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
11941249 X86_COND_NE, EFLAGS))]>,
11951250 TB;
11961251 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
11971252 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1198 "cmovbe\t{$src2, $dst|$dst, $src2}",
1253 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
11991254 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12001255 X86_COND_BE, EFLAGS))]>,
12011256 TB, OpSize;
12021257 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
12031258 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1204 "cmovbe\t{$src2, $dst|$dst, $src2}",
1259 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
12051260 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12061261 X86_COND_BE, EFLAGS))]>,
12071262 TB;
12081263 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
12091264 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1210 "cmova\t{$src2, $dst|$dst, $src2}",
1265 "cmova{w}\t{$src2, $dst|$dst, $src2}",
12111266 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12121267 X86_COND_A, EFLAGS))]>,
12131268 TB, OpSize;
12141269 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
12151270 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1216 "cmova\t{$src2, $dst|$dst, $src2}",
1271 "cmova{l}\t{$src2, $dst|$dst, $src2}",
12171272 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12181273 X86_COND_A, EFLAGS))]>,
12191274 TB;
12201275 def CMOVL16rr : I<0x4C, MRMSrcReg, // if
12211276 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1222 "cmovl\t{$src2, $dst|$dst, $src2}",
1277 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
12231278 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12241279 X86_COND_L, EFLAGS))]>,
12251280 TB, OpSize;
12261281 def CMOVL32rr : I<0x4C, MRMSrcReg, // if
12271282 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1228 "cmovl\t{$src2, $dst|$dst, $src2}",
1283 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
12291284 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12301285 X86_COND_L, EFLAGS))]>,
12311286 TB;
12321287 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
12331288 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1234 "cmovge\t{$src2, $dst|$dst, $src2}",
1289 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
12351290 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12361291 X86_COND_GE, EFLAGS))]>,
12371292 TB, OpSize;
12381293 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
12391294 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1240 "cmovge\t{$src2, $dst|$dst, $src2}",
1295 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
12411296 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12421297 X86_COND_GE, EFLAGS))]>,
12431298 TB;
12441299 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
12451300 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1246 "cmovle\t{$src2, $dst|$dst, $src2}",
1301 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
12471302 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12481303 X86_COND_LE, EFLAGS))]>,
12491304 TB, OpSize;
12501305 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
12511306 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1252 "cmovle\t{$src2, $dst|$dst, $src2}",
1307 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
12531308 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12541309 X86_COND_LE, EFLAGS))]>,
12551310 TB;
12561311 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
12571312 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1258 "cmovg\t{$src2, $dst|$dst, $src2}",
1313 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
12591314 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12601315 X86_COND_G, EFLAGS))]>,
12611316 TB, OpSize;
12621317 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
12631318 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1264 "cmovg\t{$src2, $dst|$dst, $src2}",
1319 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
12651320 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12661321 X86_COND_G, EFLAGS))]>,
12671322 TB;
12681323 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
12691324 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1270 "cmovs\t{$src2, $dst|$dst, $src2}",
1325 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
12711326 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12721327 X86_COND_S, EFLAGS))]>,
12731328 TB, OpSize;
12741329 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
12751330 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1276 "cmovs\t{$src2, $dst|$dst, $src2}",
1331 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
12771332 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12781333 X86_COND_S, EFLAGS))]>,
12791334 TB;
12801335 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
12811336 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1282 "cmovns\t{$src2, $dst|$dst, $src2}",
1337 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
12831338 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12841339 X86_COND_NS, EFLAGS))]>,
12851340 TB, OpSize;
12861341 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
12871342 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1288 "cmovns\t{$src2, $dst|$dst, $src2}",
1343 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
12891344 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
12901345 X86_COND_NS, EFLAGS))]>,
12911346 TB;
12921347 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
12931348 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1294 "cmovp\t{$src2, $dst|$dst, $src2}",
1349 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
12951350 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
12961351 X86_COND_P, EFLAGS))]>,
12971352 TB, OpSize;
12981353 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
12991354 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1300 "cmovp\t{$src2, $dst|$dst, $src2}",
1355 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
13011356 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
13021357 X86_COND_P, EFLAGS))]>,
13031358 TB;
13041359 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
13051360 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1306 "cmovnp\t{$src2, $dst|$dst, $src2}",
1361 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
13071362 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
13081363 X86_COND_NP, EFLAGS))]>,
13091364 TB, OpSize;
13101365 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
13111366 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1312 "cmovnp\t{$src2, $dst|$dst, $src2}",
1367 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
13131368 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
13141369 X86_COND_NP, EFLAGS))]>,
13151370 TB;
13161371 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
13171372 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1318 "cmovo\t{$src2, $dst|$dst, $src2}",
1373 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
13191374 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
13201375 X86_COND_O, EFLAGS))]>,
13211376 TB, OpSize;
13221377 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
13231378 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1324 "cmovo\t{$src2, $dst|$dst, $src2}",
1379 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
13251380 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
13261381 X86_COND_O, EFLAGS))]>,
13271382 TB;
13281383 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
13291384 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1330 "cmovno\t{$src2, $dst|$dst, $src2}",
1385 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
13311386 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
13321387 X86_COND_NO, EFLAGS))]>,
13331388 TB, OpSize;
13341389 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
13351390 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1336 "cmovno\t{$src2, $dst|$dst, $src2}",
1391 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
13371392 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
13381393 X86_COND_NO, EFLAGS))]>,
13391394 TB;
13411396
13421397 def CMOVB16rm : I<0x42, MRMSrcMem, // if
13431398 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1344 "cmovb\t{$src2, $dst|$dst, $src2}",
1399 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
13451400 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
13461401 X86_COND_B, EFLAGS))]>,
13471402 TB, OpSize;
13481403 def CMOVB32rm : I<0x42, MRMSrcMem, // if
13491404 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1350 "cmovb\t{$src2, $dst|$dst, $src2}",
1405 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
13511406 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
13521407 X86_COND_B, EFLAGS))]>,
13531408 TB;
13541409 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
13551410 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1356 "cmovae\t{$src2, $dst|$dst, $src2}",
1411 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
13571412 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
13581413 X86_COND_AE, EFLAGS))]>,
13591414 TB, OpSize;
13601415 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
13611416 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1362 "cmovae\t{$src2, $dst|$dst, $src2}",
1417 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
13631418 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
13641419 X86_COND_AE, EFLAGS))]>,
13651420 TB;
13661421 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
13671422 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1368 "cmove\t{$src2, $dst|$dst, $src2}",
1423 "cmove{w}\t{$src2, $dst|$dst, $src2}",
13691424 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
13701425 X86_COND_E, EFLAGS))]>,
13711426 TB, OpSize;
13721427 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
13731428 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1374 "cmove\t{$src2, $dst|$dst, $src2}",
1429 "cmove{l}\t{$src2, $dst|$dst, $src2}",
13751430 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
13761431 X86_COND_E, EFLAGS))]>,
13771432 TB;
13781433 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
13791434 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1380 "cmovne\t{$src2, $dst|$dst, $src2}",
1435 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
13811436 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
13821437 X86_COND_NE, EFLAGS))]>,
13831438 TB, OpSize;
13841439 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
13851440 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1386 "cmovne\t{$src2, $dst|$dst, $src2}",
1441 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
13871442 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
13881443 X86_COND_NE, EFLAGS))]>,
13891444 TB;
13901445 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
13911446 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1392 "cmovbe\t{$src2, $dst|$dst, $src2}",
1447 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
13931448 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
13941449 X86_COND_BE, EFLAGS))]>,
13951450 TB, OpSize;
13961451 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
13971452 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1398 "cmovbe\t{$src2, $dst|$dst, $src2}",
1453 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
13991454 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14001455 X86_COND_BE, EFLAGS))]>,
14011456 TB;
14021457 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
14031458 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1404 "cmova\t{$src2, $dst|$dst, $src2}",
1459 "cmova{w}\t{$src2, $dst|$dst, $src2}",
14051460 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14061461 X86_COND_A, EFLAGS))]>,
14071462 TB, OpSize;
14081463 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
14091464 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1410 "cmova\t{$src2, $dst|$dst, $src2}",
1465 "cmova{l}\t{$src2, $dst|$dst, $src2}",
14111466 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14121467 X86_COND_A, EFLAGS))]>,
14131468 TB;
14141469 def CMOVL16rm : I<0x4C, MRMSrcMem, // if
14151470 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1416 "cmovl\t{$src2, $dst|$dst, $src2}",
1471 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
14171472 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14181473 X86_COND_L, EFLAGS))]>,
14191474 TB, OpSize;
14201475 def CMOVL32rm : I<0x4C, MRMSrcMem, // if
14211476 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1422 "cmovl\t{$src2, $dst|$dst, $src2}",
1477 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
14231478 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14241479 X86_COND_L, EFLAGS))]>,
14251480 TB;
14261481 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
14271482 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1428 "cmovge\t{$src2, $dst|$dst, $src2}",
1483 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
14291484 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14301485 X86_COND_GE, EFLAGS))]>,
14311486 TB, OpSize;
14321487 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
14331488 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1434 "cmovge\t{$src2, $dst|$dst, $src2}",
1489 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
14351490 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14361491 X86_COND_GE, EFLAGS))]>,
14371492 TB;
14381493 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
14391494 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1440 "cmovle\t{$src2, $dst|$dst, $src2}",
1495 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
14411496 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14421497 X86_COND_LE, EFLAGS))]>,
14431498 TB, OpSize;
14441499 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
14451500 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1446 "cmovle\t{$src2, $dst|$dst, $src2}",
1501 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
14471502 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14481503 X86_COND_LE, EFLAGS))]>,
14491504 TB;
14501505 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
14511506 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1452 "cmovg\t{$src2, $dst|$dst, $src2}",
1507 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
14531508 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14541509 X86_COND_G, EFLAGS))]>,
14551510 TB, OpSize;
14561511 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
14571512 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1458 "cmovg\t{$src2, $dst|$dst, $src2}",
1513 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
14591514 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14601515 X86_COND_G, EFLAGS))]>,
14611516 TB;
14621517 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
14631518 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1464 "cmovs\t{$src2, $dst|$dst, $src2}",
1519 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
14651520 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14661521 X86_COND_S, EFLAGS))]>,
14671522 TB, OpSize;
14681523 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
14691524 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1470 "cmovs\t{$src2, $dst|$dst, $src2}",
1525 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
14711526 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14721527 X86_COND_S, EFLAGS))]>,
14731528 TB;
14741529 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
14751530 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1476 "cmovns\t{$src2, $dst|$dst, $src2}",
1531 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
14771532 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14781533 X86_COND_NS, EFLAGS))]>,
14791534 TB, OpSize;
14801535 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
14811536 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1482 "cmovns\t{$src2, $dst|$dst, $src2}",
1537 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
14831538 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14841539 X86_COND_NS, EFLAGS))]>,
14851540 TB;
14861541 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
14871542 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1488 "cmovp\t{$src2, $dst|$dst, $src2}",
1543 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
14891544 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
14901545 X86_COND_P, EFLAGS))]>,
14911546 TB, OpSize;
14921547 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
14931548 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1494 "cmovp\t{$src2, $dst|$dst, $src2}",
1549 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
14951550 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
14961551 X86_COND_P, EFLAGS))]>,
14971552 TB;
14981553 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
14991554 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1500 "cmovnp\t{$src2, $dst|$dst, $src2}",
1555 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
15011556 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
15021557 X86_COND_NP, EFLAGS))]>,
15031558 TB, OpSize;
15041559 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
15051560 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1506 "cmovnp\t{$src2, $dst|$dst, $src2}",
1561 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
15071562 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
15081563 X86_COND_NP, EFLAGS))]>,
15091564 TB;
15101565 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
15111566 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1512 "cmovo\t{$src2, $dst|$dst, $src2}",
1567 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
15131568 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
15141569 X86_COND_O, EFLAGS))]>,
15151570 TB, OpSize;
15161571 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
15171572 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1518 "cmovo\t{$src2, $dst|$dst, $src2}",
1573 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
15191574 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
15201575 X86_COND_O, EFLAGS))]>,
15211576 TB;
15221577 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
15231578 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1524 "cmovno\t{$src2, $dst|$dst, $src2}",
1579 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
15251580 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
15261581 X86_COND_NO, EFLAGS))]>,
15271582 TB, OpSize;
15281583 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
15291584 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1530 "cmovno\t{$src2, $dst|$dst, $src2}",
1585 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
15311586 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
15321587 X86_COND_NO, EFLAGS))]>,
15331588 TB;
15851640 [(set GR8:$dst, (add GR8:$src, 1)),
15861641 (implicit EFLAGS)]>;
15871642 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1588 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1643 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1644 "inc{w}\t$dst",
15891645 [(set GR16:$dst, (add GR16:$src, 1)),
15901646 (implicit EFLAGS)]>,
15911647 OpSize, Requires<[In32BitMode]>;
1592 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1648 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1649 "inc{l}\t$dst",
15931650 [(set GR32:$dst, (add GR32:$src, 1)),
15941651 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
15951652 }
16121669 [(set GR8:$dst, (add GR8:$src, -1)),
16131670 (implicit EFLAGS)]>;
16141671 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1615 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1672 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1673 "dec{w}\t$dst",
16161674 [(set GR16:$dst, (add GR16:$src, -1)),
16171675 (implicit EFLAGS)]>,
16181676 OpSize, Requires<[In32BitMode]>;
1619 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1677 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1678 "dec{l}\t$dst",
16201679 [(set GR32:$dst, (add GR32:$src, -1)),
16211680 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
16221681 }
16551714 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
16561715 (implicit EFLAGS)]>;
16571716 }
1717
1718 // AND instructions with the destination register in REG and the source register
1719 // in R/M. Included for the disassembler.
1720 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1721 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1722 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1723 (ins GR16:$src1, GR16:$src2),
1724 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1725 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1726 (ins GR32:$src1, GR32:$src2),
1727 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
16581728
16591729 def AND8rm : I<0x22, MRMSrcMem,
16601730 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
17551825
17561826
17571827 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1758 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1828 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1829 (ins GR8 :$src1, GR8 :$src2),
17591830 "or{b}\t{$src2, $dst|$dst, $src2}",
17601831 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
17611832 (implicit EFLAGS)]>;
1762 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1833 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1834 (ins GR16:$src1, GR16:$src2),
17631835 "or{w}\t{$src2, $dst|$dst, $src2}",
17641836 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
17651837 (implicit EFLAGS)]>, OpSize;
1766 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1838 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1839 (ins GR32:$src1, GR32:$src2),
17671840 "or{l}\t{$src2, $dst|$dst, $src2}",
17681841 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
17691842 (implicit EFLAGS)]>;
17701843 }
1771 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1844
1845 // OR instructions with the destination register in REG and the source register
1846 // in R/M. Included for the disassembler.
1847 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1848 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1849 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1850 (ins GR16:$src1, GR16:$src2),
1851 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1852 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1853 (ins GR32:$src1, GR32:$src2),
1854 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1855
1856 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1857 (ins GR8 :$src1, i8mem :$src2),
17721858 "or{b}\t{$src2, $dst|$dst, $src2}",
17731859 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
17741860 (implicit EFLAGS)]>;
1775 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1861 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1862 (ins GR16:$src1, i16mem:$src2),
17761863 "or{w}\t{$src2, $dst|$dst, $src2}",
17771864 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
17781865 (implicit EFLAGS)]>, OpSize;
1779 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1866 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1867 (ins GR32:$src1, i32mem:$src2),
17801868 "or{l}\t{$src2, $dst|$dst, $src2}",
17811869 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
17821870 (implicit EFLAGS)]>;
17831871
1784 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1872 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1873 (ins GR8 :$src1, i8imm:$src2),
17851874 "or{b}\t{$src2, $dst|$dst, $src2}",
17861875 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
17871876 (implicit EFLAGS)]>;
1788 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1877 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1878 (ins GR16:$src1, i16imm:$src2),
17891879 "or{w}\t{$src2, $dst|$dst, $src2}",
17901880 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
17911881 (implicit EFLAGS)]>, OpSize;
1792 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1882 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1883 (ins GR32:$src1, i32imm:$src2),
17931884 "or{l}\t{$src2, $dst|$dst, $src2}",
17941885 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
17951886 (implicit EFLAGS)]>;
17961887
1797 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1888 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1889 (ins GR16:$src1, i16i8imm:$src2),
17981890 "or{w}\t{$src2, $dst|$dst, $src2}",
17991891 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
18001892 (implicit EFLAGS)]>, OpSize;
1801 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1893 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1894 (ins GR32:$src1, i32i8imm:$src2),
18021895 "or{l}\t{$src2, $dst|$dst, $src2}",
18031896 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
18041897 (implicit EFLAGS)]>;
18641957 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
18651958 (implicit EFLAGS)]>;
18661959 } // isCommutable = 1
1960
1961 // XOR instructions with the destination register in REG and the source register
1962 // in R/M. Included for the disassembler.
1963 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1964 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1965 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1966 (ins GR16:$src1, GR16:$src2),
1967 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1968 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1969 (ins GR32:$src1, GR32:$src2),
1970 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
18671971
18681972 def XOR8rm : I<0x32, MRMSrcMem ,
18691973 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
22042308 }
22052309 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
22062310 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2207 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
2311 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst),
2312 (ins i16mem:$src, i8imm:$cnt),
22082313 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
22092314
22102315 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
22192324 }
22202325 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
22212326 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2222 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
2327 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst),
2328 (ins i32mem:$src, i8imm:$cnt),
22232329 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
22242330
22252331 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
22492355 }
22502356 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
22512357 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2252 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src, i8imm:$cnt),
2358 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst),
2359 (ins i16mem:$src, i8imm:$cnt),
22532360 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
22542361
22552362 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
22642371 }
22652372 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
22662373 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2267 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src, i8imm:$cnt),
2374 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst),
2375 (ins i32mem:$src, i8imm:$cnt),
22682376 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
22692377
22702378 // FIXME: provide shorter instructions when imm8 == 1
22852393 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
22862394 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
22872395 "rol{w}\t{$src2, $dst|$dst, $src2}",
2288 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2396 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2397 OpSize;
22892398 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
22902399 "rol{l}\t{$src2, $dst|$dst, $src2}",
22912400 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
23542463 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
23552464 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
23562465 "ror{w}\t{$src2, $dst|$dst, $src2}",
2357 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2466 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2467 OpSize;
23582468 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
23592469 "ror{l}\t{$src2, $dst|$dst, $src2}",
23602470 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
24102520
24112521 // Double shift instructions (generalizations of rotate)
24122522 let Uses = [CL] in {
2413 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2523 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2524 (ins GR32:$src1, GR32:$src2),
24142525 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
24152526 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2416 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2527 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2528 (ins GR32:$src1, GR32:$src2),
24172529 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
24182530 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2419 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2531 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2532 (ins GR16:$src1, GR16:$src2),
24202533 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
24212534 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
24222535 TB, OpSize;
2423 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2536 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2537 (ins GR16:$src1, GR16:$src2),
24242538 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
24252539 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
24262540 TB, OpSize;
24282542
24292543 let isCommutable = 1 in { // These instructions commute to each other.
24302544 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2431 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2545 (outs GR32:$dst),
2546 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
24322547 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
24332548 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
24342549 (i8 imm:$src3)))]>,
24352550 TB;
24362551 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2437 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2552 (outs GR32:$dst),
2553 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
24382554 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
24392555 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
24402556 (i8 imm:$src3)))]>,
24412557 TB;
24422558 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2443 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2559 (outs GR16:$dst),
2560 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
24442561 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
24452562 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
24462563 (i8 imm:$src3)))]>,
24472564 TB, OpSize;
24482565 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2449 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2566 (outs GR16:$dst),
2567 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
24502568 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
24512569 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
24522570 (i8 imm:$src3)))]>,
26442762 "adc{l}\t{$src2, $dst|$dst, $src2}",
26452763 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
26462764 }
2765
2766 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2767 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2768 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2769 (ins GR16:$src1, GR16:$src2),
2770 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2771 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2772 (ins GR32:$src1, GR32:$src2),
2773 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2774
26472775 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
26482776 (ins GR8:$src1, i8mem:$src2),
26492777 "adc{b}\t{$src2, $dst|$dst, $src2}",
27292857 "sub{l}\t{$src2, $dst|$dst, $src2}",
27302858 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
27312859 (implicit EFLAGS)]>;
2860
2861 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2862 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2863 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2864 (ins GR16:$src1, GR16:$src2),
2865 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2866 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2867 (ins GR32:$src1, GR32:$src2),
2868 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
27322869
27332870 // Register-Memory Subtraction
27342871 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
28713008 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
28723009 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
28733010 }
3011
3012 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3013 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3014 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3015 (ins GR16:$src1, GR16:$src2),
3016 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3017 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3018 (ins GR32:$src1, GR32:$src2),
3019 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3020
28743021 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
28753022 "sbb{b}\t{$src2, $dst|$dst, $src2}",
28763023 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
29253072 "imul{w}\t{$src2, $dst|$dst, $src2}",
29263073 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
29273074 (implicit EFLAGS)]>, TB, OpSize;
2928 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
3075 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3076 (ins GR32:$src1, i32mem:$src2),
29293077 "imul{l}\t{$src2, $dst|$dst, $src2}",
29303078 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
29313079 (implicit EFLAGS)]>, TB;
29573105 (implicit EFLAGS)]>;
29583106
29593107 // Memory-Integer Signed Integer Multiply
2960 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3108 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
29613109 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
29623110 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
29633111 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
29643112 (implicit EFLAGS)]>, OpSize;
2965 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3113 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
29663114 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
29673115 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
29683116 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
33733521
33743522 // Unlike with the register+register form, the memory+register form of the
33753523 // bt instruction does not ignore the high bits of the index. From ISel's
3376 // perspective, this is pretty bizarre. Disable these instructions for now.
3377 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3378 // "bt{w}\t{$src2, $src1|$src1, $src2}",
3524 // perspective, this is pretty bizarre. Make these instructions disassembly
3525 // only for now.
3526
3527 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3528 "bt{w}\t{$src2, $src1|$src1, $src2}",
33793529 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3380 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
3381 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3382 // "bt{l}\t{$src2, $src1|$src1, $src2}",
3530 // (implicit EFLAGS)]
3531 []
3532 >, OpSize, TB, Requires<[FastBTMem]>;
3533 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3534 "bt{l}\t{$src2, $src1|$src1, $src2}",
33833535 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3384 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
3536 // (implicit EFLAGS)]
3537 []
3538 >, TB, Requires<[FastBTMem]>;
33853539
33863540 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
33873541 "bt{w}\t{$src2, $src1|$src1, $src2}",
34023556 "bt{l}\t{$src2, $src1|$src1, $src2}",
34033557 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
34043558 (implicit EFLAGS)]>, TB;
3559
3560 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3561 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3562 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3563 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3564 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3565 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3566 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3567 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3568 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3569 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3570 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3571 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3572 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3573 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3574 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3575 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3576
3577 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3578 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3579 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3580 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3581 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3582 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3583 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3584 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3585 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3586 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3587 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3588 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3589 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3590 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3591 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3592 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3593
3594 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3595 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3596 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3597 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3598 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3599 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3600 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3601 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3602 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3603 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3604 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3605 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3606 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3607 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3608 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3609 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
34053610 } // Defs = [EFLAGS]
34063611
34073612 // Sign/Zero extenders
34083613 // Use movsbl intead of movsbw; we don't care about the high 16 bits
34093614 // of the register here. This has a smaller encoding and avoids a
3410 // partial-register update.
3615 // partial-register update. Actual movsbw included for the disassembler.
3616 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3617 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3618 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3619 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
34113620 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
34123621 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
34133622 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
34273636
34283637 // Use movzbl intead of movzbw; we don't care about the high 16 bits
34293638 // of the register here. This has a smaller encoding and avoids a
3430 // partial-register update.
3639 // partial-register update. Actual movzbw included for the disassembler.
3640 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3641 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3642 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3643 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
34313644 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
34323645 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
34333646 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
35403753 // Atomic swap. These are just normal xchg instructions. But since a memory
35413754 // operand is referenced, the atomicity is ensured.
35423755 let Constraints = "$val = $dst" in {
3543 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3756 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3757 (ins GR32:$val, i32mem:$ptr),
35443758 "xchg{l}\t{$val, $ptr|$ptr, $val}",
35453759 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3546 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3760 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3761 (ins GR16:$val, i16mem:$ptr),
35473762 "xchg{w}\t{$val, $ptr|$ptr, $val}",
35483763 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
35493764 OpSize;
3550 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3765 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
35513766 "xchg{b}\t{$val, $ptr|$ptr, $val}",
35523767 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3553 }
3768
3769 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3770 "xchg{l}\t{$val, $src|$src, $val}", []>;
3771 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3772 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3773 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3774 "xchg{b}\t{$val, $src|$src, $val}", []>;
3775 }
3776
3777 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3778 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3779 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3780 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
35543781
35553782 // Atomic compare and swap.
35563783 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
35813808
35823809 // Atomic exchange and add
35833810 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3584 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3811 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
35853812 "lock\n\t"
35863813 "xadd{l}\t{$val, $ptr|$ptr, $val}",
35873814 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
35883815 TB, LOCK;
3589 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3816 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
35903817 "lock\n\t"
35913818 "xadd{w}\t{$val, $ptr|$ptr, $val}",
35923819 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
35933820 TB, OpSize, LOCK;
3594 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3821 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
35953822 "lock\n\t"
35963823 "xadd{b}\t{$val, $ptr|$ptr, $val}",
35973824 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
35983825 TB, LOCK;
35993826 }
3827
3828 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3829 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3830 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3831 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3832 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3833 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3834
3835 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3836 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3837 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3838 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3839 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3840 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3841
3842 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3843 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3844 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3845 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3846 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3847 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3848
3849 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3850 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3851 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3852 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3853 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3854 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3855
3856 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3857 "cmpxchg8b\t$dst", []>, TB;
36003858
36013859 // Optimized codegen when the non-memory output is not used.
36023860 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
36543912 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
36553913 "lock\n\t"
36563914 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3657 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3915 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
36583916 "lock\n\t"
36593917 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
36603918 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
37794037 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
37804038 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
37814039 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4040
4041 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4042 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4043 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4044 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4045 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4046 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4047 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4048 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4049
4050 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4051
4052 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4053 "str{w}\t{$dst}", []>, TB;
4054 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4055 "str{w}\t{$dst}", []>, TB;
4056 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4057 "ltr{w}\t{$src}", []>, TB;
4058 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4059 "ltr{w}\t{$src}", []>, TB;
4060
4061 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4062 "push{w}\t%fs", []>, OpSize, TB;
4063 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4064 "push{l}\t%fs", []>, TB;
4065 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4066 "push{w}\t%gs", []>, OpSize, TB;
4067 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4068 "push{l}\t%gs", []>, TB;
4069
4070 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4071 "pop{w}\t%fs", []>, OpSize, TB;
4072 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4073 "pop{l}\t%fs", []>, TB;
4074 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4075 "pop{w}\t%gs", []>, OpSize, TB;
4076 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4077 "pop{l}\t%gs", []>, TB;
4078
4079 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4080 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4081 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4082 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4083 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4084 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4085 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4086 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4087 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4088 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4089 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4090 "les{l}\t{$src, $dst|$dst, $src}", []>;
4091 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4092 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4093 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4094 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4095 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4096 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4097 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4098 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4099
4100 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4101 "verr\t$seg", []>, TB;
4102 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4103 "verr\t$seg", []>, TB;
4104 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4105 "verw\t$seg", []>, TB;
4106 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4107 "verw\t$seg", []>, TB;
4108
4109 // Descriptor-table support instructions
4110
4111 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4112 "sgdt\t$dst", []>, TB;
4113 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4114 "sidt\t$dst", []>, TB;
4115 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4116 "sldt{w}\t$dst", []>, TB;
4117 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4118 "sldt{w}\t$dst", []>, TB;
4119 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4120 "lgdt\t$src", []>, TB;
4121 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4122 "lidt\t$src", []>, TB;
4123 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4124 "lldt{w}\t$src", []>, TB;
4125 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4126 "lldt{w}\t$src", []>, TB;
37824127
37834128 // String manipulation instructions
37844129
37854130 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
37864131 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
3787 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>;
4132 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4133
4134 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4135 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4136 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4137
4138 // CPU flow control instructions
4139
4140 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4141 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4142
4143 // FPU control instructions
4144
4145 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4146
4147 // Flag instructions
4148
4149 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4150 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4151 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4152 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4153 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4154 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4155 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4156
4157 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4158
4159 // Table lookup instructions
4160
4161 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4162
4163 // Specialized register support
4164
4165 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4166 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4167 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4168
4169 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4170 "smsw{w}\t$dst", []>, OpSize, TB;
4171 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4172 "smsw{l}\t$dst", []>, TB;
4173 // For memory operands, there is only a 16-bit form
4174 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4175 "smsw{w}\t$dst", []>, TB;
4176
4177 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4178 "lmsw{w}\t$src", []>, TB;
4179 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4180 "lmsw{w}\t$src", []>, TB;
4181
4182 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4183
4184 // Cache instructions
4185
4186 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4187 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4188
4189 // VMX instructions
4190
4191 // 66 0F 38 80
4192 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4193 // 66 0F 38 81
4194 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4195 // 0F 01 C1
4196 def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB;
4197 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4198 "vmclear\t$vmcs", []>, OpSize, TB;
4199 // 0F 01 C2
4200 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4201 // 0F 01 C3
4202 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4203 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4204 "vmptrld\t$vmcs", []>, TB;
4205 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4206 "vmptrst\t$vmcs", []>, TB;
4207 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4208 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4209 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4210 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4211 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4212 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4213 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4214 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4215 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4216 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4217 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4218 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4219 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4220 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4221 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4222 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4223 // 0F 01 C4
4224 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4225 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4226 "vmxon\t{$vmxon}", []>, XD;
37884227
37894228 //===----------------------------------------------------------------------===//
37904229 // Non-Instruction Patterns
40304469 x86_subreg_16bit)>,
40314470 Requires<[In32BitMode]>;
40324471 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4033 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4472 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4473 GR16_ABCD)),
40344474 x86_subreg_8bit_hi))>,
40354475 Requires<[In32BitMode]>;
40364476 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4037 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4477 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4478 GR16_ABCD)),
40384479 x86_subreg_8bit_hi))>,
40394480 Requires<[In32BitMode]>;
40404481 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4041 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4482 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4483 GR32_ABCD)),
40424484 x86_subreg_8bit_hi))>,
40434485 Requires<[In32BitMode]>;
40444486
7171 multiclass MMXI_binop_rm opc, string OpcodeStr, SDNode OpNode,
7272 ValueType OpVT, bit Commutable = 0> {
7373 def rr : MMXI
74 (ins VR64:$src1, VR64:$src2),
74 (ins VR64:$src1, VR64:$src2),
7575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7676 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
7777 let isCommutable = Commutable;
7878 }
7979 def rm : MMXI
80 (ins VR64:$src1, i64mem:$src2),
80 (ins VR64:$src1, i64mem:$src2),
8181 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8282 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
8383 (bitconvert
8787 multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
8888 bit Commutable = 0> {
8989 def rr : MMXI
90 (ins VR64:$src1, VR64:$src2),
90 (ins VR64:$src1, VR64:$src2),
9191 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
9292 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
9393 let isCommutable = Commutable;
9494 }
9595 def rm : MMXI
96 (ins VR64:$src1, i64mem:$src2),
96 (ins VR64:$src1, i64mem:$src2),
9797 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
9898 [(set VR64:$dst, (IntId VR64:$src1,
9999 (bitconvert (load_mmx addr:$src2))))]>;
143143 //===----------------------------------------------------------------------===//
144144
145145 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
146 [(int_x86_mmx_emms)]>;
146 [(int_x86_mmx_emms)]>;
147147 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms",
148 [(int_x86_mmx_femms)]>;
148 [(int_x86_mmx_femms)]>;
149149
150150 //===----------------------------------------------------------------------===//
151151 // MMX Scalar Instructions
154154 // Data Transfer Instructions
155155 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
156156 "movd\t{$src, $dst|$dst, $src}",
157 [(set VR64:$dst,
158 (v2i32 (scalar_to_vector GR32:$src)))]>;
157 [(set VR64:$dst,
158 (v2i32 (scalar_to_vector GR32:$src)))]>;
159159 let canFoldAsLoad = 1, isReMaterializable = 1 in
160160 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
161161 "movd\t{$src, $dst|$dst, $src}",
162162 [(set VR64:$dst,
163 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
163 (v2i32 (scalar_to_vector (loadi32 addr:$src))))]>;
164164 let mayStore = 1 in
165165 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
166166 "movd\t{$src, $dst|$dst, $src}", []>;
167 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
168 "movd\t{$src, $dst|$dst, $src}", []>;
169 def MMX_MOVQ64gmr : MMXRI<0x7E, MRMDestMem, (outs),
170 (ins i64mem:$dst, VR64:$src),
171 "movq\t{$src, $dst|$dst, $src}", []>;
167172
168173 let neverHasSideEffects = 1 in
169174 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
180185 def MMX_MOVD64rrv164 : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
181186 "movd\t{$src, $dst|$dst, $src}",
182187 [(set VR64:$dst,
183 (v1i64 (scalar_to_vector GR64:$src)))]>;
188 (v1i64 (scalar_to_vector GR64:$src)))]>;
184189
185190 let neverHasSideEffects = 1 in
186191 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
222227 (v2i32 (X86vzmovl (v2i32 (scalar_to_vector GR32:$src)))))]>;
223228 let AddedComplexity = 20 in
224229 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
225 (ins i32mem:$src),
230 (ins i32mem:$src),
226231 "movd\t{$src, $dst|$dst, $src}",
227232 [(set VR64:$dst,
228233 (v2i32 (X86vzmovl (v2i32
431436 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
432437 let mayLoad = 1 in
433438 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst),
434 (ins f128mem:$src),
439 (ins f128mem:$src),
435440 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
436441
437442 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
438443 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
439444 let mayLoad = 1 in
440445 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst),
441 (ins i64mem:$src),
446 (ins i64mem:$src),
442447 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
443448
444449 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
445450 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
446451 let mayLoad = 1 in
447452 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst),
448 (ins i64mem:$src),
453 (ins i64mem:$src),
449454 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
450455
451456 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
458463 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
459464 let mayLoad = 1 in
460465 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst),
461 (ins f128mem:$src),
466 (ins f128mem:$src),
462467 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
463468
464469 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
480485 (iPTR imm:$src2)))]>;
481486 let Constraints = "$src1 = $dst" in {
482487 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
483 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2,
484 i16i8imm:$src3),
488 (outs VR64:$dst),
489 (ins VR64:$src1, GR32:$src2,i16i8imm:$src3),
485490 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
486491 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
487492 GR32:$src2,(iPTR imm:$src3))))]>;
488493 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
489 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2,
490 i16i8imm:$src3),
494 (outs VR64:$dst),
495 (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
491496 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
492497 [(set VR64:$dst,
493498 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
6969 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
7070
7171 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
72 SDTCisVT<1, v4f32>]>;
72 SDTCisVT<1, v4f32>]>;
7373 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
7474
7575 //===----------------------------------------------------------------------===//
115115 return cast(N)->getAlignment() >= 16;
116116 }]>;
117117
118 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
119 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
120 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
121 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
122 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
123 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
118 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
119 (f32 (alignedload node:$ptr))>;
120 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
121 (f64 (alignedload node:$ptr))>;
122 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
123 (v4f32 (alignedload node:$ptr))>;
124 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
125 (v2f64 (alignedload node:$ptr))>;
126 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
127 (v4i32 (alignedload node:$ptr))>;
128 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
129 (v2i64 (alignedload node:$ptr))>;
124130
125131 // Like 'load', but uses special alignment checks suitable for use in
126132 // memory operands in most SSE instructions, which are required to
362368 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
363369
364370 // Match intrinsics which expect XMM operand(s).
371 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
372 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
373 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
374 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
375
365376 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
366377 "cvtss2si\t{$src, $dst|$dst, $src}",
367378 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
440451 "ucomiss\t{$src2, $src1|$src1, $src2}",
441452 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
442453 (implicit EFLAGS)]>;
454
455 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
456 "comiss\t{$src2, $src1|$src1, $src2}", []>;
457 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
458 "comiss\t{$src2, $src1|$src1, $src2}", []>;
459
443460 } // Defs = [EFLAGS]
444461
445462 // Aliases to match intrinsics which expect XMM operand(s).
446463 let Constraints = "$src1 = $dst" in {
447464 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
448 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
449 SSECC:$cc),
465 (outs VR128:$dst),
466 (ins VR128:$src1, VR128:$src, SSECC:$cc),
450467 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
451 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
452 VR128:$src, imm:$cc))]>;
468 [(set VR128:$dst, (int_x86_sse_cmp_ss
469 VR128:$src1,
470 VR128:$src, imm:$cc))]>;
453471 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
454 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src,
455 SSECC:$cc),
472 (outs VR128:$dst),
473 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
456474 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
457475 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
458476 (load addr:$src), imm:$cc))]>;
12041222 // Aliases to match intrinsics which expect XMM operand(s).
12051223 let Constraints = "$src1 = $dst" in {
12061224 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1207 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
1208 SSECC:$cc),
1225 (outs VR128:$dst),
1226 (ins VR128:$src1, VR128:$src, SSECC:$cc),
12091227 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
12101228 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
12111229 VR128:$src, imm:$cc))]>;
12121230 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1213 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src,
1214 SSECC:$cc),
1231 (outs VR128:$dst),
1232 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
12151233 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
12161234 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
12171235 (load addr:$src), imm:$cc))]>;
15411559 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
15421560 (memop addr:$src)))]>;
15431561 // SSE2 packed instructions with XS prefix
1562 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1563 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1564 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1565 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1566
15441567 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
15451568 "cvttps2dq\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1569 [(set VR128:$dst,
1570 (int_x86_sse2_cvttps2dq VR128:$src))]>,
15471571 XS, Requires<[HasSSE2]>;
15481572 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
15491573 "cvttps2dq\t{$src, $dst|$dst, $src}",
15711595 (memop addr:$src)))]>;
15721596
15731597 // SSE2 instructions without OpSize prefix
1598 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1599 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1600 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1601 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1602
15741603 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
15751604 "cvtps2pd\t{$src, $dst|$dst, $src}",
15761605 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
15801609 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
15811610 (load addr:$src)))]>,
15821611 TB, Requires<[HasSSE2]>;
1612
1613 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1614 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1615 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1616 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1617
15831618
15841619 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
15851620 "cvtpd2ps\t{$src, $dst|$dst, $src}",
18551890
18561891 multiclass PDI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
18571892 bit Commutable = 0> {
1858 def rr : PDI(ins VR128:$src1, VR128:$src2),
1893 def rr : PDI
1894 (ins VR128:$src1, VR128:$src2),
18591895 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
18601896 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
18611897 let isCommutable = Commutable;
18621898 }
1863 def rm : PDI(ins VR128:$src1, i128mem:$src2),
1899 def rm : PDI
1900 (ins VR128:$src1, i128mem:$src2),
18641901 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
18651902 [(set VR128:$dst, (IntId VR128:$src1,
1866 (bitconvert (memopv2i64 addr:$src2))))]>;
1903 (bitconvert (memopv2i64
1904 addr:$src2))))]>;
18671905 }
18681906
18691907 multiclass PDI_binop_rmi_int opc, bits<8> opc2, Format ImmForm,
18701908 string OpcodeStr,
18711909 Intrinsic IntId, Intrinsic IntId2> {
1872 def rr : PDI
1873 VR128:$src2),
1910 def rr : PDI
1911 (ins VR128:$src1, VR128:$src2),
18741912 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
18751913 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1876 def rm : PDI
1877 i128mem:$src2),
1914 def rm : PDI),
1915 (ins VR128:$src1, i128mem:$src2),
18781916 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
18791917 [(set VR128:$dst, (IntId VR128:$src1,
18801918 (bitconvert (memopv2i64 addr:$src2))))]>;
1881