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Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323922 91177308-0d34-0410-b5e6-96231b3b80d8 Puyan Lotfi 2 years ago
970 changed file(s) with 34583 addition(s) and 34574 deletion(s). Raw diff Collapse all Expand all
409409 return isIdentifierChar(C) && C != '.';
410410 }
411411
412 static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
413 if (C.peek() != '%')
414 return None;
415 if (isdigit(C.peek(1)))
416 return lexVirtualRegister(C, Token);
417 auto Range = C;
418 C.advance(); // Skip '%'
412 static Cursor maybeLexRegister(Cursor C, MIToken &Token,
413 ErrorCallbackType ErrorCallback) {
414 if (C.peek() != '%' && C.peek() != '$')
415 return None;
416
417 if (C.peek() == '%') {
418 if (isdigit(C.peek(1)))
419 return lexVirtualRegister(C, Token);
420
421 // ErrorCallback(Token.location(), "Named vregs are not yet supported.");
422 return None;
423 }
424
425 assert(C.peek() == '$');
426 auto Range = C;
427 C.advance(); // Skip '$'
419428 while (isRegisterChar(C.peek()))
420429 C.advance();
421430 Token.reset(MIToken::NamedRegister, Range.upto(C))
422 .setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
431 .setStringValue(Range.upto(C).drop_front(1)); // Drop the '$'
423432 return C;
424433 }
425434
641650 return R.remaining();
642651 if (Cursor R = maybeLexIRValue(C, Token, ErrorCallback))
643652 return R.remaining();
644 if (Cursor R = maybeLexRegister(C, Token))
653 if (Cursor R = maybeLexRegister(C, Token, ErrorCallback))
645654 return R.remaining();
646655 if (Cursor R = maybeLexGlobalValue(C, Token, ErrorCallback))
647656 return R.remaining();
8888 unsigned SubIdx) {
8989 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
9090 if (!Reg)
91 OS << "%noreg";
91 OS << "$noreg";
9292 else if (TargetRegisterInfo::isStackSlot(Reg))
9393 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
9494 else if (TargetRegisterInfo::isVirtualRegister(Reg))
9595 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
9696 else if (!TRI)
97 OS << '%' << "physreg" << Reg;
97 OS << '$' << "physreg" << Reg;
9898 else if (Reg < TRI->getNumRegs()) {
99 OS << '%';
99 OS << '$';
100100 printLowerCase(TRI->getName(Reg), OS);
101101 } else
102102 llvm_unreachable("Register kind is unsupported.");
1212 ; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
1313 ; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
1414
15 ; CHECK: %w0 = COPY [[ANSWER]]
16 ; CHECK: %d0 = COPY [[D_ONE]]
17 ; CHECK: %x1 = COPY [[TWELVE]]
15 ; CHECK: $w0 = COPY [[ANSWER]]
16 ; CHECK: $d0 = COPY [[D_ONE]]
17 ; CHECK: $x1 = COPY [[TWELVE]]
1818 ; CHECK: G_STORE [[THREE]](s8), {{%[0-9]+}}(p0) :: (store 1 into stack, align 0)
1919 ; CHECK: G_STORE [[ONE]](s16), {{%[0-9]+}}(p0) :: (store 2 into stack + 8, align 0)
2020 ; CHECK: G_STORE [[FOUR]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 16, align 0)
33 target triple = "aarch64-linux-gnu"
44
55 ; CHECK-LABEL: name: args_i32
6 ; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY %w0
7 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w1
8 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w2
9 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w3
10 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w4
11 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w5
12 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w6
13 ; CHECK: %{{[0-9]+}}:_(s32) = COPY %w7
14 ; CHECK: %w0 = COPY %[[ARG0]]
6 ; CHECK: %[[ARG0:[0-9]+]]:_(s32) = COPY $w0
7 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w1
8 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w2
9 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w3
10 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w4
11 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w5
12 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w6
13 ; CHECK: %{{[0-9]+}}:_(s32) = COPY $w7
14 ; CHECK: $w0 = COPY %[[ARG0]]
1515
1616 define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
1717 i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
1919 }
2020
2121 ; CHECK-LABEL: name: args_i64
22 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %x0
23 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x1
24 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x2
25 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x3
26 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x4
27 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x5
28 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x6
29 ; CHECK: %{{[0-9]+}}:_(s64) = COPY %x7
30 ; CHECK: %x0 = COPY %[[ARG0]]
22 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $x0
23 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x1
24 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x2
25 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x3
26 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x4
27 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x5
28 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x6
29 ; CHECK: %{{[0-9]+}}:_(s64) = COPY $x7
30 ; CHECK: $x0 = COPY %[[ARG0]]
3131 define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
3232 i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
3333 ret i64 %x0
3535
3636
3737 ; CHECK-LABEL: name: args_ptrs
38 ; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY %x0
39 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x1
40 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x2
41 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x3
42 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x4
43 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x5
44 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x6
45 ; CHECK: %{{[0-9]+}}:_(p0) = COPY %x7
46 ; CHECK: %x0 = COPY %[[ARG0]]
38 ; CHECK: %[[ARG0:[0-9]+]]:_(p0) = COPY $x0
39 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x1
40 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x2
41 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x3
42 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x4
43 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x5
44 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x6
45 ; CHECK: %{{[0-9]+}}:_(p0) = COPY $x7
46 ; CHECK: $x0 = COPY %[[ARG0]]
4747 define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3,
4848 [3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) {
4949 ret i8* %x0
5050 }
5151
5252 ; CHECK-LABEL: name: args_arr
53 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY %d0
54 ; CHECK: %d0 = COPY %[[ARG0]]
53 ; CHECK: %[[ARG0:[0-9]+]]:_(s64) = COPY $d0
54 ; CHECK: $d0 = COPY %[[ARG0]]
5555 define [1 x double] @args_arr([1 x double] %d0) {
5656 ret [1 x double] %d0
5757 }
6666 ; CHECK: [[F_ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
6767 ; CHECK: [[TWO:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
6868
69 ; CHECK: %w0 = COPY [[ANSWER]]
70 ; CHECK: %d0 = COPY [[D_ONE]]
71 ; CHECK: %x1 = COPY [[TWELVE]]
69 ; CHECK: $w0 = COPY [[ANSWER]]
70 ; CHECK: $d0 = COPY [[D_ONE]]
71 ; CHECK: $x1 = COPY [[TWELVE]]
7272 ; CHECK: [[THREE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[THREE]]
73 ; CHECK: %w2 = COPY [[THREE_TMP]](s32)
73 ; CHECK: $w2 = COPY [[THREE_TMP]](s32)
7474 ; CHECK: [[ONE_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[ONE]]
75 ; CHECK: %w3 = COPY [[ONE_TMP]](s32)
76 ; CHECK: %w4 = COPY [[FOUR]](s32)
77 ; CHECK: %s1 = COPY [[F_ONE]](s32)
78 ; CHECK: %d2 = COPY [[TWO]](s64)
75 ; CHECK: $w3 = COPY [[ONE_TMP]](s32)
76 ; CHECK: $w4 = COPY [[FOUR]](s32)
77 ; CHECK: $s1 = COPY [[F_ONE]](s32)
78 ; CHECK: $d2 = COPY [[TWO]](s64)
7979 declare void @varargs(i32, double, i64, ...)
8080 define void @test_varargs() {
8181 call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0)
66
77 ; Tests for add.
88 ; CHECK-LABEL: name: addi64
9 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
10 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
9 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
10 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
1111 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_ADD [[ARG1]], [[ARG2]]
12 ; CHECK-NEXT: %x0 = COPY [[RES]]
13 ; CHECK-NEXT: RET_ReallyLR implicit %x0
12 ; CHECK-NEXT: $x0 = COPY [[RES]]
13 ; CHECK-NEXT: RET_ReallyLR implicit $x0
1414 define i64 @addi64(i64 %arg1, i64 %arg2) {
1515 %res = add i64 %arg1, %arg2
1616 ret i64 %res
1717 }
1818
1919 ; CHECK-LABEL: name: muli64
20 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
21 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
20 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
21 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
2222 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_MUL [[ARG1]], [[ARG2]]
23 ; CHECK-NEXT: %x0 = COPY [[RES]]
24 ; CHECK-NEXT: RET_ReallyLR implicit %x0
23 ; CHECK-NEXT: $x0 = COPY [[RES]]
24 ; CHECK-NEXT: RET_ReallyLR implicit $x0
2525 define i64 @muli64(i64 %arg1, i64 %arg2) {
2626 %res = mul i64 %arg1, %arg2
2727 ret i64 %res
106106 ; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
107107 ; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
108108 ;
109 ; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
109 ; CHECK: [[ADDR:%.*]]:_(p0) = COPY $x0
110110 ;
111111 ; Check that we emit the correct branch.
112112 ; CHECK: [[TST:%.*]]:_(s1) = G_LOAD [[ADDR]](p0)
134134 ;
135135 ; CHECK: bb.{{[a-zA-Z0-9.]+}}:
136136 ; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+]](0x40000000)
137 ; CHECK: %0:_(s32) = COPY %w0
137 ; CHECK: %0:_(s32) = COPY $w0
138138 ; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
139139 ; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
140140 ; CHECK: %[[reg0:[0-9]+]]:_(s32) = G_CONSTANT i32 0
170170 ;
171171 ; CHECK: [[BB_RET]].{{[a-zA-Z0-9.]+}}:
172172 ; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
173 ; CHECK: %w0 = COPY %[[regret]](s32)
174 ; CHECK: RET_ReallyLR implicit %w0
173 ; CHECK: $w0 = COPY %[[regret]](s32)
174 ; CHECK: RET_ReallyLR implicit $w0
175175 ;
176176 define i32 @switch(i32 %argc) {
177177 entry:
288288
289289 ; Tests for or.
290290 ; CHECK-LABEL: name: ori64
291 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
292 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
291 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
292 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
293293 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_OR [[ARG1]], [[ARG2]]
294 ; CHECK-NEXT: %x0 = COPY [[RES]]
295 ; CHECK-NEXT: RET_ReallyLR implicit %x0
294 ; CHECK-NEXT: $x0 = COPY [[RES]]
295 ; CHECK-NEXT: RET_ReallyLR implicit $x0
296296 define i64 @ori64(i64 %arg1, i64 %arg2) {
297297 %res = or i64 %arg1, %arg2
298298 ret i64 %res
299299 }
300300
301301 ; CHECK-LABEL: name: ori32
302 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
303 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
302 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
303 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
304304 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_OR [[ARG1]], [[ARG2]]
305 ; CHECK-NEXT: %w0 = COPY [[RES]]
306 ; CHECK-NEXT: RET_ReallyLR implicit %w0
305 ; CHECK-NEXT: $w0 = COPY [[RES]]
306 ; CHECK-NEXT: RET_ReallyLR implicit $w0
307307 define i32 @ori32(i32 %arg1, i32 %arg2) {
308308 %res = or i32 %arg1, %arg2
309309 ret i32 %res
311311
312312 ; Tests for xor.
313313 ; CHECK-LABEL: name: xori64
314 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
315 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
314 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
315 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
316316 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_XOR [[ARG1]], [[ARG2]]
317 ; CHECK-NEXT: %x0 = COPY [[RES]]
318 ; CHECK-NEXT: RET_ReallyLR implicit %x0
317 ; CHECK-NEXT: $x0 = COPY [[RES]]
318 ; CHECK-NEXT: RET_ReallyLR implicit $x0
319319 define i64 @xori64(i64 %arg1, i64 %arg2) {
320320 %res = xor i64 %arg1, %arg2
321321 ret i64 %res
322322 }
323323
324324 ; CHECK-LABEL: name: xori32
325 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
326 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
325 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
326 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
327327 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_XOR [[ARG1]], [[ARG2]]
328 ; CHECK-NEXT: %w0 = COPY [[RES]]
329 ; CHECK-NEXT: RET_ReallyLR implicit %w0
328 ; CHECK-NEXT: $w0 = COPY [[RES]]
329 ; CHECK-NEXT: RET_ReallyLR implicit $w0
330330 define i32 @xori32(i32 %arg1, i32 %arg2) {
331331 %res = xor i32 %arg1, %arg2
332332 ret i32 %res
334334
335335 ; Tests for and.
336336 ; CHECK-LABEL: name: andi64
337 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
338 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
337 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
338 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
339339 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_AND [[ARG1]], [[ARG2]]
340 ; CHECK-NEXT: %x0 = COPY [[RES]]
341 ; CHECK-NEXT: RET_ReallyLR implicit %x0
340 ; CHECK-NEXT: $x0 = COPY [[RES]]
341 ; CHECK-NEXT: RET_ReallyLR implicit $x0
342342 define i64 @andi64(i64 %arg1, i64 %arg2) {
343343 %res = and i64 %arg1, %arg2
344344 ret i64 %res
345345 }
346346
347347 ; CHECK-LABEL: name: andi32
348 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
349 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
348 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
349 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
350350 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_AND [[ARG1]], [[ARG2]]
351 ; CHECK-NEXT: %w0 = COPY [[RES]]
352 ; CHECK-NEXT: RET_ReallyLR implicit %w0
351 ; CHECK-NEXT: $w0 = COPY [[RES]]
352 ; CHECK-NEXT: RET_ReallyLR implicit $w0
353353 define i32 @andi32(i32 %arg1, i32 %arg2) {
354354 %res = and i32 %arg1, %arg2
355355 ret i32 %res
357357
358358 ; Tests for sub.
359359 ; CHECK-LABEL: name: subi64
360 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
361 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY %x1
360 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
361 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s64) = COPY $x1
362362 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s64) = G_SUB [[ARG1]], [[ARG2]]
363 ; CHECK-NEXT: %x0 = COPY [[RES]]
364 ; CHECK-NEXT: RET_ReallyLR implicit %x0
363 ; CHECK-NEXT: $x0 = COPY [[RES]]
364 ; CHECK-NEXT: RET_ReallyLR implicit $x0
365365 define i64 @subi64(i64 %arg1, i64 %arg2) {
366366 %res = sub i64 %arg1, %arg2
367367 ret i64 %res
368368 }
369369
370370 ; CHECK-LABEL: name: subi32
371 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
372 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
371 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
372 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
373373 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SUB [[ARG1]], [[ARG2]]
374 ; CHECK-NEXT: %w0 = COPY [[RES]]
375 ; CHECK-NEXT: RET_ReallyLR implicit %w0
374 ; CHECK-NEXT: $w0 = COPY [[RES]]
375 ; CHECK-NEXT: RET_ReallyLR implicit $w0
376376 define i32 @subi32(i32 %arg1, i32 %arg2) {
377377 %res = sub i32 %arg1, %arg2
378378 ret i32 %res
379379 }
380380
381381 ; CHECK-LABEL: name: ptrtoint
382 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
382 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
383383 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[ARG1]]
384 ; CHECK: %x0 = COPY [[RES]]
385 ; CHECK: RET_ReallyLR implicit %x0
384 ; CHECK: $x0 = COPY [[RES]]
385 ; CHECK: RET_ReallyLR implicit $x0
386386 define i64 @ptrtoint(i64* %a) {
387387 %val = ptrtoint i64* %a to i64
388388 ret i64 %val
389389 }
390390
391391 ; CHECK-LABEL: name: inttoptr
392 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
392 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
393393 ; CHECK: [[RES:%[0-9]+]]:_(p0) = G_INTTOPTR [[ARG1]]
394 ; CHECK: %x0 = COPY [[RES]]
395 ; CHECK: RET_ReallyLR implicit %x0
394 ; CHECK: $x0 = COPY [[RES]]
395 ; CHECK: RET_ReallyLR implicit $x0
396396 define i64* @inttoptr(i64 %a) {
397397 %val = inttoptr i64 %a to i64*
398398 ret i64* %val
399399 }
400400
401401 ; CHECK-LABEL: name: trivial_bitcast
402 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY %x0
403 ; CHECK: %x0 = COPY [[ARG1]]
404 ; CHECK: RET_ReallyLR implicit %x0
402 ; CHECK: [[ARG1:%[0-9]+]]:_(p0) = COPY $x0
403 ; CHECK: $x0 = COPY [[ARG1]]
404 ; CHECK: RET_ReallyLR implicit $x0
405405 define i64* @trivial_bitcast(i8* %a) {
406406 %val = bitcast i8* %a to i64*
407407 ret i64* %val
408408 }
409409
410410 ; CHECK-LABEL: name: trivial_bitcast_with_copy
411 ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
411 ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY $x0
412412 ; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
413413
414414 ; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
428428 }
429429
430430 ; CHECK-LABEL: name: bitcast
431 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
431 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
432432 ; CHECK: [[RES1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[ARG1]]
433433 ; CHECK: [[RES2:%[0-9]+]]:_(s64) = G_BITCAST [[RES1]]
434 ; CHECK: %x0 = COPY [[RES2]]
435 ; CHECK: RET_ReallyLR implicit %x0
434 ; CHECK: $x0 = COPY [[RES2]]
435 ; CHECK: RET_ReallyLR implicit $x0
436436 define i64 @bitcast(i64 %a) {
437437 %res1 = bitcast i64 %a to <2 x i32>
438438 %res2 = bitcast <2 x i32> %res1 to i64
440440 }
441441
442442 ; CHECK-LABEL: name: trunc
443 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY %x0
443 ; CHECK: [[ARG1:%[0-9]+]]:_(s64) = COPY $x0
444444 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_LOAD
445445 ; CHECK: [[RES1:%[0-9]+]]:_(s8) = G_TRUNC [[ARG1]]
446446 ; CHECK: [[RES2:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[VEC]]
453453 }
454454
455455 ; CHECK-LABEL: name: load
456 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
457 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
456 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
457 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
458458 ; CHECK: [[VAL1:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16)
459459 ; CHECK: [[VAL2:%[0-9]+]]:_(s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42, addrspace 42)
460460 ; CHECK: [[SUM2:%.*]]:_(s64) = G_ADD [[VAL1]], [[VAL2]]
461461 ; CHECK: [[VAL3:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr)
462462 ; CHECK: [[SUM3:%[0-9]+]]:_(s64) = G_ADD [[SUM2]], [[VAL3]]
463 ; CHECK: %x0 = COPY [[SUM3]]
464 ; CHECK: RET_ReallyLR implicit %x0
463 ; CHECK: $x0 = COPY [[SUM3]]
464 ; CHECK: RET_ReallyLR implicit $x0
465465 define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
466466 %val1 = load i64, i64* %addr, align 16
467467
474474 }
475475
476476 ; CHECK-LABEL: name: store
477 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
478 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY %x1
479 ; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY %x2
480 ; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY %x3
477 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
478 ; CHECK: [[ADDR42:%[0-9]+]]:_(p42) = COPY $x1
479 ; CHECK: [[VAL1:%[0-9]+]]:_(s64) = COPY $x2
480 ; CHECK: [[VAL2:%[0-9]+]]:_(s64) = COPY $x3
481481 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16)
482482 ; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42, addrspace 42)
483483 ; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr)
491491 }
492492
493493 ; CHECK-LABEL: name: intrinsics
494 ; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY %w0
495 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY %w1
494 ; CHECK: [[CUR:%[0-9]+]]:_(s32) = COPY $w0
495 ; CHECK: [[BITS:%[0-9]+]]:_(s32) = COPY $w1
496496 ; CHECK: [[CREG:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
497497 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]]
498498 ; CHECK: [[PTR_VEC:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.ptr.vec
521521 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
522522
523523 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
524 ; CHECK: %w0 = COPY [[RES]]
524 ; CHECK: $w0 = COPY [[RES]]
525525 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
526526 br i1 %tst, label %true, label %false
527527
550550 ; It's important that constants are after argument passing, but before the
551551 ; rest of the entry block.
552552 ; CHECK-LABEL: name: constant_int
553 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
553 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
554554 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
555555
556556 ; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
557557 ; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
558558 ; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
559559 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
560 ; CHECK: %w0 = COPY [[RES]]
560 ; CHECK: $w0 = COPY [[RES]]
561561
562562 define i32 @constant_int(i32 %in) {
563563 br label %next
580580
581581 ; CHECK-LABEL: name: test_undef
582582 ; CHECK: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
583 ; CHECK: %w0 = COPY [[UNDEF]]
583 ; CHECK: $w0 = COPY [[UNDEF]]
584584 define i32 @test_undef() {
585585 ret i32 undef
586586 }
588588 ; CHECK-LABEL: name: test_constant_inttoptr
589589 ; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
590590 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ONE]]
591 ; CHECK: %x0 = COPY [[PTR]]
591 ; CHECK: $x0 = COPY [[PTR]]
592592 define i8* @test_constant_inttoptr() {
593593 ret i8* inttoptr(i64 1 to i8*)
594594 }
597597 ; functions, so reuse the "i64 1" from above.
598598 ; CHECK-LABEL: name: test_reused_constant
599599 ; CHECK: [[ONE:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
600 ; CHECK: %x0 = COPY [[ONE]]
600 ; CHECK: $x0 = COPY [[ONE]]
601601 define i64 @test_reused_constant() {
602602 ret i64 1
603603 }
604604
605605 ; CHECK-LABEL: name: test_sext
606 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
606 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
607607 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SEXT [[IN]]
608 ; CHECK: %x0 = COPY [[RES]]
608 ; CHECK: $x0 = COPY [[RES]]
609609 define i64 @test_sext(i32 %in) {
610610 %res = sext i32 %in to i64
611611 ret i64 %res
612612 }
613613
614614 ; CHECK-LABEL: name: test_zext
615 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
615 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
616616 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ZEXT [[IN]]
617 ; CHECK: %x0 = COPY [[RES]]
617 ; CHECK: $x0 = COPY [[RES]]
618618 define i64 @test_zext(i32 %in) {
619619 %res = zext i32 %in to i64
620620 ret i64 %res
621621 }
622622
623623 ; CHECK-LABEL: name: test_shl
624 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
625 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
624 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
625 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
626626 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SHL [[ARG1]], [[ARG2]]
627 ; CHECK-NEXT: %w0 = COPY [[RES]]
628 ; CHECK-NEXT: RET_ReallyLR implicit %w0
627 ; CHECK-NEXT: $w0 = COPY [[RES]]
628 ; CHECK-NEXT: RET_ReallyLR implicit $w0
629629 define i32 @test_shl(i32 %arg1, i32 %arg2) {
630630 %res = shl i32 %arg1, %arg2
631631 ret i32 %res
633633
634634
635635 ; CHECK-LABEL: name: test_lshr
636 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
637 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
636 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
637 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
638638 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_LSHR [[ARG1]], [[ARG2]]
639 ; CHECK-NEXT: %w0 = COPY [[RES]]
640 ; CHECK-NEXT: RET_ReallyLR implicit %w0
639 ; CHECK-NEXT: $w0 = COPY [[RES]]
640 ; CHECK-NEXT: RET_ReallyLR implicit $w0
641641 define i32 @test_lshr(i32 %arg1, i32 %arg2) {
642642 %res = lshr i32 %arg1, %arg2
643643 ret i32 %res
644644 }
645645
646646 ; CHECK-LABEL: name: test_ashr
647 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
648 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
647 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
648 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
649649 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_ASHR [[ARG1]], [[ARG2]]
650 ; CHECK-NEXT: %w0 = COPY [[RES]]
651 ; CHECK-NEXT: RET_ReallyLR implicit %w0
650 ; CHECK-NEXT: $w0 = COPY [[RES]]
651 ; CHECK-NEXT: RET_ReallyLR implicit $w0
652652 define i32 @test_ashr(i32 %arg1, i32 %arg2) {
653653 %res = ashr i32 %arg1, %arg2
654654 ret i32 %res
655655 }
656656
657657 ; CHECK-LABEL: name: test_sdiv
658 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
659 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
658 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
659 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
660660 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SDIV [[ARG1]], [[ARG2]]
661 ; CHECK-NEXT: %w0 = COPY [[RES]]
662 ; CHECK-NEXT: RET_ReallyLR implicit %w0
661 ; CHECK-NEXT: $w0 = COPY [[RES]]
662 ; CHECK-NEXT: RET_ReallyLR implicit $w0
663663 define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
664664 %res = sdiv i32 %arg1, %arg2
665665 ret i32 %res
666666 }
667667
668668 ; CHECK-LABEL: name: test_udiv
669 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
670 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
669 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
670 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
671671 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UDIV [[ARG1]], [[ARG2]]
672 ; CHECK-NEXT: %w0 = COPY [[RES]]
673 ; CHECK-NEXT: RET_ReallyLR implicit %w0
672 ; CHECK-NEXT: $w0 = COPY [[RES]]
673 ; CHECK-NEXT: RET_ReallyLR implicit $w0
674674 define i32 @test_udiv(i32 %arg1, i32 %arg2) {
675675 %res = udiv i32 %arg1, %arg2
676676 ret i32 %res
677677 }
678678
679679 ; CHECK-LABEL: name: test_srem
680 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
681 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
680 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
681 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
682682 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_SREM [[ARG1]], [[ARG2]]
683 ; CHECK-NEXT: %w0 = COPY [[RES]]
684 ; CHECK-NEXT: RET_ReallyLR implicit %w0
683 ; CHECK-NEXT: $w0 = COPY [[RES]]
684 ; CHECK-NEXT: RET_ReallyLR implicit $w0
685685 define i32 @test_srem(i32 %arg1, i32 %arg2) {
686686 %res = srem i32 %arg1, %arg2
687687 ret i32 %res
688688 }
689689
690690 ; CHECK-LABEL: name: test_urem
691 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %w0
692 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %w1
691 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $w0
692 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $w1
693693 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_UREM [[ARG1]], [[ARG2]]
694 ; CHECK-NEXT: %w0 = COPY [[RES]]
695 ; CHECK-NEXT: RET_ReallyLR implicit %w0
694 ; CHECK-NEXT: $w0 = COPY [[RES]]
695 ; CHECK-NEXT: RET_ReallyLR implicit $w0
696696 define i32 @test_urem(i32 %arg1, i32 %arg2) {
697697 %res = urem i32 %arg1, %arg2
698698 ret i32 %res
700700
701701 ; CHECK-LABEL: name: test_constant_null
702702 ; CHECK: [[NULL:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
703 ; CHECK: %x0 = COPY [[NULL]]
703 ; CHECK: $x0 = COPY [[NULL]]
704704 define i8* @test_constant_null() {
705705 ret i8* null
706706 }
707707
708708 ; CHECK-LABEL: name: test_struct_memops
709 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
709 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
710710 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 4)
711711 ; CHECK: G_STORE [[VAL]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 4)
712712 define void @test_struct_memops({ i8, i32 }* %addr) {
716716 }
717717
718718 ; CHECK-LABEL: name: test_i1_memops
719 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
719 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
720720 ; CHECK: [[VAL:%[0-9]+]]:_(s1) = G_LOAD [[ADDR]](p0) :: (load 1 from %ir.addr)
721721 ; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store 1 into %ir.addr)
722722 define void @test_i1_memops(i1* %addr) {
726726 }
727727
728728 ; CHECK-LABEL: name: int_comparison
729 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
730 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
731 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
729 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
730 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
731 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
732732 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]]
733733 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
734734 define void @int_comparison(i32 %a, i32 %b, i1* %addr) {
738738 }
739739
740740 ; CHECK-LABEL: name: ptr_comparison
741 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x0
742 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x1
743 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
741 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x0
742 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x1
743 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
744744 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]]
745745 ; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0)
746746 define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) {
750750 }
751751
752752 ; CHECK-LABEL: name: test_fadd
753 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
754 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
753 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
754 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
755755 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FADD [[ARG1]], [[ARG2]]
756 ; CHECK-NEXT: %s0 = COPY [[RES]]
757 ; CHECK-NEXT: RET_ReallyLR implicit %s0
756 ; CHECK-NEXT: $s0 = COPY [[RES]]
757 ; CHECK-NEXT: RET_ReallyLR implicit $s0
758758 define float @test_fadd(float %arg1, float %arg2) {
759759 %res = fadd float %arg1, %arg2
760760 ret float %res
761761 }
762762
763763 ; CHECK-LABEL: name: test_fsub
764 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
765 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
764 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
765 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
766766 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FSUB [[ARG1]], [[ARG2]]
767 ; CHECK-NEXT: %s0 = COPY [[RES]]
768 ; CHECK-NEXT: RET_ReallyLR implicit %s0
767 ; CHECK-NEXT: $s0 = COPY [[RES]]
768 ; CHECK-NEXT: RET_ReallyLR implicit $s0
769769 define float @test_fsub(float %arg1, float %arg2) {
770770 %res = fsub float %arg1, %arg2
771771 ret float %res
772772 }
773773
774774 ; CHECK-LABEL: name: test_fmul
775 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
776 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
775 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
776 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
777777 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FMUL [[ARG1]], [[ARG2]]
778 ; CHECK-NEXT: %s0 = COPY [[RES]]
779 ; CHECK-NEXT: RET_ReallyLR implicit %s0
778 ; CHECK-NEXT: $s0 = COPY [[RES]]
779 ; CHECK-NEXT: RET_ReallyLR implicit $s0
780780 define float @test_fmul(float %arg1, float %arg2) {
781781 %res = fmul float %arg1, %arg2
782782 ret float %res
783783 }
784784
785785 ; CHECK-LABEL: name: test_fdiv
786 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
787 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
786 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
787 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
788788 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FDIV [[ARG1]], [[ARG2]]
789 ; CHECK-NEXT: %s0 = COPY [[RES]]
790 ; CHECK-NEXT: RET_ReallyLR implicit %s0
789 ; CHECK-NEXT: $s0 = COPY [[RES]]
790 ; CHECK-NEXT: RET_ReallyLR implicit $s0
791791 define float @test_fdiv(float %arg1, float %arg2) {
792792 %res = fdiv float %arg1, %arg2
793793 ret float %res
794794 }
795795
796796 ; CHECK-LABEL: name: test_frem
797 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY %s0
798 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY %s1
797 ; CHECK: [[ARG1:%[0-9]+]]:_(s32) = COPY $s0
798 ; CHECK-NEXT: [[ARG2:%[0-9]+]]:_(s32) = COPY $s1
799799 ; CHECK-NEXT: [[RES:%[0-9]+]]:_(s32) = G_FREM [[ARG1]], [[ARG2]]
800 ; CHECK-NEXT: %s0 = COPY [[RES]]
801 ; CHECK-NEXT: RET_ReallyLR implicit %s0
800 ; CHECK-NEXT: $s0 = COPY [[RES]]
801 ; CHECK-NEXT: RET_ReallyLR implicit $s0
802802 define float @test_frem(float %arg1, float %arg2) {
803803 %res = frem float %arg1, %arg2
804804 ret float %res
805805 }
806806
807807 ; CHECK-LABEL: name: test_sadd_overflow
808 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
809 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
810 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
808 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
809 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
810 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
811811 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SADDO [[LHS]], [[RHS]]
812812 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
813813 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
821821 }
822822
823823 ; CHECK-LABEL: name: test_uadd_overflow
824 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
825 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
826 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
824 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
825 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
826 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
827827 ; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
828828 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]]
829829 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
838838 }
839839
840840 ; CHECK-LABEL: name: test_ssub_overflow
841 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
842 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
843 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
841 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
842 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
843 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
844844 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SSUBO [[LHS]], [[RHS]]
845845 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
846846 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
854854 }
855855
856856 ; CHECK-LABEL: name: test_usub_overflow
857 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
858 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
859 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
857 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
858 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
859 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
860860 ; CHECK: [[ZERO:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
861861 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]]
862862 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
871871 }
872872
873873 ; CHECK-LABEL: name: test_smul_overflow
874 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
875 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
876 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
874 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
875 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
876 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
877877 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_SMULO [[LHS]], [[RHS]]
878878 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
879879 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
887887 }
888888
889889 ; CHECK-LABEL: name: test_umul_overflow
890 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w0
891 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w1
892 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
890 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w0
891 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w1
892 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
893893 ; CHECK: [[VAL:%[0-9]+]]:_(s32), [[OVERFLOW:%[0-9]+]]:_(s1) = G_UMULO [[LHS]], [[RHS]]
894894 ; CHECK: [[TMP:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
895895 ; CHECK: [[TMP1:%[0-9]+]]:_(s64) = G_INSERT [[TMP]], [[VAL]](s32), 0
905905 ; CHECK-LABEL: name: test_extractvalue
906906 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
907907 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT [[STRUCT]](s128), 64
908 ; CHECK: %w0 = COPY [[RES]]
908 ; CHECK: $w0 = COPY [[RES]]
909909 %struct.nested = type {i8, { i8, i32 }, i32}
910910 define i32 @test_extractvalue(%struct.nested* %addr) {
911911 %struct = load %struct.nested, %struct.nested* %addr
925925 }
926926
927927 ; CHECK-LABEL: name: test_insertvalue
928 ; CHECK: [[VAL:%[0-9]+]]:_(s32) = COPY %w1
928 ; CHECK: [[VAL:%[0-9]+]]:_(s32) = COPY $w1
929929 ; CHECK: [[STRUCT:%[0-9]+]]:_(s128) = G_LOAD
930930 ; CHECK: [[NEWSTRUCT:%[0-9]+]]:_(s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64
931931 ; CHECK: G_STORE [[NEWSTRUCT]](s128),
938938
939939 define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) {
940940 ; CHECK-LABEL: name: test_trivial_insert
941 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
942 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY %x1
941 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0
942 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = COPY $x1
943943 ; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY [[VAL]](s64)
944 ; CHECK: %x0 = COPY [[RES]]
944 ; CHECK: $x0 = COPY [[RES]]
945945 %res = insertvalue [1 x i64] %s, i64 %val, 0
946946 ret [1 x i64] %res
947947 }
948948
949949 define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) {
950950 ; CHECK-LABEL: name: test_trivial_insert_ptr
951 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY %x0
952 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY %x1
951 ; CHECK: [[STRUCT:%[0-9]+]]:_(s64) = COPY $x0
952 ; CHECK: [[VAL:%[0-9]+]]:_(p0) = COPY $x1
953953 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_PTRTOINT [[VAL]](p0)
954 ; CHECK: %x0 = COPY [[RES]]
954 ; CHECK: $x0 = COPY [[RES]]
955955 %res = insertvalue [1 x i8*] %s, i8* %val, 0
956956 ret [1 x i8*] %res
957957 }
970970 }
971971
972972 ; CHECK-LABEL: name: test_select
973 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
973 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
974974 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
975 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %w1
976 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %w2
975 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $w1
976 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w2
977977 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
978 ; CHECK: %w0 = COPY [[RES]]
978 ; CHECK: $w0 = COPY [[RES]]
979979 define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) {
980980 %res = select i1 %tst, i32 %lhs, i32 %rhs
981981 ret i32 %res
982982 }
983983
984984 ; CHECK-LABEL: name: test_select_ptr
985 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
985 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
986986 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
987 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY %x1
988 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY %x2
987 ; CHECK: [[LHS:%[0-9]+]]:_(p0) = COPY $x1
988 ; CHECK: [[RHS:%[0-9]+]]:_(p0) = COPY $x2
989989 ; CHECK: [[RES:%[0-9]+]]:_(p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
990 ; CHECK: %x0 = COPY [[RES]]
990 ; CHECK: $x0 = COPY [[RES]]
991991 define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) {
992992 %res = select i1 %tst, i8* %lhs, i8* %rhs
993993 ret i8* %res
994994 }
995995
996996 ; CHECK-LABEL: name: test_select_vec
997 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY %w0
997 ; CHECK: [[TST_C:%[0-9]+]]:_(s32) = COPY $w0
998998 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_TRUNC [[TST_C]]
999 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1000 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
999 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q0
1000 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
10011001 ; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]]
1002 ; CHECK: %q0 = COPY [[RES]]
1002 ; CHECK: $q0 = COPY [[RES]]
10031003 define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) {
10041004 %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs
10051005 ret <4 x i32> %res
10061006 }
10071007
10081008 ; CHECK-LABEL: name: test_vselect_vec
1009 ; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1010 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY %q1
1011 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY %q2
1009 ; CHECK: [[TST32:%[0-9]+]]:_(<4 x s32>) = COPY $q0
1010 ; CHECK: [[LHS:%[0-9]+]]:_(<4 x s32>) = COPY $q1
1011 ; CHECK: [[RHS:%[0-9]+]]:_(<4 x s32>) = COPY $q2
10121012 ; CHECK: [[TST:%[0-9]+]]:_(<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>)
10131013 ; CHECK: [[RES:%[0-9]+]]:_(<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]]
1014 ; CHECK: %q0 = COPY [[RES]]
1014 ; CHECK: $q0 = COPY [[RES]]
10151015 define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) {
10161016 %tst = trunc <4 x i32> %tst32 to <4 x i1>
10171017 %res = select <4 x i1> %tst, <4 x i32> %lhs, <4 x i32> %rhs
10191019 }
10201020
10211021 ; CHECK-LABEL: name: test_fptosi
1022 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
1022 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
10231023 ; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
10241024 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOSI [[FP]](s32)
1025 ; CHECK: %x0 = COPY [[RES]]
1025 ; CHECK: $x0 = COPY [[RES]]
10261026 define i64 @test_fptosi(float* %fp.addr) {
10271027 %fp = load float, float* %fp.addr
10281028 %res = fptosi float %fp to i64
10301030 }
10311031
10321032 ; CHECK-LABEL: name: test_fptoui
1033 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY %x0
1033 ; CHECK: [[FPADDR:%[0-9]+]]:_(p0) = COPY $x0
10341034 ; CHECK: [[FP:%[0-9]+]]:_(s32) = G_LOAD [[FPADDR]](p0)
10351035 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPTOUI [[FP]](s32)
1036 ; CHECK: %x0 = COPY [[RES]]
1036 ; CHECK: $x0 = COPY [[RES]]
10371037 define i64 @test_fptoui(float* %fp.addr) {
10381038 %fp = load float, float* %fp.addr
10391039 %res = fptoui float %fp to i64
10411041 }
10421042
10431043 ; CHECK-LABEL: name: test_sitofp
1044 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1045 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
1044 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
1045 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
10461046 ; CHECK: [[FP:%[0-9]+]]:_(s64) = G_SITOFP [[IN]](s32)
10471047 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
10481048 define void @test_sitofp(double* %addr, i32 %in) {
10521052 }
10531053
10541054 ; CHECK-LABEL: name: test_uitofp
1055 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1056 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w1
1055 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
1056 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w1
10571057 ; CHECK: [[FP:%[0-9]+]]:_(s64) = G_UITOFP [[IN]](s32)
10581058 ; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0)
10591059 define void @test_uitofp(double* %addr, i32 %in) {
10631063 }
10641064
10651065 ; CHECK-LABEL: name: test_fpext
1066 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %s0
1066 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $s0
10671067 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FPEXT [[IN]](s32)
1068 ; CHECK: %d0 = COPY [[RES]]
1068 ; CHECK: $d0 = COPY [[RES]]
10691069 define double @test_fpext(float %in) {
10701070 %res = fpext float %in to double
10711071 ret double %res
10721072 }
10731073
10741074 ; CHECK-LABEL: name: test_fptrunc
1075 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %d0
1075 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $d0
10761076 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPTRUNC [[IN]](s64)
1077 ; CHECK: %s0 = COPY [[RES]]
1077 ; CHECK: $s0 = COPY [[RES]]
10781078 define float @test_fptrunc(double %in) {
10791079 %res = fptrunc double %in to float
10801080 ret float %res
10811081 }
10821082
10831083 ; CHECK-LABEL: name: test_constant_float
1084 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1084 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
10851085 ; CHECK: [[TMP:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+00
10861086 ; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0)
10871087 define void @test_constant_float(float* %addr) {
10901090 }
10911091
10921092 ; CHECK-LABEL: name: float_comparison
1093 ; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY %x0
1094 ; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY %x1
1095 ; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY %x2
1093 ; CHECK: [[LHSADDR:%[0-9]+]]:_(p0) = COPY $x0
1094 ; CHECK: [[RHSADDR:%[0-9]+]]:_(p0) = COPY $x1
1095 ; CHECK: [[BOOLADDR:%[0-9]+]]:_(p0) = COPY $x2
10961096 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_LOAD [[LHSADDR]](p0)
10971097 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_LOAD [[RHSADDR]](p0)
10981098 ; CHECK: [[TST:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]]
11231123 define i32* @test_global() {
11241124 ; CHECK-LABEL: name: test_global
11251125 ; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var{{$}}
1126 ; CHECK: %x0 = COPY [[TMP]](p0)
1126 ; CHECK: $x0 = COPY [[TMP]](p0)
11271127
11281128 ret i32* @var
11291129 }
11321132 define i32 addrspace(42)* @test_global_addrspace() {
11331133 ; CHECK-LABEL: name: test_global
11341134 ; CHECK: [[TMP:%[0-9]+]]:_(p42) = G_GLOBAL_VALUE @var1{{$}}
1135 ; CHECK: %x0 = COPY [[TMP]](p42)
1135 ; CHECK: $x0 = COPY [[TMP]](p42)
11361136
11371137 ret i32 addrspace(42)* @var1
11381138 }
11411141 define void()* @test_global_func() {
11421142 ; CHECK-LABEL: name: test_global_func
11431143 ; CHECK: [[TMP:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @allocai64{{$}}
1144 ; CHECK: %x0 = COPY [[TMP]](p0)
1144 ; CHECK: $x0 = COPY [[TMP]](p0)
11451145
11461146 ret void()* @allocai64
11471147 }
11491149 declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i1)
11501150 define void @test_memcpy(i8* %dst, i8* %src, i64 %size) {
11511151 ; CHECK-LABEL: name: test_memcpy
1152 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1153 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
1154 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
1155 ; CHECK: %x0 = COPY [[DST]]
1156 ; CHECK: %x1 = COPY [[SRC]]
1157 ; CHECK: %x2 = COPY [[SIZE]]
1158 ; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2
1152 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
1153 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
1154 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
1155 ; CHECK: $x0 = COPY [[DST]]
1156 ; CHECK: $x1 = COPY [[SRC]]
1157 ; CHECK: $x2 = COPY [[SIZE]]
1158 ; CHECK: BL &memcpy, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
11591159 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0)
11601160 ret void
11611161 }
11631163 declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i1)
11641164 define void @test_memmove(i8* %dst, i8* %src, i64 %size) {
11651165 ; CHECK-LABEL: name: test_memmove
1166 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1167 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY %x1
1168 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
1169 ; CHECK: %x0 = COPY [[DST]]
1170 ; CHECK: %x1 = COPY [[SRC]]
1171 ; CHECK: %x2 = COPY [[SIZE]]
1172 ; CHECK: BL &memmove, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2
1166 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
1167 ; CHECK: [[SRC:%[0-9]+]]:_(p0) = COPY $x1
1168 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
1169 ; CHECK: $x0 = COPY [[DST]]
1170 ; CHECK: $x1 = COPY [[SRC]]
1171 ; CHECK: $x2 = COPY [[SIZE]]
1172 ; CHECK: BL &memmove, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2
11731173 call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i1 0)
11741174 ret void
11751175 }
11771177 declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i1)
11781178 define void @test_memset(i8* %dst, i8 %val, i64 %size) {
11791179 ; CHECK-LABEL: name: test_memset
1180 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY %x0
1181 ; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY %w1
1180 ; CHECK: [[DST:%[0-9]+]]:_(p0) = COPY $x0
1181 ; CHECK: [[SRC_C:%[0-9]+]]:_(s32) = COPY $w1
11821182 ; CHECK: [[SRC:%[0-9]+]]:_(s8) = G_TRUNC [[SRC_C]]
1183 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY %x2
1184 ; CHECK: %x0 = COPY [[DST]]
1183 ; CHECK: [[SIZE:%[0-9]+]]:_(s64) = COPY $x2
1184 ; CHECK: $x0 = COPY [[DST]]
11851185 ; CHECK: [[SRC_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[SRC]]
1186 ; CHECK: %w1 = COPY [[SRC_TMP]]
1187 ; CHECK: %x2 = COPY [[SIZE]]
1188 ; CHECK: BL &memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2
1186 ; CHECK: $w1 = COPY [[SRC_TMP]]
1187 ; CHECK: $x2 = COPY [[SIZE]]
1188 ; CHECK: BL &memset, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
11891189 call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i1 0)
11901190 ret void
11911191 }
11941194 declare i32 @llvm.objectsize.i32(i8*, i1)
11951195 define void @test_objectsize(i8* %addr0, i8* %addr1) {
11961196 ; CHECK-LABEL: name: test_objectsize
1197 ; CHECK: [[ADDR0:%[0-9]+]]:_(p0) = COPY %x0
1198 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY %x1
1197 ; CHECK: [[ADDR0:%[0-9]+]]:_(p0) = COPY $x0
1198 ; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $x1
11991199 ; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 -1
12001200 ; CHECK: {{%[0-9]+}}:_(s64) = G_CONSTANT i64 0
12011201 ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 -1
12091209
12101210 define void @test_large_const(i128* %addr) {
12111211 ; CHECK-LABEL: name: test_large_const
1212 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1212 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
12131213 ; CHECK: [[VAL:%[0-9]+]]:_(s128) = G_CONSTANT i128 42
12141214 ; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0)
12151215 store i128 42, i128* %addr
12441244
12451245 define void @test_va_arg(i8* %list) {
12461246 ; CHECK-LABEL: test_va_arg
1247 ; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY %x0
1247 ; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY $x0
12481248 ; CHECK: G_VAARG [[LIST]](p0), 8
12491249 ; CHECK: G_VAARG [[LIST]](p0), 1
12501250 ; CHECK: G_VAARG [[LIST]](p0), 16
12581258 declare float @llvm.pow.f32(float, float)
12591259 define float @test_pow_intrin(float %l, float %r) {
12601260 ; CHECK-LABEL: name: test_pow_intrin
1261 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY %s0
1262 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY %s1
1261 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
1262 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s1
12631263 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FPOW [[LHS]], [[RHS]]
1264 ; CHECK: %s0 = COPY [[RES]]
1264 ; CHECK: $s0 = COPY [[RES]]
12651265 %res = call float @llvm.pow.f32(float %l, float %r)
12661266 ret float %res
12671267 }
12691269 declare float @llvm.fma.f32(float, float, float)
12701270 define float @test_fma_intrin(float %a, float %b, float %c) {
12711271 ; CHECK-LABEL: name: test_fma_intrin
1272 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1273 ; CHECK: [[B:%[0-9]+]]:_(s32) = COPY %s1
1274 ; CHECK: [[C:%[0-9]+]]:_(s32) = COPY %s2
1272 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
1273 ; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1
1274 ; CHECK: [[C:%[0-9]+]]:_(s32) = COPY $s2
12751275 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FMA [[A]], [[B]], [[C]]
1276 ; CHECK: %s0 = COPY [[RES]]
1276 ; CHECK: $s0 = COPY [[RES]]
12771277 %res = call float @llvm.fma.f32(float %a, float %b, float %c)
12781278 ret float %res
12791279 }
12811281 declare float @llvm.exp.f32(float)
12821282 define float @test_exp_intrin(float %a) {
12831283 ; CHECK-LABEL: name: test_exp_intrin
1284 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1284 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
12851285 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP [[A]]
1286 ; CHECK: %s0 = COPY [[RES]]
1286 ; CHECK: $s0 = COPY [[RES]]
12871287 %res = call float @llvm.exp.f32(float %a)
12881288 ret float %res
12891289 }
12911291 declare float @llvm.exp2.f32(float)
12921292 define float @test_exp2_intrin(float %a) {
12931293 ; CHECK-LABEL: name: test_exp2_intrin
1294 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1294 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
12951295 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FEXP2 [[A]]
1296 ; CHECK: %s0 = COPY [[RES]]
1296 ; CHECK: $s0 = COPY [[RES]]
12971297 %res = call float @llvm.exp2.f32(float %a)
12981298 ret float %res
12991299 }
13011301 declare float @llvm.log.f32(float)
13021302 define float @test_log_intrin(float %a) {
13031303 ; CHECK-LABEL: name: test_log_intrin
1304 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1304 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
13051305 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG [[A]]
1306 ; CHECK: %s0 = COPY [[RES]]
1306 ; CHECK: $s0 = COPY [[RES]]
13071307 %res = call float @llvm.log.f32(float %a)
13081308 ret float %res
13091309 }
13111311 declare float @llvm.log2.f32(float)
13121312 define float @test_log2_intrin(float %a) {
13131313 ; CHECK-LABEL: name: test_log2_intrin
1314 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY %s0
1314 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
13151315 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG2 [[A]]
1316 ; CHECK: %s0 = COPY [[RES]]
1316 ; CHECK: $s0 = COPY [[RES]]
13171317 %res = call float @llvm.log2.f32(float %a)
13181318 ret float %res
13191319 }
13301330
13311331 define void @test_load_store_atomics(i8* %addr) {
13321332 ; CHECK-LABEL: name: test_load_store_atomics
1333 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1333 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
13341334 ; CHECK: [[V0:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr)
13351335 ; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr)
13361336 ; CHECK: [[V1:%[0-9]+]]:_(s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr)
13511351
13521352 define float @test_fneg_f32(float %x) {
13531353 ; CHECK-LABEL: name: test_fneg_f32
1354 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %s0
1354 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
13551355 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
1356 ; CHECK: %s0 = COPY [[RES]](s32)
1356 ; CHECK: $s0 = COPY [[RES]](s32)
13571357 %neg = fsub float -0.000000e+00, %x
13581358 ret float %neg
13591359 }
13601360
13611361 define double @test_fneg_f64(double %x) {
13621362 ; CHECK-LABEL: name: test_fneg_f64
1363 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY %d0
1363 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
13641364 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
1365 ; CHECK: %d0 = COPY [[RES]](s64)
1365 ; CHECK: $d0 = COPY [[RES]](s64)
13661366 %neg = fsub double -0.000000e+00, %x
13671367 ret double %neg
13681368 }
13781378
13791379 define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){
13801380 ; CHECK-LABEL: name: test_insertelement
1381 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1382 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
1383 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w1
1381 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
1382 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
1383 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w1
13841384 ; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32)
1385 ; CHECK: %d0 = COPY [[RES]](<2 x s32>)
1385 ; CHECK: $d0 = COPY [[RES]](<2 x s32>)
13861386 %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx
13871387 ret <2 x i32> %res
13881388 }
13891389
13901390 define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) {
13911391 ; CHECK-LABEL: name: test_extractelement
1392 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1393 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY %w0
1392 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0
1393 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w0
13941394 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32)
1395 ; CHECK: %w0 = COPY [[RES]](s32)
1395 ; CHECK: $w0 = COPY [[RES]](s32)
13961396 %res = extractelement <2 x i32> %vec, i32 %idx
13971397 ret i32 %res
13981398 }
13991399
14001400 define i32 @test_singleelementvector(i32 %elt){
14011401 ; CHECK-LABEL: name: test_singleelementvector
1402 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY %w0
1402 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0
14031403 ; CHECK-NOT: G_INSERT_VECTOR_ELT
14041404 ; CHECK-NOT: G_EXTRACT_VECTOR_ELT
1405 ; CHECK: %w0 = COPY [[ELT]](s32)
1405 ; CHECK: $w0 = COPY [[ELT]](s32)
14061406 %vec = insertelement <1 x i32> undef, i32 %elt, i32 0
14071407 %res = extractelement <1 x i32> %vec, i32 0
14081408 ret i32 %res
14121412 ; CHECK-LABEL: name: test_constantaggzerovector_v2i32
14131413 ; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14141414 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
1415 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1415 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
14161416 ret <2 x i32> zeroinitializer
14171417 }
14181418
14201420 ; CHECK-LABEL: name: test_constantaggzerovector_v2f32
14211421 ; CHECK: [[ZERO:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
14221422 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32)
1423 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1423 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
14241424 ret <2 x float> zeroinitializer
14251425 }
14261426
14381438 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
14391439 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
14401440 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32)
1441 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1441 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
14421442 ret <2 x i32>
14431443 }
14441444
14601460 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
14611461 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
14621462 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)
1463 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
1463 ; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
14641464 ret <4 x i32>
14651465 }
14661466
14691469 ; CHECK: [[FC1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
14701470 ; CHECK: [[FC2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
14711471 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64)
1472 ; CHECK: %q0 = COPY [[VEC]](<2 x s64>)
1472 ; CHECK: $q0 = COPY [[VEC]](<2 x s64>)
14731473 ret <2 x double>
14741474 }
14751475
14761476 define i32 @test_constantaggzerovector_v1s32(i32 %arg){
14771477 ; CHECK-LABEL: name: test_constantaggzerovector_v1s32
1478 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1478 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
14791479 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14801480 ; CHECK-NOT: G_MERGE_VALUES
14811481 ; CHECK: G_ADD [[ARG]], [[C0]]
14871487
14881488 define i32 @test_constantdatavector_v1s32(i32 %arg){
14891489 ; CHECK-LABEL: name: test_constantdatavector_v1s32
1490 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1490 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
14911491 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
14921492 ; CHECK-NOT: G_MERGE_VALUES
14931493 ; CHECK: G_ADD [[ARG]], [[C1]]
15001500 declare ghccc float @different_call_conv_target(float %x)
15011501 define float @test_different_call_conv_target(float %x) {
15021502 ; CHECK-LABEL: name: test_different_call_conv
1503 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
1504 ; CHECK: %s8 = COPY [[X]]
1505 ; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s8, implicit-def %s0
1503 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0
1504 ; CHECK: $s8 = COPY [[X]]
1505 ; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s8, implicit-def $s0
15061506 %res = call ghccc float @different_call_conv_target(float %x)
15071507 ret float %res
15081508 }
15091509
15101510 define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
15111511 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
1512 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %w0
1512 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0
15131513 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
15141514 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
15151515 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
15161516 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
1517 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1517 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
15181518 %vec = insertelement <1 x i32> undef, i32 %arg, i32 0
15191519 %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
15201520 ret <2 x i32> %res
15221522
15231523 define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
15241524 ; CHECK-LABEL: name: test_shufflevector_v2s32_s32
1525 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1525 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
15261526 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
15271527 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15281528 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
1529 ; CHECK: %w0 = COPY [[RES]](s32)
1529 ; CHECK: $w0 = COPY [[RES]](s32)
15301530 %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32>
15311531 %res = extractelement <1 x i32> %vec, i32 0
15321532 ret i32 %res
15341534
15351535 define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
15361536 ; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
1537 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1537 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
15381538 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
15391539 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15401540 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
15411541 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
15421542 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1543 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1543 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
15441544 %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32>
15451545 ret <2 x i32> %res
15461546 }
15471547
15481548 define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
15491549 ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
1550 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1550 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0
15511551 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
15521552 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15531553 ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
15611561
15621562 define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
15631563 ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
1564 ; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY %d0
1565 ; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY %d1
1564 ; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY $d0
1565 ; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY $d1
15661566 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
15671567 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15681568 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
15691569 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
15701570 ; CHECK: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
15711571 ; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
1572 ; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
1572 ; CHECK: $q0 = COPY [[VEC]](<4 x s32>)
15731573 %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32>
15741574 ret <4 x i32> %res
15751575 }
15761576
15771577 define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
15781578 ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
1579 ; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY %q0
1579 ; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY $q0
15801580 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
15811581 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
15821582 ; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
15831583 ; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
15841584 ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
1585 ; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
1585 ; CHECK: $d0 = COPY [[VEC]](<2 x s32>)
15861586 %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32>
15871587 ret <2 x i32> %res
15881588 }
15901590
15911591 define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
15921592 ; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
1593 ; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY %d0
1594 ; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY %d1
1593 ; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
1594 ; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY $d1
15951595 ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
15961596 ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
15971597 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
16101610 ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
16111611 ; CHECK: [[MASK:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
16121612 ; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
1613 ; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
1613 ; CHECK: $q0 = COPY [[VEC]](<16 x s8>)
16141614 %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32>
16151615 ret <16 x i8> %res
16161616 }
16191619 ; CHECK: [[UNDEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
16201620 ; CHECK: [[F:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
16211621 ; CHECK: [[M:%[0-9]+]]:_(<4 x s16>) = G_MERGE_VALUES [[UNDEF]](s16), [[UNDEF]](s16), [[UNDEF]](s16), [[F]](s16)
1622 ; CHECK: %d0 = COPY [[M]](<4 x s16>)
1622 ; CHECK: $d0 = COPY [[M]](<4 x s16>)
16231623 define <4 x half> @test_constant_vector() {
16241624 ret <4 x half>
16251625 }
16261626
16271627 define i32 @test_target_mem_intrinsic(i32* %addr) {
16281628 ; CHECK-LABEL: name: test_target_mem_intrinsic
1629 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
1629 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
16301630 ; CHECK: [[VAL:%[0-9]+]]:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), [[ADDR]](p0) :: (volatile load 4 from %ir.addr)
16311631 ; CHECK: G_TRUNC [[VAL]](s64)
16321632 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
121121 - { id: 1, class: _ }
122122 body: |
123123 bb.0.entry:
124 liveins: %x0
124 liveins: $x0
125125 ; CHECK-LABEL: name: defaultMapping
126126 ; CHECK: %1:gpr(s32) = G_ADD %0
127 %0(s32) = COPY %w0
127 %0(s32) = COPY $w0
128128 %1(s32) = G_ADD %0, %0
129129 ...
130130
139139 - { id: 1, class: _ }
140140 body: |
141141 bb.0.entry:
142 liveins: %d0
142 liveins: $d0
143143 ; CHECK-LABEL: name: defaultMappingVector
144 ; CHECK: %0:fpr(<2 x s32>) = COPY %d0
144 ; CHECK: %0:fpr(<2 x s32>) = COPY $d0
145145 ; CHECK: %1:fpr(<2 x s32>) = G_ADD %0
146 %0(<2 x s32>) = COPY %d0
146 %0(<2 x s32>) = COPY $d0
147147 %1(<2 x s32>) = G_ADD %0, %0
148148 ...
149149
159159 - { id: 2, class: _ }
160160 body: |
161161 bb.0.entry:
162 liveins: %s0, %x0
162 liveins: $s0, $x0
163163 ; CHECK-LABEL: name: defaultMapping1Repair
164 ; CHECK: %0:fpr(s32) = COPY %s0
165 ; CHECK-NEXT: %1:gpr(s32) = COPY %w0
164 ; CHECK: %0:fpr(s32) = COPY $s0
165 ; CHECK-NEXT: %1:gpr(s32) = COPY $w0
166166 ; CHECK-NEXT: %3:gpr(s32) = COPY %0
167167 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %3, %1
168 %0(s32) = COPY %s0
169 %1(s32) = COPY %w0
168 %0(s32) = COPY $s0
169 %1(s32) = COPY $w0
170170 %2(s32) = G_ADD %0, %1
171171 ...
172172
178178 - { id: 1, class: _ }
179179 body: |
180180 bb.0.entry:
181 liveins: %s0, %x0
181 liveins: $s0, $x0
182182 ; CHECK-LABEL: name: defaultMapping2Repairs
183 ; CHECK: %0:fpr(s32) = COPY %s0
183 ; CHECK: %0:fpr(s32) = COPY $s0
184184 ; CHECK-NEXT: %2:gpr(s32) = COPY %0
185185 ; CHECK-NEXT: %3:gpr(s32) = COPY %0
186186 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %2, %3
187 %0(s32) = COPY %s0
187 %0(s32) = COPY $s0
188188 %1(s32) = G_ADD %0, %0
189189 ...
190190
200200 - { id: 1, class: fpr }
201201 body: |
202202 bb.0.entry:
203 liveins: %w0
203 liveins: $w0
204204 ; CHECK-LABEL: name: defaultMappingDefRepair
205 ; CHECK: %0:gpr(s32) = COPY %w0
205 ; CHECK: %0:gpr(s32) = COPY $w0
206206 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %0
207207 ; CHECK-NEXT: %1:fpr(s32) = COPY %2
208 %0(s32) = COPY %w0
208 %0(s32) = COPY $w0
209209 %1(s32) = G_ADD %0, %0
210210 ...
211211
230230 body: |
231231 bb.0.entry:
232232 successors: %bb.2.end, %bb.1.then
233 liveins: %x0, %x1, %w2
234
235 %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src)
233 liveins: $x0, $x1, $w2
234
235 %0 = LDRWui killed $x0, 0 :: (load 4 from %ir.src)
236236 %5(s32) = COPY %0
237 %1(p0) = COPY %x1
238 %2 = COPY %w2
237 %1(p0) = COPY $x1
238 %2 = COPY $w2
239239 TBNZW killed %2, 0, %bb.2.end
240240
241241 bb.1.then:
258258 - { id: 2, class: _ }
259259 body: |
260260 bb.0.entry:
261 liveins: %w0, %s0
261 liveins: $w0, $s0
262262 ; CHECK-LABEL: name: defaultMappingUseRepairPhysReg
263 ; CHECK: %0:gpr(s32) = COPY %w0
264 ; CHECK-NEXT: %1:fpr(s32) = COPY %s0
263 ; CHECK: %0:gpr(s32) = COPY $w0
264 ; CHECK-NEXT: %1:fpr(s32) = COPY $s0
265265 ; CHECK-NEXT: %3:gpr(s32) = COPY %1
266266 ; CHECK-NEXT: %2:gpr(s32) = G_ADD %0, %3
267 %0(s32) = COPY %w0
268 %1(s32) = COPY %s0
267 %0(s32) = COPY $w0
268 %1(s32) = COPY $s0
269269 %2(s32) = G_ADD %0, %1
270270 ...
271271
278278 - { id: 1, class: _ }
279279 body: |
280280 bb.0.entry:
281 liveins: %w0
281 liveins: $w0
282282 ; CHECK-LABEL: name: defaultMappingDefRepairPhysReg
283 ; CHECK: %0:gpr(s32) = COPY %w0
283 ; CHECK: %0:gpr(s32) = COPY $w0
284284 ; CHECK-NEXT: %1:gpr(s32) = G_ADD %0, %0
285 ; CHECK-NEXT: %s0 = COPY %1
286 %0(s32) = COPY %w0
285 ; CHECK-NEXT: $s0 = COPY %1
286 %0(s32) = COPY $w0
287287 %1(s32) = G_ADD %0, %0
288 %s0 = COPY %1
288 $s0 = COPY %1
289289 ...
290290
291291 ---
299299 - { id: 2, class: _ }
300300 body: |
301301 bb.0.entry:
302 liveins: %x0, %x1
303 ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
304 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
302 liveins: $x0, $x1
303 ; CHECK: %0:gpr(<2 x s32>) = COPY $x0
304 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
305305
306306 ; Fast mode tries to reuse the source of the copy for the destination.
307307 ; Now, the default mapping says that %0 and %1 need to be in FPR.
313313
314314 ; Greedy mode remapped the instruction on the GPR bank.
315315 ; GREEDY-NEXT: %2:gpr(<2 x s32>) = G_OR %0, %1
316 %0(<2 x s32>) = COPY %x0
317 %1(<2 x s32>) = COPY %x1
316 %0(<2 x s32>) = COPY $x0
317 %1(<2 x s32>) = COPY $x1
318318 %2(<2 x s32>) = G_OR %0, %1
319319 ...
320320
330330 - { id: 2, class: fpr }
331331 body: |
332332 bb.0.entry:
333 liveins: %x0, %x1
333 liveins: $x0, $x1
334334 ; CHECK-LABEL: name: greedyMappingOrWithConstraints
335335
336 ; CHECK: %0:gpr(<2 x s32>) = COPY %x0
337 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY %x1
336 ; CHECK: %0:gpr(<2 x s32>) = COPY $x0
337 ; CHECK-NEXT: %1:gpr(<2 x s32>) = COPY $x1
338338
339339 ; Fast mode tries to reuse the source of the copy for the destination.
340340 ; Now, the default mapping says that %0 and %1 need to be in FPR.
348348 ; GREEDY-NEXT: %3:gpr(<2 x s32>) = G_OR %0, %1
349349 ; We need to keep %2 into FPR because we do not know anything about it.
350350 ; GREEDY-NEXT: %2:fpr(<2 x s32>) = COPY %3
351 %0(<2 x s32>) = COPY %x0
352 %1(<2 x s32>) = COPY %x1
351 %0(<2 x s32>) = COPY $x0
352 %1(<2 x s32>) = COPY $x1
353353 %2(<2 x s32>) = G_OR %0, %1
354354 ...
355355
365365 - { id: 1, class: gpr64 }
366366 body: |
367367 bb.0:
368 liveins: %x0
369
370 ; CHECK: %0:gpr64 = COPY %x0
368 liveins: $x0
369
370 ; CHECK: %0:gpr64 = COPY $x0
371371 ; CHECK-NEXT: %1:gpr64 = ADDXrr %0, %0
372 ; CHECK-NEXT: %x0 = COPY %1
373 ; CHECK-NEXT: RET_ReallyLR implicit %x0
374
375 %0 = COPY %x0
372 ; CHECK-NEXT: $x0 = COPY %1
373 ; CHECK-NEXT: RET_ReallyLR implicit $x0
374
375 %0 = COPY $x0
376376 %1 = ADDXrr %0, %0
377 %x0 = COPY %1
378 RET_ReallyLR implicit %x0
377 $x0 = COPY %1
378 RET_ReallyLR implicit $x0
379379 ...
380380
381381 ---
403403 - { id: 1, class: _ }
404404
405405 # CHECK: body:
406 # CHECK: %0:gpr(s32) = COPY %w0
406 # CHECK: %0:gpr(s32) = COPY $w0
407407 # CHECK: %1:gpr(s32) = G_BITCAST %0
408408 body: |
409409 bb.0:
410 liveins: %w0
411
412 %0(s32) = COPY %w0
410 liveins: $w0
411
412 %0(s32) = COPY $w0
413413 %1(s32) = G_BITCAST %0
414414 ...
415415
426426 - { id: 1, class: _ }
427427
428428 # CHECK: body:
429 # CHECK: %0:fpr(<2 x s16>) = COPY %s0
429 # CHECK: %0:fpr(<2 x s16>) = COPY $s0
430430 # CHECK: %1:fpr(<2 x s16>) = G_BITCAST %0
431431 body: |
432432 bb.0:
433 liveins: %s0
434
435 %0(<2 x s16>) = COPY %s0
433 liveins: $s0
434
435 %0(<2 x s16>) = COPY $s0
436436 %1(<2 x s16>) = G_BITCAST %0
437437 ...
438438
450450 - { id: 1, class: _ }
451451
452452 # CHECK: body:
453 # CHECK: %0:gpr(s32) = COPY %w0
453 # CHECK: %0:gpr(s32) = COPY $w0
454454 # FAST: %1:fpr(<2 x s16>) = G_BITCAST %0
455455 # GREEDY: %1:gpr(<2 x s16>) = G_BITCAST %0
456456 body: |
457457 bb.0:
458 liveins: %w0
459
460 %0(s32) = COPY %w0
458 liveins: $w0
459
460 %0(s32) = COPY $w0
461461 %1(<2 x s16>) = G_BITCAST %0
462462 ...
463463
469469 - { id: 0, class: _ }
470470 - { id: 1, class: _ }
471471 # CHECK: body:
472 # CHECK: %0:fpr(<2 x s16>) = COPY %s0
472 # CHECK: %0:fpr(<2 x s16>) = COPY $s0
473473 # FAST: %1:gpr(s32) = G_BITCAST %0
474474 # GREEDY: %1:fpr(s32) = G_BITCAST %0
475475 body: |
476476 bb.0:
477 liveins: %s0
478
479 %0(<2 x s16>) = COPY %s0
477 liveins: $s0
478
479 %0(<2 x s16>) = COPY $s0
480480 %1(s32) = G_BITCAST %0
481481 ...
482482
488488 - { id: 0, class: _ }
489489 - { id: 1, class: _ }
490490 # CHECK: body:
491 # CHECK: %0:gpr(s64) = COPY %x0
491 # CHECK: %0:gpr(s64) = COPY $x0
492492 # CHECK: %1:gpr(s64) = G_BITCAST %0
493493 body: |
494494 bb.0:
495 liveins: %x0
496
497 %0(s64) = COPY %x0
495 liveins: $x0
496
497 %0(s64) = COPY $x0
498498 %1(s64) = G_BITCAST %0
499499 ...
500500
506506 - { id: 0, class: _ }
507507 - { id: 1, class: _ }
508508 # CHECK: body:
509 # CHECK: %0:fpr(<2 x s32>) = COPY %d0
509 # CHECK: %0:fpr(<2 x s32>) = COPY $d0
510510 # CHECK: %1:fpr(<2 x s32>) = G_BITCAST %0
511511 body: |
512512 bb.0:
513 liveins: %d0
514
515 %0(<2 x s32>) = COPY %d0
513 liveins: $d0
514
515 %0(<2 x s32>) = COPY $d0
516516 %1(<2 x s32>) = G_BITCAST %0
517517 ...
518518
524524 - { id: 0, class: _ }
525525 - { id: 1, class: _ }
526526 # CHECK: body:
527 # CHECK: %0:gpr(s64) = COPY %x0
527 # CHECK: %0:gpr(s64) = COPY $x0
528528 # FAST: %1:fpr(<2 x s32>) = G_BITCAST %0
529529 # GREEDY: %1:gpr(<2 x s32>) = G_BITCAST %0
530530 body: |
531531 bb.0:
532 liveins: %x0
533
534 %0(s64) = COPY %x0
532 liveins: $x0
533
534 %0(s64) = COPY $x0
535535 %1(<2 x s32>) = G_BITCAST %0
536536 ...
537537
543543 - { id: 0, class: _ }
544544 - { id: 1, class: _ }
545545 # CHECK: body:
546 # CHECK: %0:fpr(<2 x s32>) = COPY %d0
546 # CHECK: %0:fpr(<2 x s32>) = COPY $d0
547547 # FAST: %1:gpr(s64) = G_BITCAST %0
548548 # GREEDY: %1:fpr(s64) = G_BITCAST %0
549549 body: |
550550 bb.0:
551 liveins: %d0
552
553 %0(<2 x s32>) = COPY %d0
551 liveins: $d0
552
553 %0(<2 x s32>) = COPY $d0
554554 %1(s64) = G_BITCAST %0
555555 ...
556556
568568 # CHECK: %2:fpr(<2 x s64>) = G_BITCAST %3(s128)
569569 body: |
570570 bb.1:
571 liveins: %x0, %x1
572 %0(s64) = COPY %x0
573 %1(s64) = COPY %x1
571 liveins: $x0, $x1
572 %0(s64) = COPY $x0
573 %1(s64) = COPY $x1
574574 %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
575575 %2(<2 x s64>) = G_BITCAST %3(s128)
576 %q0 = COPY %2(<2 x s64>)
577 RET_ReallyLR implicit %q0
576 $q0 = COPY %2(<2 x s64>)
577 RET_ReallyLR implicit $q0
578578
579579 ...
580580
597597 # CHECK-NEXT: %2:fpr(<2 x s64>) = G_BITCAST %4(s128)
598598 body: |
599599 bb.1:
600 liveins: %x0, %x1
601 %0(s64) = COPY %x0
602 %1(s64) = COPY %x1
600 liveins: $x0, $x1
601 %0(s64) = COPY $x0
602 %1(s64) = COPY $x1
603603 %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
604604 %4(s128) = COPY %3(s128)
605605 %2(<2 x s64>) = G_BITCAST %4(s128)
606 %q0 = COPY %2(<2 x s64>)
607 RET_ReallyLR implicit %q0
606 $q0 = COPY %2(<2 x s64>)
607 RET_ReallyLR implicit $q0
608608
609609 ...
610610
629629 # CHECK: %1:fpr(s128) = COPY %0
630630 body: |
631631 bb.1:
632 liveins: %x0
633 %0 = LDRQui killed %x0, 0
632 liveins: $x0
633 %0 = LDRQui killed $x0, 0
634634 %1(s128) = COPY %0
635 %q0 = COPY %1(s128)
636 RET_ReallyLR implicit %q0
635 $q0 = COPY %1(s128)
636 RET_ReallyLR implicit $q0
637637
638638 ...
639639
653653 # CHECK: registers:
654654 # CHECK: - { id: 0, class: gpr, preferred-register: '' }
655655 # CHECK: - { id: 1, class: gpr, preferred-register: '' }
656 # CHECK: %0:gpr(s32) = COPY %w0
656 # CHECK: %0:gpr(s32) = COPY $w0
657657 # CHECK-NEXT: %1:gpr(s16) = G_TRUNC %0(s32)
658658 body: |
659659 bb.1:
660 liveins: %w0
661 %0(s32) = COPY %w0
660 liveins: $w0
661 %0(s32) = COPY $w0
662662 %1(s16) = G_TRUNC %0(s32)
663 %h0 = COPY %1(s16)
664 RET_ReallyLR implicit %h0
663 $h0 = COPY %1(s16)
664 RET_ReallyLR implicit $h0
665665
666666 ...
667667
681681 - { id: 4, class: _ }
682682 - { id: 5, class: _ }
683683 # No repairing should be necessary for both modes.
684 # CHECK: %0:gpr(s64) = COPY %x0
685 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
684 # CHECK: %0:gpr(s64) = COPY $x0
685 # CHECK-NEXT: %1:gpr(p0) = COPY $x1
686686 # FAST-NEXT: %2:fpr(<2 x s32>) = G_BITCAST %0(s64)
687687 # FAST-NEXT: %3:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
688688 # FAST-NEXT: %4:fpr(<2 x s32>) = G_OR %2, %3
690690 # GREEDY-NEXT: %3:gpr(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
691691 # GREEDY-NEXT: %4:gpr(<2 x s32>) = G_OR %2, %3
692692 # CHECK-NEXT: %5:gpr(s64) = G_BITCAST %4(<2 x s32>)
693 # CHECK-NEXT: %x0 = COPY %5(s64)
694 # CHECK-NEXT: RET_ReallyLR implicit %x0
695 body: |
696 bb.0:
697 liveins: %x0, %x1
698
699 %0(s64) = COPY %x0
700 %1(p0) = COPY %x1
693 # CHECK-NEXT: $x0 = COPY %5(s64)
694 # CHECK-NEXT: RET_ReallyLR implicit $x0
695 body: |
696 bb.0:
697 liveins: $x0, $x1
698
699 %0(s64) = COPY $x0
700 %1(p0) = COPY $x1
701701 %2(<2 x s32>) = G_BITCAST %0(s64)
702702 %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
703703 %4(<2 x s32>) = G_OR %2, %3
704704 %5(s64) = G_BITCAST %4(<2 x s32>)
705 %x0 = COPY %5(s64)
706 RET_ReallyLR implicit %x0
705 $x0 = COPY %5(s64)
706 RET_ReallyLR implicit $x0
707707
708708 ...
709709
727727 - { id: 3, class: _ }
728728
729729 # No repairing should be necessary for both modes.
730 # CHECK: %0:gpr(s64) = COPY %x0
731 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
730 # CHECK: %0:gpr(s64) = COPY $x0
731 # CHECK-NEXT: %1:gpr(p0) = COPY $x1
732732 # CHECK-NEXT: %2:fpr(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
733733 # %0 has been mapped to GPR, we need to repair to match FPR.
734734 # CHECK-NEXT: %4:fpr(s64) = COPY %0
735735 # CHECK-NEXT: %3:fpr(s64) = G_FADD %4, %2
736 # CHECK-NEXT: %x0 = COPY %3(s64)
737 # CHECK-NEXT: RET_ReallyLR implicit %x0
738
739 body: |
740 bb.0:
741 liveins: %x0, %x1
742
743 %0(s64) = COPY %x0
744 %1(p0) = COPY %x1
736 # CHECK-NEXT: $x0 = COPY %3(s64)
737 # CHECK-NEXT: RET_ReallyLR implicit $x0
738
739 body: |
740 bb.0:
741 liveins: $x0, $x1
742
743 %0(s64) = COPY $x0
744 %1(p0) = COPY $x1
745745 %2(s64) = G_LOAD %1(p0) :: (load 8 from %ir.addr)
746746 %3(s64) = G_FADD %0, %2
747 %x0 = COPY %3(s64)
748 RET_ReallyLR implicit %x0
747 $x0 = COPY %3(s64)
748 RET_ReallyLR implicit $x0
749749
750750 ...
751751
767767 - { id: 1, class: _ }
768768 - { id: 2, class: _ }
769769
770 # CHECK: %0:gpr(s64) = COPY %x0
771 # CHECK-NEXT: %1:gpr(p0) = COPY %x1
770 # CHECK: %0:gpr(s64) = COPY $x0
771 # CHECK-NEXT: %1:gpr(p0) = COPY $x1
772772 # %0 has been mapped to GPR, we need to repair to match FPR.
773773 # CHECK-NEXT: %3:fpr(s64) = COPY %0
774774 # CHECK-NEXT: %4:fpr(s64) = COPY %0
778778
779779 body: |
780780 bb.0:
781 liveins: %x0, %x1
782
783 %0(s64) = COPY %x0
784 %1(p0) = COPY %x1
781 liveins: $x0, $x1
782
783 %0(s64) = COPY $x0
784 %1(p0) = COPY $x1
785785 %2(s64) = G_FADD %0, %0
786786 G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
787787 RET_ReallyLR
803803 - { id: 0, class: _ }
804804 - { id: 1, class: _ }
805805 - { id: 2, class: _ }
806 # CHECK: %1:gpr(s32) = COPY %w0
806 # CHECK: %1:gpr(s32) = COPY $w0
807807 # CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
808808 # %0 has been mapped to GPR, we need to repair to match FPR.
809809 # CHECK-NEXT: %3:fpr(s16) = COPY %0
810810 # CHECK-NEXT: %2:fpr(s32) = G_FPEXT %3
811 # CHECK-NEXT: %s0 = COPY %2
811 # CHECK-NEXT: $s0 = COPY %2
812812 # CHECK-NEXT: RET_ReallyLR
813813
814814 body: |
815815 bb.1:
816 liveins: %w0
817
818 %1(s32) = COPY %w0
816 liveins: $w0
817
818 %1(s32) = COPY $w0
819819 %0(s16) = G_TRUNC %1(s32)
820820 %2(s32) = G_FPEXT %0(s16)
821 %s0 = COPY %2(s32)
822 RET_ReallyLR implicit %s0
821 $s0 = COPY %2(s32)
822 RET_ReallyLR implicit $s0
823823
824824 ...
825825
838838 - { id: 0, class: _ }
839839 - { id: 1, class: _ }
840840 - { id: 2, class: _ }
841 # CHECK: %1:gpr(s32) = COPY %w0
841 # CHECK: %1:gpr(s32) = COPY $w0
842842 # CHECK-NEXT: %0:gpr(s16) = G_TRUNC %1
843843 # %0 has been mapped to GPR, we need to repair to match FPR.
844844 # CHECK-NEXT: %3:fpr(s16) = COPY %0
845845 # CHECK-NEXT: %2:fpr(s64) = G_FPEXT %3
846 # CHECK-NEXT: %d0 = COPY %2
846 # CHECK-NEXT: $d0 = COPY %2
847847 # CHECK-NEXT: RET_ReallyLR
848848
849849 body: |
850850 bb.1:
851 liveins: %w0
852
853 %1(s32) = COPY %w0
851 liveins: $w0
852
853 %1(s32) = COPY $w0
854854 %0(s16) = G_TRUNC %1(s32)
855855 %2(s64) = G_FPEXT %0(s16)
856 %d0 = COPY %2(s64)
857 RET_ReallyLR implicit %d0
856 $d0 = COPY %2(s64)
857 RET_ReallyLR implicit $d0
858858
859859 ...
860860
871871 registers:
872872 - { id: 0, class: _ }
873873 - { id: 1, class: _ }
874 # CHECK: %0:gpr(s32) = COPY %w0
874 # CHECK: %0:gpr(s32) = COPY $w0
875875 # %0 has been mapped to GPR, we need to repair to match FPR.
876876 # CHECK-NEXT: %2:fpr(s32) = COPY %0
877877 # CHECK-NEXT: %1:fpr(s64) = G_FPEXT %2
878 # CHECK-NEXT: %d0 = COPY %1
878 # CHECK-NEXT: $d0 = COPY %1
879879 # CHECK-NEXT: RET_ReallyLR
880880 body: |
881881 bb.1:
882 liveins: %w0
883
884 %0(s32) = COPY %w0
882 liveins: $w0
883
884 %0(s32) = COPY $w0
885885 %1(s64) = G_FPEXT %0(s32)
886 %d0 = COPY %1(s64)
887 RET_ReallyLR implicit %d0
886 $d0 = COPY %1(s64)
887 RET_ReallyLR implicit $d0
888888
889889 ...
890890
893893 # CHECK-LABEL: name: passFp16
894894 # CHECK: registers:
895895 # CHECK: - { id: 0, class: fpr, preferred-register: '' }
896 # CHECK: %0:fpr(s16) = COPY %h0
897 # CHECK-NEXT: %h0 = COPY %0(s16)
896 # CHECK: %0:fpr(s16) = COPY $h0
897 # CHECK-NEXT: $h0 = COPY %0(s16)
898898 name: passFp16
899899 alignment: 2
900900 legalized: true
902902 - { id: 0, class: _ }
903903 body: |
904904 bb.1.entry:
905 liveins: %h0
906
907 %0(s16) = COPY %h0
908 %h0 = COPY %0(s16)
909 RET_ReallyLR implicit %h0
905 liveins: $h0
906
907 %0(s16) = COPY $h0
908 $h0 = COPY %0(s16)
909 RET_ReallyLR implicit $h0
910910
911911 ...
912912 ---
918918 # CHECK: - { id: 1, class: gpr, preferred-register: '' }
919919 # CHECK: - { id: 2, class: fpr, preferred-register: '' }
920920 #
921 # CHECK: %0:fpr(s16) = COPY %h0
921 # CHECK: %0:fpr(s16) = COPY $h0
922922 # CHECK-NEXT: %1:gpr(p0) = G_FRAME_INDEX %stack.0.p.addr
923923 # If we didn't look through the copy for %0, the default mapping
924924 # would have been on GPR and we would have to insert a copy to move
928928 # would have been on GPR and we would have to insert a copy to move
929929 # the value to FPR (h0).
930930 # CHECK-NEXT: %2:fpr(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
931 # CHECK-NEXT: %h0 = COPY %2(s16)
931 # CHECK-NEXT: $h0 = COPY %2(s16)
932932 name: passFp16ViaAllocas
933933 alignment: 2
934934 legalized: true
943943 - { id: 0, name: p.addr, size: 2, alignment: 2, stack-id: 0 }
944944 body: |
945945 bb.1.entry:
946 liveins: %h0
947
948 %0(s16) = COPY %h0
946 liveins: $h0
947
948 %0(s16) = COPY $h0
949949 %1(p0) = G_FRAME_INDEX %stack.0.p.addr
950950 G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p.addr)
951951 %2(s16) = G_LOAD %1(p0) :: (load 2 from %ir.p.addr)
952 %h0 = COPY %2(s16)
953 RET_ReallyLR implicit %h0
954
955 ...
952 $h0 = COPY %2(s16)
953 RET_ReallyLR implicit $h0
954
955 ...
1010 ; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0)
1111 ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
1212 ; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
13 ; CHECK: %w0 = COPY [[SUM32]](s32)
13 ; CHECK: $w0 = COPY [[SUM32]](s32)
1414 define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
1515 %sum = add i8 %lhs, %rhs
1616 ret i8 %sum
1919 ; CHECK-LABEL: name: test_call_stack
2020 ; CHECK: [[C42:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
2121 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
22 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
22 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
2323 ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
2424 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
2525 ; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0)
26 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
26 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
2727 ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
2828 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
2929 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0)
3434 }
3535
3636 ; CHECK-LABEL: name: test_128bit_struct
37 ; CHECK: %x0 = COPY
38 ; CHECK: %x1 = COPY
39 ; CHECK: %x2 = COPY
37 ; CHECK: $x0 = COPY
38 ; CHECK: $x1 = COPY
39 ; CHECK: $x2 = COPY
4040 ; CHECK: BL @take_128bit_struct
4141 define void @test_128bit_struct([2 x i64]* %ptr) {
4242 %struct = load [2 x i64], [2 x i64]* %ptr
4545 }
4646
4747 ; CHECK-LABEL: name: take_128bit_struct
48 ; CHECK: {{%.*}}:_(p0) = COPY %x0
49 ; CHECK: {{%.*}}:_(s64) = COPY %x1
50 ; CHECK: {{%.*}}:_(s64) = COPY %x2
48 ; CHECK: {{%.*}}:_(p0) = COPY $x0
49 ; CHECK: {{%.*}}:_(s64) = COPY $x1
50 ; CHECK: {{%.*}}:_(s64) = COPY $x2
5151 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
5252 store [2 x i64] %in, [2 x i64]* %ptr
5353 ret void
5858 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
5959 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
6060
61 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
61 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
6262 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
6363 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
6464 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
6565
66 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
66 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
6767 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
6868 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
6969 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
0 ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
11
22 ; CHECK-LABEL: name: test_trivial_call
3 ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
4 ; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def %lr
5 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
3 ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
4 ; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def $lr
5 ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
66 declare void @trivial_callee()
77 define void @test_trivial_call() {
88 call void @trivial_callee()
1010 }
1111
1212 ; CHECK-LABEL: name: test_simple_return
13 ; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0
14 ; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY %x0
15 ; CHECK: %x0 = COPY [[RES]]
16 ; CHECK: RET_ReallyLR implicit %x0
13 ; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
14 ; CHECK: [[RES:%[0-9]+]]:_(s64) = COPY $x0
15 ; CHECK: $x0 = COPY [[RES]]
16 ; CHECK: RET_ReallyLR implicit $x0
1717 declare i64 @simple_return_callee()
1818 define i64 @test_simple_return() {
1919 %res = call i64 @simple_return_callee()
2121 }
2222
2323 ; CHECK-LABEL: name: test_simple_arg
24 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
25 ; CHECK: %w0 = COPY [[IN]]
26 ; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
24 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
25 ; CHECK: $w0 = COPY [[IN]]
26 ; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
2727 ; CHECK: RET_ReallyLR
2828 declare void @simple_arg_callee(i32 %in)
2929 define void @test_simple_arg(i32 %in) {
3535 ; CHECK: registers:
3636 ; Make sure the register feeding the indirect call is properly constrained.
3737 ; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64, preferred-register: '' }
38 ; CHECK: %[[FUNC]]:gpr64(p0) = COPY %x0
39 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp
38 ; CHECK: %[[FUNC]]:gpr64(p0) = COPY $x0
39 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def $lr, implicit $sp
4040 ; CHECK: RET_ReallyLR
4141 define void @test_indirect_call(void()* %func) {
4242 call void %func()
4444 }
4545
4646 ; CHECK-LABEL: name: test_multiple_args
47 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY %x0
47 ; CHECK: [[IN:%[0-9]+]]:_(s64) = COPY $x0
4848 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
49 ; CHECK: %w0 = COPY [[ANSWER]]
50 ; CHECK: %x1 = COPY [[IN]]
51 ; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1
49 ; CHECK: $w0 = COPY [[ANSWER]]
50 ; CHECK: $x1 = COPY [[IN]]
51 ; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $x1
5252 ; CHECK: RET_ReallyLR
5353 declare void @multiple_args_callee(i32, i64)
5454 define void @test_multiple_args(i64 %in) {
5858
5959
6060 ; CHECK-LABEL: name: test_struct_formal
61 ; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY %d0
62 ; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY %x0
63 ; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY %w1
61 ; CHECK: [[DBL:%[0-9]+]]:_(s64) = COPY $d0
62 ; CHECK: [[I64:%[0-9]+]]:_(s64) = COPY $x0
63 ; CHECK: [[I8_C:%[0-9]+]]:_(s32) = COPY $w1
6464 ; CHECK: [[I8:%[0-9]+]]:_(s8) = G_TRUNC [[I8_C]]
65 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x2
65 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x2
6666
6767 ; CHECK: [[UNDEF:%[0-9]+]]:_(s192) = G_IMPLICIT_DEF
6868 ; CHECK: [[ARG0:%[0-9]+]]:_(s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0
7979
8080
8181 ; CHECK-LABEL: name: test_struct_return
82 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY %x0
82 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
8383 ; CHECK: [[VAL:%[0-9]+]]:_(s192) = G_LOAD [[ADDR]](p0)
8484
8585 ; CHECK: [[DBL:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 0
8686 ; CHECK: [[I64:%[0-9]+]]:_(s64) = G_EXTRACT [[VAL]](s192), 64
8787 ; CHECK: [[I32:%[0-9]+]]:_(s32) = G_EXTRACT [[VAL]](s192), 128
8888
89 ; CHECK: %d0 = COPY [[DBL]](s64)
90 ; CHECK: %x0 = COPY [[I64]](s64)
91 ; CHECK: %w1 = COPY [[I32]](s32)
92 ; CHECK: RET_ReallyLR implicit %d0, implicit %x0, implicit %w1
89 ; CHECK: $d0 = COPY [[DBL]](s64)
90 ; CHECK: $x0 = COPY [[I64]](s64)
91 ; CHECK: $w1 = COPY [[I32]](s32)
92 ; CHECK: RET_ReallyLR implicit $d0, implicit $x0, implicit $w1
9393 define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) {
9494 %val = load {double, i64, i32}, {double, i64, i32}* %addr
9595 ret {double, i64, i32} %val
104104 ; CHECK: [[E2:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 128
105105 ; CHECK: [[E3:%[0-9]+]]:_(s64) = G_EXTRACT [[ARG]](s256), 192
106106
107 ; CHECK: %x0 = COPY [[E0]](s64)
108 ; CHECK: %x1 = COPY [[E1]](s64)
109 ; CHECK: %x2 = COPY [[E2]](s64)
110 ; CHECK: %x3 = COPY [[E3]](s64)
111 ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3
112 ; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY %x0
113 ; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY %x1
114 ; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY %x2
115 ; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY %x3
107 ; CHECK: $x0 = COPY [[E0]](s64)
108 ; CHECK: $x1 = COPY [[E1]](s64)
109 ; CHECK: $x2 = COPY [[E2]](s64)
110 ; CHECK: $x3 = COPY [[E3]](s64)
111 ; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1, implicit-def $x2, implicit-def $x3
112 ; CHECK: [[E0:%[0-9]+]]:_(s64) = COPY $x0
113 ; CHECK: [[E1:%[0-9]+]]:_(s64) = COPY $x1
114 ; CHECK: [[E2:%[0-9]+]]:_(s64) = COPY $x2
115 ; CHECK: [[E3:%[0-9]+]]:_(s64) = COPY $x3
116116 ; CHECK: [[RES:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[E0]](s64), [[E1]](s64), [[E2]](s64), [[E3]](s64)
117117 ; CHECK: G_EXTRACT [[RES]](s256), 64
118118 declare [4 x i64] @arr_callee([4 x i64])
127127 ; CHECK-LABEL: name: test_abi_exts_call
128128 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
129129 ; CHECK: [[VAL_TMP:%[0-9]+]]:_(s32) = G_ANYEXT [[VAL]]
130 ; CHECK: %w0 = COPY [[VAL_TMP]]
131 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
130 ; CHECK: $w0 = COPY [[VAL_TMP]]
131 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
132132 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
133 ; CHECK: %w0 = COPY [[SVAL]](s32)
134 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
133 ; CHECK: $w0 = COPY [[SVAL]](s32)
134 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
135135 ; CHECK: [[ZVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
136 ; CHECK: %w0 = COPY [[ZVAL]](s32)
137 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0
136 ; CHECK: $w0 = COPY [[ZVAL]](s32)
137 ; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
138138 declare void @take_char(i8)
139139 define void @test_abi_exts_call(i8* %addr) {
140140 %val = load i8, i8* %addr
147147 ; CHECK-LABEL: name: test_abi_sext_ret
148148 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
149149 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_SEXT [[VAL]](s8)
150 ; CHECK: %w0 = COPY [[SVAL]](s32)
151 ; CHECK: RET_ReallyLR implicit %w0
150 ; CHECK: $w0 = COPY [[SVAL]](s32)
151 ; CHECK: RET_ReallyLR implicit $w0
152152 define signext i8 @test_abi_sext_ret(i8* %addr) {
153153 %val = load i8, i8* %addr
154154 ret i8 %val
157157 ; CHECK-LABEL: name: test_abi_zext_ret
158158 ; CHECK: [[VAL:%[0-9]+]]:_(s8) = G_LOAD
159159 ; CHECK: [[SVAL:%[0-9]+]]:_(s32) = G_ZEXT [[VAL]](s8)
160 ; CHECK: %w0 = COPY [[SVAL]](s32)
161 ; CHECK: RET_ReallyLR implicit %w0
160 ; CHECK: $w0 = COPY [[SVAL]](s32)
161 ; CHECK: RET_ReallyLR implicit $w0
162162 define zeroext i8 @test_abi_zext_ret(i8* %addr) {
163163 %val = load i8, i8* %addr
164164 ret i8 %val
187187 ; CHECK: [[C42:%[0-9]+]]:_(s64) = G_CONSTANT i64 42
188188 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
189189 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
190 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
191 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
190 ; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def $sp, implicit $sp
191 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
192192 ; CHECK: [[C42_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
193193 ; CHECK: [[C42_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
194194 ; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0)
195 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
195 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
196196 ; CHECK: [[C12_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
197197 ; CHECK: [[C12_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[C12_OFFS]](s64)
198198 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0)
199 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
199 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
200200 ; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
201201 ; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[PTR_OFFS]](s64)
202202 ; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0)
203203 ; CHECK: BL @test_stack_slots
204 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp
204 ; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
205205 define void @test_call_stack() {
206206 call void @test_stack_slots([8 x i64] undef, i64 42, i64 12, i64* null)
207207 ret void
218218 }
219219
220220 ; CHECK-LABEL: name: test_128bit_struct
221 ; CHECK: %x0 = COPY
222 ; CHECK: %x1 = COPY
223 ; CHECK: %x2 = COPY
221 ; CHECK: $x0 = COPY
222 ; CHECK: $x1 = COPY
223 ; CHECK: $x2 = COPY
224224 ; CHECK: BL @take_128bit_struct
225225 define void @test_128bit_struct([2 x i64]* %ptr) {
226226 %struct = load [2 x i64], [2 x i64]* %ptr
229229 }
230230
231231 ; CHECK-LABEL: name: take_128bit_struct
232 ; CHECK: {{%.*}}:_(p0) = COPY %x0
233 ; CHECK: {{%.*}}:_(s64) = COPY %x1
234 ; CHECK: {{%.*}}:_(s64) = COPY %x2
232 ; CHECK: {{%.*}}:_(p0) = COPY $x0
233 ; CHECK: {{%.*}}:_(s64) = COPY $x1
234 ; CHECK: {{%.*}}:_(s64) = COPY $x2
235235 define void @take_128bit_struct([2 x i64]* %ptr, [2 x i64] %in) {
236236 store [2 x i64] %in, [2 x i64]* %ptr
237237 ret void
242242 ; CHECK: [[LO:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 0
243243 ; CHECK: [[HI:%[0-9]+]]:_(s64) = G_EXTRACT [[STRUCT]](s128), 64
244244
245 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
245 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
246246 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
247247 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
248248 ; CHECK: G_STORE [[LO]](s64), [[ADDR]](p0) :: (store 8 into stack, align 0)
249249
250 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
250 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
251251 ; CHECK: [[OFF:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
252252 ; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF]]
253253 ; CHECK: G_STORE [[HI]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 0)
55 ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
66 ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
77 ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
8 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
8 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use $noreg, !11, !DIExpression(), debug-location !12
99 define void @debug_declare(i32 %in) #0 !dbg !7 {
1010 entry:
1111 %in.addr = alloca i32, align 4
1616 }
1717
1818 ; CHECK-LABEL: name: debug_declare_vla
19 ; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
19 ; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use $noreg, !14, !DIExpression(), debug-location !15
2020 define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
2121 entry:
2222 %vla.addr = alloca i32, i32 %in
2525 }
2626
2727 ; CHECK-LABEL: name: debug_value
28 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
28 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY $w0
2929 define void @debug_value(i32 %in) #0 !dbg !16 {
3030 %addr = alloca i32
31 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
31 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use $noreg, !17, !DIExpression(), debug-location !18
3232 call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
3333 store i32 %in, i32* %addr
34 ; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
34 ; CHECK: DBG_VALUE debug-use %1(p0), debug-use $noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
3535 call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
3636 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
3737 call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
3838 ; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
3939 call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
40 ; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
40 ; CHECK: DBG_VALUE $noreg, 0, !17, !DIExpression(), debug-location !18
4141 call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
4242 ret void
4343 }
0 ; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s
11
22 ; CHECK-LABEL: name: test_simple_alloca
3 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
3 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
44 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
55 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
66 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
7 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
7 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
88 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
99 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 4
10 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
10 ; CHECK: $sp = COPY [[ALIGNED_ALLOC]]
1111 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
12 ; CHECK: %x0 = COPY [[ALLOC]]
12 ; CHECK: $x0 = COPY [[ALLOC]]
1313 define i8* @test_simple_alloca(i32 %numelts) {
1414 %addr = alloca i8, i32 %numelts
1515 ret i8* %addr
1616 }
1717
1818 ; CHECK-LABEL: name: test_aligned_alloca
19 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
19 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
2020 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
2121 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
2222 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
23 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
23 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
2424 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
2525 ; CHECK: [[ALIGNED_ALLOC:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALLOC]], 5
26 ; CHECK: %sp = COPY [[ALIGNED_ALLOC]]
26 ; CHECK: $sp = COPY [[ALIGNED_ALLOC]]
2727 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = COPY [[ALIGNED_ALLOC]]
28 ; CHECK: %x0 = COPY [[ALLOC]]
28 ; CHECK: $x0 = COPY [[ALLOC]]
2929 define i8* @test_aligned_alloca(i32 %numelts) {
3030 %addr = alloca i8, i32 %numelts, align 32
3131 ret i8* %addr
3232 }
3333
3434 ; CHECK-LABEL: name: test_natural_alloca
35 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY %w0
35 ; CHECK: [[NUMELTS:%[0-9]+]]:_(s32) = COPY $w0
3636 ; CHECK: [[TYPE_SIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
3737 ; CHECK: [[NUMELTS_64:%[0-9]+]]:_(s64) = G_ZEXT [[NUMELTS]](s32)
3838 ; CHECK: [[NUMBYTES:%[0-9]+]]:_(s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]]
39 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY %sp
39 ; CHECK: [[SP_TMP:%[0-9]+]]:_(p0) = COPY $sp
4040 ; CHECK: [[ALLOC:%[0-9]+]]:_(p0) = G_GEP [[SP_TMP]], [[NUMBYTES]]
41 ; CHECK: %sp = COPY [[ALLOC]]
41 ; CHECK: $sp = COPY [[ALLOC]]
4242 ; CHECK: [[ALLOC_TMP:%[0-9]+]]:_(p0) = COPY [[ALLOC]]
43 ; CHECK: %x0 = COPY [[ALLOC_TMP]]
43 ; CHECK: $x0 = COPY [[ALLOC_TMP]]
4444 define i128* @test_natural_alloca(i32 %numelts) {
4545 %addr = alloca i128, i32 %numelts
4646 ret i128* %addr
2727 di-variable: '', di-expression: '', di-location: '' }
2828 body: |
2929 bb.1.entry:
30 liveins: %q0
30 liveins: $q0
3131
3232 ; This test just checks we don't crash on G_FNEG of FP128 types. Expect to fall
3333 ; back until support is added for fp128.
3434 ; CHECK: ret
35 %0:_(s128) = COPY %q0
35 %0:_(s128) = COPY $q0
3636 %1:_(p0) = G_FRAME_INDEX %stack.0.a.addr
3737 G_STORE %0(s128), %1(p0) :: (store 16 into %ir.a.addr)
3838 %2:_(s128) = G_LOAD %1(p0) :: (load 16 from %ir.a.addr)
3939 %3:_(s128) = G_FNEG %2
40 %q0 = COPY %3(s128)
41 RET_ReallyLR implicit %q0
40 $q0 = COPY %3(s128)
41 RET_ReallyLR implicit $q0
4242
4343 ...
2323
2424 ; At this point we mapped 46 values. The 'i32 100' constant will grow the map.
2525 ; CHECK: %46:_(s32) = G_CONSTANT i32 100
26 ; CHECK: %w0 = COPY %46(s32)
26 ; CHECK: $w0 = COPY %46(s32)
2727 %res = bitcast i32 100 to i32
2828 ret i32 %res
2929 }
1010 ; CHECK-NEXT: bb.1 (%ir-block.0):
1111 ; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
1212 ; CHECK: EH_LABEL
13 ; CHECK: %w0 = COPY
14 ; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
15 ; CHECK: {{%[0-9]+}}:_(s32) = COPY %w0
13 ; CHECK: $w0 = COPY
14 ; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
15 ; CHECK: {{%[0-9]+}}:_(s32) = COPY $w0
1616 ; CHECK: EH_LABEL
1717 ; CHECK: G_BR %[[GOOD]]
1818
1919 ; CHECK: [[BAD]].{{[a-z]+}} (landing-pad):
2020 ; CHECK: EH_LABEL
2121 ; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
22 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
22 ; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY $x0
2323 ; CHECK: [[VAL_WITH_PTR:%[0-9]+]]:_(s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0
24 ; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY %x1
24 ; CHECK: [[SEL_PTR:%[0-9]+]]:_(p0) = COPY $x1
2525 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_PTRTOINT [[SEL_PTR]]
2626 ; CHECK: [[PTR_SEL:%[0-9]+]]:_(s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64
2727 ; CHECK: [[PTR_RET:%[0-9]+]]:_(s64) = G_EXTRACT [[PTR_SEL]](s128), 0
2828 ; CHECK: [[SEL_RET:%[0-9]+]]:_(s32) = G_EXTRACT [[PTR_SEL]](s128), 64
29 ; CHECK: %x0 = COPY [[PTR_RET]]
30 ; CHECK: %w1 = COPY [[SEL_RET]]
29 ; CHECK: $x0 = COPY [[PTR_RET]]
30 ; CHECK: $w1 = COPY [[SEL_RET]]
3131
3232 ; CHECK: [[GOOD]].{{[a-z]+}}:
3333 ; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
4848 }
4949
5050 ; CHECK-LABEL: name: test_invoke_indirect
51 ; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY %x0
51 ; CHECK: [[CALLEE:%[0-9]+]]:gpr64(p0) = COPY $x0
5252 ; CHECK: BLR [[CALLEE]]
5353 define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
5454 invoke void %callee() to label %continue unwind label %broken
6767 ; CHECK: [[ANSWER:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
6868 ; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.0
6969
70 ; CHECK: %x0 = COPY [[NULL]]
70 ; CHECK: $x0 = COPY [[NULL]]
7171
72 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
72 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
7373 ; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
7474 ; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
7575 ; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]]
7676
77 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
77 ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY $sp
7878 ; CHECK: [[OFFSET:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
7979 ; CHECK: [[SLOT:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFFSET]](s64)
8080 ; CHECK: G_STORE [[ONE]](s32), [[SLOT]]
2929 name: test_scalar_add_big
3030 body: |
3131 bb.0.entry:
32 liveins: %x0, %x1, %x2, %x3
32 liveins: $x0, $x1, $x2, $x3
3333
3434 ; CHECK-LABEL: name: test_scalar_add_big
35 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
36 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
37 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %x2
38 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY %x3
35 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
36 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
37 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
38 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
3939 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
4040 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
4141 ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
4242 ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
43 ; CHECK: %x0 = COPY [[UADDE]](s64)
44 ; CHECK: %x1 = COPY [[UADDE2]](s64)
45 %0:_(s64) = COPY %x0
46 %1:_(s64) = COPY %x1
47 %2:_(s64) = COPY %x2
48 %3:_(s64) = COPY %x3
43 ; CHECK: $x0 = COPY [[UADDE]](s64)
44 ; CHECK: $x1 = COPY [[UADDE2]](s64)
45 %0:_(s64) = COPY $x0
46 %1:_(s64) = COPY $x1
47 %2:_(s64) = COPY $x2
48 %3:_(s64) = COPY $x3
4949 %4:_(s128) = G_MERGE_VALUES %0, %1
5050 %5:_(s128) = G_MERGE_VALUES %2, %3
5151 %6:_(s128) = G_ADD %4, %5
5252 %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
53 %x0 = COPY %7
54 %x1 = COPY %8
53 $x0 = COPY %7
54 $x1 = COPY %8
5555 ...
5656
5757 ---
6969 - { id: 9, class: _ }
7070 body: |
7171 bb.0.entry:
72 liveins: %x0, %x1, %x2, %x3
72 liveins: $x0, $x1, $x2, $x3
7373 ; CHECK-LABEL: name: test_scalar_add_big_nonpow2
7474 ; CHECK-NOT: G_MERGE_VALUES
7575 ; CHECK-NOT: G_UNMERGE_VALUES
8080 ; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
8181 ; CHECK-NOT: G_MERGE_VALUES
8282 ; CHECK-NOT: G_UNMERGE_VALUES
83 ; CHECK: %x0 = COPY [[RES_LO]]
84 ; CHECK: %x1 = COPY [[RES_MI]]
85 ; CHECK: %x2 = COPY [[RES_HI]]
83 ; CHECK: $x0 = COPY [[RES_LO]]
84 ; CHECK: $x1 = COPY [[RES_MI]]
85 ; CHECK: $x2 = COPY [[RES_HI]]
8686
87 %0(s64) = COPY %x0
88 %1(s64) = COPY %x1
89 %2(s64) = COPY %x2
90 %3(s64) = COPY %x3
87 %0(s64) = COPY $x0
88 %1(s64) = COPY $x1
89 %2(s64) = COPY $x2
90 %3(s64) = COPY $x3
9191 %4(s192) = G_MERGE_VALUES %0, %1, %2
9292 %5(s192) = G_MERGE_VALUES %1, %2, %3
9393 %6(s192) = G_ADD %4, %5
9494 %7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
95 %x0 = COPY %7
96 %x1 = COPY %8
97 %x2 = COPY %9
95 $x0 = COPY %7
96 $x1 = COPY %8
97 $x2 = COPY %9
9898 ...
9999
100100 ---
101101 name: test_scalar_add_small
102102 body: |
103103 bb.0.entry:
104 liveins: %x0, %x1, %x2, %x3
104 liveins: $x0, $x1, $x2, $x3
105105
106106 ; CHECK-LABEL: name: test_scalar_add_small
107 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
108 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
107 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
108 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
109109 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
110110 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
111111 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
112112 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
113 ; CHECK: %x0 = COPY [[ANYEXT]](s64)
114 %0:_(s64) = COPY %x0
115 %1:_(s64) = COPY %x1
113 ; CHECK: $x0 = COPY [[ANYEXT]](s64)
114 %0:_(s64) = COPY $x0
115 %1:_(s64) = COPY $x1
116116 %2:_(s8) = G_TRUNC %0
117117 %3:_(s8) = G_TRUNC %1
118118 %4:_(s8) = G_ADD %2, %3
119119 %5:_(s64) = G_ANYEXT %4
120 %x0 = COPY %5
120 $x0 = COPY %5
121121 ...
122122
123123 ---
124124 name: test_vector_add
125125 body: |
126126 bb.0.entry:
127 liveins: %q0, %q1, %q2, %q3
127 liveins: $q0, $q1, $q2, $q3
128128
129129 ; CHECK-LABEL: name: test_vector_add
130 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY %q0
131 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY %q1
132 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY %q2
133 ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY %q3
130 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
131 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
132 ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
133 ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
134134 ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
135135 ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
136 ; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
137 ; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
138 %0:_(<2 x s64>) = COPY %q0
139 %1:_(<2 x s64>) = COPY %q1
140 %2:_(<2 x s64>) = COPY %q2
141 %3:_(<2 x s64>) = COPY %q3
136 ; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
137 ; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
138 %0:_(<2 x s64>) = COPY $q0
139 %1:_(<2 x s64>) = COPY $q1
140 %2:_(<2 x s64>) = COPY $q2
141 %3:_(<2 x s64>) = COPY $q3
142142 %4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
143143 %5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
144144 %6:_(<4 x s64>) = G_ADD %4, %5
145145 %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
146 %q0 = COPY %7
147 %q1 = COPY %8
146 $q0 = COPY %7
147 $q1 = COPY %8
148148 ...
149149 ---
150150 name: test_vector_add_nonpow2
161161 - { id: 9, class: _ }
162162 body: |
163163 bb.0.entry:
164 liveins: %q0, %q1, %q2, %q3
164 liveins: $q0, $q1, $q2, $q3
165165 ; CHECK-LABEL: name: test_vector_add_nonpow2
166166 ; CHECK-NOT: G_EXTRACT
167167 ; CHECK-NOT: G_SEQUENCE
170170 ; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
171171 ; CHECK-NOT: G_EXTRACT
172172 ; CHECK-NOT: G_SEQUENCE
173 ; CHECK: %q0 = COPY [[RES_LO]]
174 ; CHECK: %q1 = COPY [[RES_MI]]
175 ; CHECK: %q2 = COPY [[RES_HI]]
173 ; CHECK: $q0 = COPY [[RES_LO]]
174 ; CHECK: $q1 = COPY [[RES_MI]]
175 ; CHECK: $q2 = COPY [[RES_HI]]
176176
177 %0(<2 x s64>) = COPY %q0
178 %1(<2 x s64>) = COPY %q1
179 %2(<2 x s64>) = COPY %q2
180 %3(<2 x s64>) = COPY %q3
177 %0(<2 x s64>) = COPY $q0
178 %1(<2 x s64>) = COPY $q1
179 %2(<2 x s64>) = COPY $q2
180 %3(<2 x s64>) = COPY $q3
181181 %4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
182182 %5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
183183 %6(<6 x s64>) = G_ADD %4, %5
184184 %7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
185 %q0 = COPY %7
186 %q1 = COPY %8
187 %q2 = COPY %9
185 $q0 = COPY %7
186 $q1 = COPY %8
187 $q2 = COPY %9
188188 ...
2121 - { id: 6, class: _ }
2222 body: |
2323 bb.0.entry:
24 liveins: %x0, %x1, %x2, %x3
24 liveins: $x0, $x1, $x2, $x3
2525
2626 ; CHECK-LABEL: name: test_scalar_and_small
27 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
28 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
27 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
28 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
2929 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
3030 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
3131 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
3232 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
33 ; CHECK: %w0 = COPY [[COPY2]](s32)
33 ; CHECK: $w0 = COPY [[COPY2]](s32)
3434 ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
35 ; CHECK: %x0 = COPY [[COPY3]](s64)
36 %0(s64) = COPY %x0
37 %1(s64) = COPY %x1
35 ; CHECK: $x0 = COPY [[COPY3]](s64)
36 %0(s64) = COPY $x0
37 %1(s64) = COPY $x1
3838 %2(s8) = G_TRUNC %0
3939 %3(s8) = G_TRUNC %1
4040 %4(s8) = G_AND %2, %3
4141 %6(s32) = G_ANYEXT %4
42 %w0 = COPY %6
42 $w0 = COPY %6
4343 %5(s64) = G_ANYEXT %2
44 %x0 = COPY %5
44 $x0 = COPY %5
4545 ...
1313 name: cmpxchg_i8
1414 body: |
1515 bb.0:
16 liveins: %x0
16 liveins: $x0
1717
1818 ; CHECK-LABEL: name: cmpxchg_i8
19 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
19 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
2020 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
2121 ; CHECK: [[CST2:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
2222 ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 1 on %ir.addr)
2323 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
24 ; CHECK: %w0 = COPY [[RES2]]
25 %0:_(p0) = COPY %x0
24 ; CHECK: $w0 = COPY [[RES2]]
25 %0:_(p0) = COPY $x0
2626 %1:_(s8) = G_CONSTANT i8 1
2727 %2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 1 on %ir.addr)
2828 %3:_(s32) = G_ANYEXT %2
29 %w0 = COPY %3(s32)
29 $w0 = COPY %3(s32)
3030 ...
3131
3232 ---
3333 name: cmpxchg_i16
3434 body: |
3535 bb.0:
36 liveins: %x0
36 liveins: $x0
3737
3838 ; CHECK-LABEL: name: cmpxchg_i16
39 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
39 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
4040 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
4141 ; CHECK: [[CST2:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
4242 ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST2]] :: (load store monotonic 2 on %ir.addr)
4343 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
44 ; CHECK: %w0 = COPY [[RES2]]
45 %0:_(p0) = COPY %x0
44 ; CHECK: $w0 = COPY [[RES2]]
45 %0:_(p0) = COPY $x0
4646 %1:_(s16) = G_CONSTANT i16 1
4747 %2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 2 on %ir.addr)
4848 %3:_(s32) = G_ANYEXT %2
49 %w0 = COPY %3(s32)
49 $w0 = COPY %3(s32)
5050 ...
5151
5252 ---
5353 name: cmpxchg_i32
5454 body: |
5555 bb.0:
56 liveins: %x0
56 liveins: $x0
5757
5858 ; CHECK-LABEL: name: cmpxchg_i32
59 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
59 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
6060 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
6161 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 4 on %ir.addr)
62 ; CHECK: %w0 = COPY [[RES]]
63 %0:_(p0) = COPY %x0
62 ; CHECK: $w0 = COPY [[RES]]
63 %0:_(p0) = COPY $x0
6464 %1:_(s32) = G_CONSTANT i32 1
6565 %2:_(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 4 on %ir.addr)
66 %w0 = COPY %2(s32)
66 $w0 = COPY %2(s32)
6767 ...
6868
6969 ---
7070 name: cmpxchg_i64
7171 body: |
7272 bb.0:
73 liveins: %x0
73 liveins: $x0
7474
7575 ; CHECK-LABEL: name: cmpxchg_i64
76 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
76 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
7777 ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
7878 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMICRMW_ADD [[COPY]](p0), [[CST]] :: (load store monotonic 8 on %ir.addr)
79 ; CHECK: %x0 = COPY [[RES]]
80 %0:_(p0) = COPY %x0
79 ; CHECK: $x0 = COPY [[RES]]
80 %0:_(p0) = COPY $x0
8181 %1:_(s64) = G_CONSTANT i64 1
8282 %2:_(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
83 %x0 = COPY %2(s64)
83 $x0 = COPY %2(s64)
8484 ...
2929 - { id: 14, class: _ }
3030 body: |
3131 bb.0.entry:
32 liveins: %x0, %x1, %x2, %x3
32 liveins: $x0, $x1, $x2, $x3
3333 ; CHECK-LABEL: name: test_icmp
34 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
35 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
34 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
35 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
3636 ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
3737 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
38 ; CHECK: %w0 = COPY [[COPY2]](s32)
38 ; CHECK: $w0 = COPY [[COPY2]](s32)
3939 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
4040 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
4141 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
4444 ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
4545 ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
4646 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
47 ; CHECK: %w0 = COPY [[COPY3]](s32)
47 ; CHECK: $w0 = COPY [[COPY3]](s32)
4848 ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
4949 ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
5050 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
51 ; CHECK: %w0 = COPY [[COPY4]](s32)
52 %0(s64) = COPY %x0
53 %1(s64) = COPY %x0
51 ; CHECK: $w0 = COPY [[COPY4]](s32)
52 %0(s64) = COPY $x0
53 %1(s64) = COPY $x0
5454
5555 %2(s8) = G_TRUNC %0
5656 %3(s8) = G_TRUNC %1
5757
5858 %4(s1) = G_ICMP intpred(sge), %0, %1
5959 %11(s32) = G_ANYEXT %4
60 %w0 = COPY %11
60 $w0 = COPY %11
6161
6262 %8(s1) = G_ICMP intpred(ult), %2, %3
6363 %12(s32) = G_ANYEXT %8
64 %w0 = COPY %12
64 $w0 = COPY %12
6565
6666 %9(p0) = G_INTTOPTR %0(s64)
6767 %10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
6868 %14(s32) = G_ANYEXT %10
69 %w0 = COPY %14
69 $w0 = COPY %14
7070 ...
1212
1313 body: |
1414 bb.0:
15 liveins: %x0
15 liveins: $x0
1616
1717 ; CHECK-LABEL: name: cmpxchg_i32
18 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
18 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
1919 ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
2020 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
2121 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
2222 ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]]
2323 ; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]]
2424 ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]]
25 ; CHECK: %w0 = COPY [[MUL]]
26 %0:_(p0) = COPY %x0
25 ; CHECK: $w0 = COPY [[MUL]]
26 %0:_(p0) = COPY $x0
2727 %1:_(s32) = G_CONSTANT i32 0
2828 %2:_(s32) = G_CONSTANT i32 1
2929 %3:_(s32), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
3030 %5:_(s32) = G_ANYEXT %4
3131 %6:_(s32) = G_MUL %3, %5
32 %w0 = COPY %6(s32)
32 $w0 = COPY %6(s32)
3333 ...
3434
3535 ---
3737
3838 body: |
3939 bb.0:
40 liveins: %x0
40 liveins: $x0
4141
4242 ; CHECK-LABEL: name: cmpxchg_i64
43 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
43 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
4444 ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
4545 ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
4646 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
4747 ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]]
4848 ; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]]
4949 ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]]
50 ; CHECK: %x0 = COPY [[MUL]]
51 %0:_(p0) = COPY %x0
50 ; CHECK: $x0 = COPY [[MUL]]
51 %0:_(p0) = COPY $x0
5252 %1:_(s64) = G_CONSTANT i64 0
5353 %2:_(s64) = G_CONSTANT i64 1
5454 %3:_(s64), %4:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
5555 %5:_(s64) = G_ANYEXT %4
5656 %6:_(s64) = G_MUL %3, %5
57 %x0 = COPY %6(s64)
57 $x0 = COPY %6(s64)
5858 ...
1313 name: cmpxchg_i8
1414 body: |
1515 bb.0:
16 liveins: %x0
16 liveins: $x0
1717
1818 ; CHECK-LABEL: name: cmpxchg_i8
19 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
19 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
2020 ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
2121 ; CHECK: [[CMPT:%[0-9]+]]:_(s8) = G_TRUNC [[CMP]]
2222 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
2323 ; CHECK: [[CSTT:%[0-9]+]]:_(s8) = G_TRUNC [[CST]]
2424 ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 1 on %ir.addr)
2525 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s8)
26 ; CHECK: %w0 = COPY [[RES2]]
27 %0:_(p0) = COPY %x0
26 ; CHECK: $w0 = COPY [[RES2]]
27 %0:_(p0) = COPY $x0
2828 %1:_(s8) = G_CONSTANT i8 0
2929 %2:_(s8) = G_CONSTANT i8 1
3030 %3:_(s8) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 1 on %ir.addr)
3131 %4:_(s32) = G_ANYEXT %3
32 %w0 = COPY %4(s32)
32 $w0 = COPY %4(s32)
3333 ...
3434
3535 ---
3636 name: cmpxchg_i16
3737 body: |
3838 bb.0:
39 liveins: %x0
39 liveins: $x0
4040
4141 ; CHECK-LABEL: name: cmpxchg_i16
42 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
42 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
4343 ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
4444 ; CHECK: [[CMPT:%[0-9]+]]:_(s16) = G_TRUNC [[CMP]]
4545 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
4646 ; CHECK: [[CSTT:%[0-9]+]]:_(s16) = G_TRUNC [[CST]]
4747 ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMPT]], [[CSTT]] :: (load store monotonic 2 on %ir.addr)
4848 ; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]](s16)
49 ; CHECK: %w0 = COPY [[RES2]]
50 %0:_(p0) = COPY %x0
49 ; CHECK: $w0 = COPY [[RES2]]
50 %0:_(p0) = COPY $x0
5151 %1:_(s16) = G_CONSTANT i16 0
5252 %2:_(s16) = G_CONSTANT i16 1
5353 %3:_(s16) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 2 on %ir.addr)
5454 %4:_(s32) = G_ANYEXT %3
55 %w0 = COPY %4(s32)
55 $w0 = COPY %4(s32)
5656 ...
5757
5858 ---
5959 name: cmpxchg_i32
6060 body: |
6161 bb.0:
62 liveins: %x0
62 liveins: $x0
6363
6464 ; CHECK-LABEL: name: cmpxchg_i32
65 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
65 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
6666 ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
6767 ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
6868 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 4 on %ir.addr)
69 ; CHECK: %w0 = COPY [[RES]]
70 %0:_(p0) = COPY %x0
69 ; CHECK: $w0 = COPY [[RES]]
70 %0:_(p0) = COPY $x0
7171 %1:_(s32) = G_CONSTANT i32 0
7272 %2:_(s32) = G_CONSTANT i32 1
7373 %3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 4 on %ir.addr)
74 %w0 = COPY %3(s32)
74 $w0 = COPY %3(s32)
7575 ...
7676
7777 ---
7878 name: cmpxchg_i64
7979 body: |
8080 bb.0:
81 liveins: %x0
81 liveins: $x0
8282
8383 ; CHECK-LABEL: name: cmpxchg_i64
84 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
84 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
8585 ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
8686 ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
8787 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic 8 on %ir.addr)
88 ; CHECK: %x0 = COPY [[RES]]
89 %0:_(p0) = COPY %x0
88 ; CHECK: $x0 = COPY [[RES]]
89 %0:_(p0) = COPY $x0
9090 %1:_(s64) = G_CONSTANT i64 0
9191 %2:_(s64) = G_CONSTANT i64 1
9292 %3:_(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store monotonic 8 on %ir.addr)
93 %x0 = COPY %3(s64)
93 $x0 = COPY %3(s64)