llvm.org GIT mirror llvm / 1061506
[MIPS GlobalISel] Select integer to floating point conversions Select G_SITOFP and G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D63542 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363912 91177308-0d34-0410-b5e6-96231b3b80d8 Petar Avramovic 2 months ago
7 changed file(s) with 675 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
434434 // FIXME: Support other types
435435 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
436436 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
437 if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
437 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
438438 return UnableToLegalize;
439439 LegalizeResult Status = conversionLibcall(
440440 MI, MIRBuilder,
441441 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
442 Type::getInt32Ty(Ctx));
442 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
443443 if (Status != Legalized)
444444 return Status;
445445 break;
119119 .libcallForCartesianProduct({s64}, {s64, s32})
120120 .minScalar(0, s32);
121121
122 // Int to FP conversion instructions
123 getActionDefinitionsBuilder(G_SITOFP)
124 .legalForCartesianProduct({s64, s32}, {s32})
125 .libcallForCartesianProduct({s64, s32}, {s64})
126 .minScalar(1, s32);
127
128 getActionDefinitionsBuilder(G_UITOFP)
129 .libcallForCartesianProduct({s64, s32}, {s64})
130 .minScalar(1, s32);
131
122132 computeTables();
123133 verify(*ST.getInstrInfo());
124134 }
181181 });
182182 break;
183183 }
184 case G_SITOFP: {
185 unsigned SizeInt = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
186 unsigned SizeFP = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
187 assert((SizeInt == 32) && "Unsupported integer size");
188 assert((SizeFP == 32 || SizeFP == 64) && "Unsupported floating point size");
189 OperandsMapping =
190 getOperandsMapping({SizeFP == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
191 : &Mips::ValueMappings[Mips::DPRIdx],
192 &Mips::ValueMappings[Mips::GPRIdx]});
193 break;
194 }
184195 case G_CONSTANT:
185196 case G_FRAME_INDEX:
186197 case G_GLOBAL_VALUE:
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @i32tof32() {entry: ret void}
6 define void @i32tof64() {entry: ret void}
7
8 ...
9 ---
10 name: i32tof32
11 alignment: 2
12 legalized: true
13 regBankSelected: true
14 tracksRegLiveness: true
15 body: |
16 bb.1.entry:
17 liveins: $a0
18
19 ; FP32-LABEL: name: i32tof32
20 ; FP32: liveins: $a0
21 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
22 ; FP32: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
23 ; FP32: $f0 = COPY [[PseudoCVT_S_W]]
24 ; FP32: RetRA implicit $f0
25 ; FP64-LABEL: name: i32tof32
26 ; FP64: liveins: $a0
27 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
28 ; FP64: [[PseudoCVT_S_W:%[0-9]+]]:fgr32 = PseudoCVT_S_W [[COPY]]
29 ; FP64: $f0 = COPY [[PseudoCVT_S_W]]
30 ; FP64: RetRA implicit $f0
31 %0:gprb(s32) = COPY $a0
32 %1:fprb(s32) = G_SITOFP %0(s32)
33 $f0 = COPY %1(s32)
34 RetRA implicit $f0
35
36 ...
37 ---
38 name: i32tof64
39 alignment: 2
40 legalized: true
41 regBankSelected: true
42 tracksRegLiveness: true
43 body: |
44 bb.1.entry:
45 liveins: $a0
46
47 ; FP32-LABEL: name: i32tof64
48 ; FP32: liveins: $a0
49 ; FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
50 ; FP32: [[PseudoCVT_D32_W:%[0-9]+]]:afgr64 = PseudoCVT_D32_W [[COPY]]
51 ; FP32: $d0 = COPY [[PseudoCVT_D32_W]]
52 ; FP32: RetRA implicit $d0
53 ; FP64-LABEL: name: i32tof64
54 ; FP64: liveins: $a0
55 ; FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
56 ; FP64: [[PseudoCVT_D64_W:%[0-9]+]]:fgr64 = PseudoCVT_D64_W [[COPY]]
57 ; FP64: $d0 = COPY [[PseudoCVT_D64_W]]
58 ; FP64: RetRA implicit $d0
59 %0:gprb(s32) = COPY $a0
60 %1:fprb(s64) = G_SITOFP %0(s32)
61 $d0 = COPY %1(s64)
62 RetRA implicit $d0
63
64 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @i64tof32() {entry: ret void}
6 define void @i32tof32() {entry: ret void}
7 define void @i16tof32() {entry: ret void}
8 define void @i8tof32() {entry: ret void}
9 define void @i64tof64() {entry: ret void}
10 define void @i32tof64() {entry: ret void}
11 define void @i16tof64() {entry: ret void}
12 define void @i8tof64() {entry: ret void}
13 define void @u64tof32() {entry: ret void}
14 define void @u64tof64() {entry: ret void}
15
16 ...
17 ---
18 name: i64tof32
19 alignment: 2
20 tracksRegLiveness: true
21 body: |
22 bb.1.entry:
23 liveins: $a0, $a1
24
25 ; FP32-LABEL: name: i64tof32
26 ; FP32: liveins: $a0, $a1
27 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
28 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
29 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
30 ; FP32: $a0 = COPY [[COPY]](s32)
31 ; FP32: $a1 = COPY [[COPY1]](s32)
32 ; FP32: JAL &__floatdisf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
33 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
34 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
35 ; FP32: $f0 = COPY [[COPY2]](s32)
36 ; FP32: RetRA implicit $f0
37 ; FP64-LABEL: name: i64tof32
38 ; FP64: liveins: $a0, $a1
39 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
40 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
41 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
42 ; FP64: $a0 = COPY [[COPY]](s32)
43 ; FP64: $a1 = COPY [[COPY1]](s32)
44 ; FP64: JAL &__floatdisf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
45 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
46 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
47 ; FP64: $f0 = COPY [[COPY2]](s32)
48 ; FP64: RetRA implicit $f0
49 %1:_(s32) = COPY $a0
50 %2:_(s32) = COPY $a1
51 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
52 %3:_(s32) = G_SITOFP %0(s64)
53 $f0 = COPY %3(s32)
54 RetRA implicit $f0
55
56 ...
57 ---
58 name: i32tof32
59 alignment: 2
60 tracksRegLiveness: true
61 body: |
62 bb.1.entry:
63 liveins: $a0
64
65 ; FP32-LABEL: name: i32tof32
66 ; FP32: liveins: $a0
67 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
68 ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
69 ; FP32: $f0 = COPY [[SITOFP]](s32)
70 ; FP32: RetRA implicit $f0
71 ; FP64-LABEL: name: i32tof32
72 ; FP64: liveins: $a0
73 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
74 ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
75 ; FP64: $f0 = COPY [[SITOFP]](s32)
76 ; FP64: RetRA implicit $f0
77 %0:_(s32) = COPY $a0
78 %1:_(s32) = G_SITOFP %0(s32)
79 $f0 = COPY %1(s32)
80 RetRA implicit $f0
81
82 ...
83 ---
84 name: i16tof32
85 alignment: 2
86 tracksRegLiveness: true
87 body: |
88 bb.1.entry:
89 liveins: $a0
90
91 ; FP32-LABEL: name: i16tof32
92 ; FP32: liveins: $a0
93 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
94 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
95 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
96 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
97 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
98 ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
99 ; FP32: $f0 = COPY [[SITOFP]](s32)
100 ; FP32: RetRA implicit $f0
101 ; FP64-LABEL: name: i16tof32
102 ; FP64: liveins: $a0
103 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
104 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
105 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
106 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
107 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
108 ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
109 ; FP64: $f0 = COPY [[SITOFP]](s32)
110 ; FP64: RetRA implicit $f0
111 %1:_(s32) = COPY $a0
112 %0:_(s16) = G_TRUNC %1(s32)
113 %2:_(s32) = G_SITOFP %0(s16)
114 $f0 = COPY %2(s32)
115 RetRA implicit $f0
116
117 ...
118 ---
119 name: i8tof32
120 alignment: 2
121 tracksRegLiveness: true
122 body: |
123 bb.1.entry:
124 liveins: $a0
125
126 ; FP32-LABEL: name: i8tof32
127 ; FP32: liveins: $a0
128 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
129 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
130 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
131 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
132 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
133 ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
134 ; FP32: $f0 = COPY [[SITOFP]](s32)
135 ; FP32: RetRA implicit $f0
136 ; FP64-LABEL: name: i8tof32
137 ; FP64: liveins: $a0
138 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
139 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
140 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
141 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
142 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
143 ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
144 ; FP64: $f0 = COPY [[SITOFP]](s32)
145 ; FP64: RetRA implicit $f0
146 %1:_(s32) = COPY $a0
147 %0:_(s8) = G_TRUNC %1(s32)
148 %2:_(s32) = G_SITOFP %0(s8)
149 $f0 = COPY %2(s32)
150 RetRA implicit $f0
151
152 ...
153 ---
154 name: i64tof64
155 alignment: 2
156 tracksRegLiveness: true
157 body: |
158 bb.1.entry:
159 liveins: $a0, $a1
160
161 ; FP32-LABEL: name: i64tof64
162 ; FP32: liveins: $a0, $a1
163 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
164 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
165 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
166 ; FP32: $a0 = COPY [[COPY]](s32)
167 ; FP32: $a1 = COPY [[COPY1]](s32)
168 ; FP32: JAL &__floatdidf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
169 ; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
170 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
171 ; FP32: $d0 = COPY [[COPY2]](s64)
172 ; FP32: RetRA implicit $d0
173 ; FP64-LABEL: name: i64tof64
174 ; FP64: liveins: $a0, $a1
175 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
176 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
177 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
178 ; FP64: $a0 = COPY [[COPY]](s32)
179 ; FP64: $a1 = COPY [[COPY1]](s32)
180 ; FP64: JAL &__floatdidf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
181 ; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
182 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
183 ; FP64: $d0 = COPY [[COPY2]](s64)
184 ; FP64: RetRA implicit $d0
185 %1:_(s32) = COPY $a0
186 %2:_(s32) = COPY $a1
187 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
188 %3:_(s64) = G_SITOFP %0(s64)
189 $d0 = COPY %3(s64)
190 RetRA implicit $d0
191
192 ...
193 ---
194 name: i32tof64
195 alignment: 2
196 tracksRegLiveness: true
197 body: |
198 bb.1.entry:
199 liveins: $a0
200
201 ; FP32-LABEL: name: i32tof64
202 ; FP32: liveins: $a0
203 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
204 ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
205 ; FP32: $d0 = COPY [[SITOFP]](s64)
206 ; FP32: RetRA implicit $d0
207 ; FP64-LABEL: name: i32tof64
208 ; FP64: liveins: $a0
209 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
210 ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
211 ; FP64: $d0 = COPY [[SITOFP]](s64)
212 ; FP64: RetRA implicit $d0
213 %0:_(s32) = COPY $a0
214 %1:_(s64) = G_SITOFP %0(s32)
215 $d0 = COPY %1(s64)
216 RetRA implicit $d0
217
218 ...
219 ---
220 name: i16tof64
221 alignment: 2
222 tracksRegLiveness: true
223 body: |
224 bb.1.entry:
225 liveins: $a0
226
227 ; FP32-LABEL: name: i16tof64
228 ; FP32: liveins: $a0
229 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
230 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
231 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
232 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
233 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
234 ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
235 ; FP32: $d0 = COPY [[SITOFP]](s64)
236 ; FP32: RetRA implicit $d0
237 ; FP64-LABEL: name: i16tof64
238 ; FP64: liveins: $a0
239 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
240 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
241 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
242 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
243 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
244 ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
245 ; FP64: $d0 = COPY [[SITOFP]](s64)
246 ; FP64: RetRA implicit $d0
247 %1:_(s32) = COPY $a0
248 %0:_(s16) = G_TRUNC %1(s32)
249 %2:_(s64) = G_SITOFP %0(s16)
250 $d0 = COPY %2(s64)
251 RetRA implicit $d0
252
253 ...
254 ---
255 name: i8tof64
256 alignment: 2
257 tracksRegLiveness: true
258 body: |
259 bb.1.entry:
260 liveins: $a0
261
262 ; FP32-LABEL: name: i8tof64
263 ; FP32: liveins: $a0
264 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
265 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
266 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
267 ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
268 ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
269 ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
270 ; FP32: $d0 = COPY [[SITOFP]](s64)
271 ; FP32: RetRA implicit $d0
272 ; FP64-LABEL: name: i8tof64
273 ; FP64: liveins: $a0
274 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
275 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
276 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
277 ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
278 ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
279 ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
280 ; FP64: $d0 = COPY [[SITOFP]](s64)
281 ; FP64: RetRA implicit $d0
282 %1:_(s32) = COPY $a0
283 %0:_(s8) = G_TRUNC %1(s32)
284 %2:_(s64) = G_SITOFP %0(s8)
285 $d0 = COPY %2(s64)
286 RetRA implicit $d0
287
288 ...
289 ---
290 name: u64tof32
291 alignment: 2
292 tracksRegLiveness: true
293 body: |
294 bb.1.entry:
295 liveins: $a0, $a1
296
297 ; FP32-LABEL: name: u64tof32
298 ; FP32: liveins: $a0, $a1
299 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
300 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
301 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
302 ; FP32: $a0 = COPY [[COPY]](s32)
303 ; FP32: $a1 = COPY [[COPY1]](s32)
304 ; FP32: JAL &__floatundisf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
305 ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
306 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
307 ; FP32: $f0 = COPY [[COPY2]](s32)
308 ; FP32: RetRA implicit $f0
309 ; FP64-LABEL: name: u64tof32
310 ; FP64: liveins: $a0, $a1
311 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
312 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
313 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
314 ; FP64: $a0 = COPY [[COPY]](s32)
315 ; FP64: $a1 = COPY [[COPY1]](s32)
316 ; FP64: JAL &__floatundisf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $f0
317 ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY $f0
318 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
319 ; FP64: $f0 = COPY [[COPY2]](s32)
320 ; FP64: RetRA implicit $f0
321 %1:_(s32) = COPY $a0
322 %2:_(s32) = COPY $a1
323 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
324 %3:_(s32) = G_UITOFP %0(s64)
325 $f0 = COPY %3(s32)
326 RetRA implicit $f0
327
328 ...
329 ---
330 name: u64tof64
331 alignment: 2
332 tracksRegLiveness: true
333 body: |
334 bb.1.entry:
335 liveins: $a0, $a1
336
337 ; FP32-LABEL: name: u64tof64
338 ; FP32: liveins: $a0, $a1
339 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
340 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
341 ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
342 ; FP32: $a0 = COPY [[COPY]](s32)
343 ; FP32: $a1 = COPY [[COPY1]](s32)
344 ; FP32: JAL &__floatundidf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0
345 ; FP32: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
346 ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
347 ; FP32: $d0 = COPY [[COPY2]](s64)
348 ; FP32: RetRA implicit $d0
349 ; FP64-LABEL: name: u64tof64
350 ; FP64: liveins: $a0, $a1
351 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
352 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
353 ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
354 ; FP64: $a0 = COPY [[COPY]](s32)
355 ; FP64: $a1 = COPY [[COPY1]](s32)
356 ; FP64: JAL &__floatundidf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $d0_64
357 ; FP64: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0_64
358 ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
359 ; FP64: $d0 = COPY [[COPY2]](s64)
360 ; FP64: RetRA implicit $d0
361 %1:_(s32) = COPY $a0
362 %2:_(s32) = COPY $a1
363 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
364 %3:_(s64) = G_UITOFP %0(s64)
365 $d0 = COPY %3(s64)
366 RetRA implicit $d0
367
368 ...
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
2 ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
3
4 define float @i64tof32(i64 signext %a) {
5 ; MIPS32-LABEL: i64tof32:
6 ; MIPS32: # %bb.0: # %entry
7 ; MIPS32-NEXT: addiu $sp, $sp, -24
8 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
9 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
10 ; MIPS32-NEXT: .cfi_offset 31, -4
11 ; MIPS32-NEXT: jal __floatdisf
12 ; MIPS32-NEXT: nop
13 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
14 ; MIPS32-NEXT: addiu $sp, $sp, 24
15 ; MIPS32-NEXT: jr $ra
16 ; MIPS32-NEXT: nop
17 entry:
18 %conv = sitofp i64 %a to float
19 ret float %conv
20 }
21
22 define float @i32tof32(i32 signext %a) {
23 ; MIPS32-LABEL: i32tof32:
24 ; MIPS32: # %bb.0: # %entry
25 ; MIPS32-NEXT: mtc1 $4, $f0
26 ; MIPS32-NEXT: cvt.s.w $f0, $f0
27 ; MIPS32-NEXT: jr $ra
28 ; MIPS32-NEXT: nop
29 entry:
30 %conv = sitofp i32 %a to float
31 ret float %conv
32 }
33
34 define float @i16tof32(i16 signext %a) {
35 ; MIPS32-LABEL: i16tof32:
36 ; MIPS32: # %bb.0: # %entry
37 ; MIPS32-NEXT: sll $1, $4, 16
38 ; MIPS32-NEXT: sra $1, $1, 16
39 ; MIPS32-NEXT: mtc1 $1, $f0
40 ; MIPS32-NEXT: cvt.s.w $f0, $f0
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: nop
43 entry:
44 %conv = sitofp i16 %a to float
45 ret float %conv
46 }
47
48 define float @i8tof32(i8 signext %a) {
49 ; MIPS32-LABEL: i8tof32:
50 ; MIPS32: # %bb.0: # %entry
51 ; MIPS32-NEXT: sll $1, $4, 24
52 ; MIPS32-NEXT: sra $1, $1, 24
53 ; MIPS32-NEXT: mtc1 $1, $f0
54 ; MIPS32-NEXT: cvt.s.w $f0, $f0
55 ; MIPS32-NEXT: jr $ra
56 ; MIPS32-NEXT: nop
57 entry:
58 %conv = sitofp i8 %a to float
59 ret float %conv
60 }
61
62 define double @i64tof64(i64 signext %a) {
63 ; MIPS32-LABEL: i64tof64:
64 ; MIPS32: # %bb.0: # %entry
65 ; MIPS32-NEXT: addiu $sp, $sp, -24
66 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
67 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
68 ; MIPS32-NEXT: .cfi_offset 31, -4
69 ; MIPS32-NEXT: jal __floatdidf
70 ; MIPS32-NEXT: nop
71 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
72 ; MIPS32-NEXT: addiu $sp, $sp, 24
73 ; MIPS32-NEXT: jr $ra
74 ; MIPS32-NEXT: nop
75 entry:
76 %conv = sitofp i64 %a to double
77 ret double %conv
78 }
79
80 define double @i32tof64(i32 signext %a) {
81 ; MIPS32-LABEL: i32tof64:
82 ; MIPS32: # %bb.0: # %entry
83 ; MIPS32-NEXT: mtc1 $4, $f0
84 ; MIPS32-NEXT: cvt.d.w $f0, $f0
85 ; MIPS32-NEXT: jr $ra
86 ; MIPS32-NEXT: nop
87 entry:
88 %conv = sitofp i32 %a to double
89 ret double %conv
90 }
91
92 define double @i16tof64(i16 signext %a) {
93 ; MIPS32-LABEL: i16tof64:
94 ; MIPS32: # %bb.0: # %entry
95 ; MIPS32-NEXT: sll $1, $4, 16
96 ; MIPS32-NEXT: sra $1, $1, 16
97 ; MIPS32-NEXT: mtc1 $1, $f0
98 ; MIPS32-NEXT: cvt.d.w $f0, $f0
99 ; MIPS32-NEXT: jr $ra
100 ; MIPS32-NEXT: nop
101 entry:
102 %conv = sitofp i16 %a to double
103 ret double %conv
104 }
105
106 define double @i8tof64(i8 signext %a) {
107 ; MIPS32-LABEL: i8tof64:
108 ; MIPS32: # %bb.0: # %entry
109 ; MIPS32-NEXT: sll $1, $4, 24
110 ; MIPS32-NEXT: sra $1, $1, 24
111 ; MIPS32-NEXT: mtc1 $1, $f0
112 ; MIPS32-NEXT: cvt.d.w $f0, $f0
113 ; MIPS32-NEXT: jr $ra
114 ; MIPS32-NEXT: nop
115 entry:
116 %conv = sitofp i8 %a to double
117 ret double %conv
118 }
119
120 define float @u64tof32(i64 zeroext %a) {
121 ; MIPS32-LABEL: u64tof32:
122 ; MIPS32: # %bb.0: # %entry
123 ; MIPS32-NEXT: addiu $sp, $sp, -24
124 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
125 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
126 ; MIPS32-NEXT: .cfi_offset 31, -4
127 ; MIPS32-NEXT: jal __floatundisf
128 ; MIPS32-NEXT: nop
129 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
130 ; MIPS32-NEXT: addiu $sp, $sp, 24
131 ; MIPS32-NEXT: jr $ra
132 ; MIPS32-NEXT: nop
133 entry:
134 %conv = uitofp i64 %a to float
135 ret float %conv
136 }
137
138 define double @u64tof64(i64 zeroext %a) {
139 ; MIPS32-LABEL: u64tof64:
140 ; MIPS32: # %bb.0: # %entry
141 ; MIPS32-NEXT: addiu $sp, $sp, -24
142 ; MIPS32-NEXT: .cfi_def_cfa_offset 24
143 ; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
144 ; MIPS32-NEXT: .cfi_offset 31, -4
145 ; MIPS32-NEXT: jal __floatundidf
146 ; MIPS32-NEXT: nop
147 ; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
148 ; MIPS32-NEXT: addiu $sp, $sp, 24
149 ; MIPS32-NEXT: jr $ra
150 ; MIPS32-NEXT: nop
151 entry:
152 %conv = uitofp i64 %a to double
153 ret double %conv
154 }
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
2 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
3 --- |
4
5 define void @i32tof32() {entry: ret void}
6 define void @i32tof64() {entry: ret void}
7
8 ...
9 ---
10 name: i32tof32
11 alignment: 2
12 legalized: true
13 tracksRegLiveness: true
14 body: |
15 bb.1.entry:
16 liveins: $a0
17
18 ; FP32-LABEL: name: i32tof32
19 ; FP32: liveins: $a0
20 ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
21 ; FP32: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
22 ; FP32: $f0 = COPY [[SITOFP]](s32)
23 ; FP32: RetRA implicit $f0
24 ; FP64-LABEL: name: i32tof32
25 ; FP64: liveins: $a0
26 ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
27 ; FP64: [[SITOFP:%[0-9]+]]:fprb(s32) = G_SITOFP [[COPY]](s32)
28 ; FP64: $f0 = COPY [[SITOFP]](s32)
29 ; FP64: RetRA implicit $f0
30 %0:_(s32) = COPY $a0
31 %1:_(s32) = G_SITOFP %0(s32)
32 $f0 = COPY %1(s32)
33 RetRA implicit $f0
34
35 ...
36 ---
37 name: i32tof64
38 alignment: 2
39 legalized: true
40 tracksRegLiveness: true
41 body: |
42 bb.1.entry:
43 liveins: $a0
44
45 ; FP32-LABEL: name: i32tof64
46 ; FP32: liveins: $a0
47 ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
48 ; FP32: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
49 ; FP32: $d0 = COPY [[SITOFP]](s64)
50 ; FP32: RetRA implicit $d0
51 ; FP64-LABEL: name: i32tof64
52 ; FP64: liveins: $a0
53 ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
54 ; FP64: [[SITOFP:%[0-9]+]]:fprb(s64) = G_SITOFP [[COPY]](s32)
55 ; FP64: $d0 = COPY [[SITOFP]](s64)
56 ; FP64: RetRA implicit $d0
57 %0:_(s32) = COPY $a0
58 %1:_(s64) = G_SITOFP %0(s32)
59 $d0 = COPY %1(s64)
60 RetRA implicit $d0
61
62 ...