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Merging r355854: ------------------------------------------------------------------------ r355854 | jonpa | 2019-03-11 12:00:37 -0700 (Mon, 11 Mar 2019) | 13 lines [RegAlloc] Avoid compile time regression with multiple copy hints. As a fix for https://bugs.llvm.org/show_bug.cgi?id=40986 ("excessive compile time building opencollada"), this patch makes sure that no phys reg is hinted more than once from getRegAllocationHints(). This handles the case were many virtual registers are assigned to the same physreg. The previous compile time fix (r343686) in weightCalcHelper() only made sure that physical/virtual registers are passed no more than once to addRegAllocationHint(). Review: Dimitry Andric, Quentin Colombet https://reviews.llvm.org/D59201 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@358905 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 months ago
2 changed file(s) with 811 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1313 #include "llvm/CodeGen/TargetRegisterInfo.h"
1414 #include "llvm/ADT/ArrayRef.h"
1515 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/SmallSet.h"
1617 #include "llvm/ADT/STLExtras.h"
1718 #include "llvm/ADT/StringExtras.h"
1819 #include "llvm/CodeGen/MachineFrameInfo.h"
397398 const std::pair> &Hints_MRI =
398399 MRI.getRegAllocationHints(VirtReg);
399400
401 SmallSet HintedRegs;
400402 // First hint may be a target hint.
401403 bool Skip = (Hints_MRI.first != 0);
402404 for (auto Reg : Hints_MRI.second) {
410412 if (VRM && isVirtualRegister(Phys))
411413 Phys = VRM->getPhys(Phys);
412414
415 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
416 // registers allocated to the same physreg).
417 if (!HintedRegs.insert(Phys).second)
418 continue;
413419 // Check that Phys is a valid hint in VirtReg's register class.
414420 if (!isPhysicalRegister(Phys))
415421 continue;
0 # RUN: llc -mtriple=i386-unknown-unknown -mcpu=i486 %s -o - -run-pass greedy \
1 # RUN: -debug-only=regalloc 2>&1 | FileCheck %s
2 # REQUIRES: asserts
3
4 --- |
5 %0 = type { %1 }
6 %1 = type { %2, %23, %23*, %27*, %28*, %29, %33*, %34, %42, i8, i32, i32, i32 }
7 %2 = type { %3, %6, %14, %14, i8, i8*, i8*, %16 }
8 %3 = type { i32 (...)**, %4*, %5* }
9 %4 = type { i32 (...)**, %3* }
10 %5 = type { i32 (...)** }
11 %6 = type { %7 }
12 %7 = type { %8, i32, %12 }
13 %8 = type { %9**, %9**, %9**, %10 }
14 %9 = type { i32, i32, i32, i8* }
15 %10 = type { %11 }
16 %11 = type { %9** }
17 %12 = type { %13 }
18 %13 = type { i32 }
19 %14 = type { i32, %15* }
20 %15 = type { i32, i32, i8* }
21 %16 = type { %17 }
22 %17 = type { %18*, %20, %22 }
23 %18 = type { %19* }
24 %19 = type <{ %18, %19*, %18*, i8, [3 x i8] }>
25 %20 = type { %21 }
26 %21 = type { %18 }
27 %22 = type { %13 }
28 %23 = type { %24 }
29 %24 = type { %18*, %25, %26 }
30 %25 = type { %21 }
31 %26 = type { %13 }
32 %27 = type { i32 (...)** }
33 %28 = type { i32 (...)** }
34 %29 = type { %30 }
35 %30 = type { %18*, %31, %32 }
36 %31 = type { %21 }
37 %32 = type { %13 }
38 %33 = type { i32 (...)** }
39 %34 = type { %35 }
40 %35 = type { %36 }
41 %36 = type { %37, i32, %41 }
42 %37 = type { %38**, %38**, %38**, %39 }
43 %38 = type { %42, i32 }
44 %39 = type { %40 }
45 %40 = type { %38** }
46 %41 = type { %13 }
47 %42 = type { %43 }
48 %43 = type { %18*, %44, %45 }
49 %44 = type { %21 }
50 %45 = type { %13 }
51 %46 = type { %47, %48 }
52 %47 = type <{ %18, %19*, %18*, i8 }>
53 %48 = type { %49 }
54 %49 = type { i32, %50 }
55 %50 = type { { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 }, { i32, i32 } }
56
57 define void @fun(%0* %arg) local_unnamed_addr #0 align 2 personality i32 (...)* @__gxx_personality_v0 {
58 bb:
59 %tmp = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1
60 %tmp1 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0
61 br i1 undef, label %bb5, label %bb6
62
63 bb5: ; preds = %bb
64 unreachable
65
66 bb6: ; preds = %bb
67 %tmp8 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 8, i32 0, i32 1, i32 0, i32 0
68 br i1 undef, label %bb10, label %bb9
69
70 bb9: ; preds = %bb6
71 unreachable
72
73 bb10: ; preds = %bb6
74 store %18* %tmp8, %18** undef
75 br i1 undef, label %bb14, label %bb13
76
77 bb13: ; preds = %bb10
78 unreachable
79
80 bb14: ; preds = %bb10
81 br i1 undef, label %bb17, label %bb18
82
83 bb17: ; preds = %bb14
84 unreachable
85
86 bb18: ; preds = %bb14
87 br i1 undef, label %bb20, label %bb19
88
89 bb19: ; preds = %bb18
90 unreachable
91
92 bb20: ; preds = %bb18
93 br i1 undef, label %bb25, label %bb24
94
95 bb24: ; preds = %bb20
96 unreachable
97
98 bb25: ; preds = %bb20
99 br i1 undef, label %bb29, label %bb30
100
101 bb29: ; preds = %bb25
102 unreachable
103
104 bb30: ; preds = %bb25
105 br i1 undef, label %bb38, label %bb31
106
107 bb31: ; preds = %bb30
108 %tmp32 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0
109 br i1 undef, label %bb34, label %bb35
110
111 bb34: ; preds = %bb31
112 unreachable
113
114 bb35: ; preds = %bb31
115 br i1 undef, label %bb40, label %bb36
116
117 bb36: ; preds = %bb35
118 unreachable
119
120 bb38: ; preds = %bb30
121 %tmp391 = bitcast %18* %tmp1 to %19**
122 br label %bb40
123
124 bb40: ; preds = %bb35, %bb38
125 %tmp41 = phi %18* [ %tmp1, %bb38 ], [ null, %bb35 ]
126 %tmp42 = phi %19** [ %tmp391, %bb38 ], [ %tmp32, %bb35 ]
127 br i1 undef, label %bb43, label %bb48
128
129 bb43: ; preds = %bb40
130 %tmp44 = tail call i8* @_Znwj()
131 store %18* %tmp41, %18** undef
132 %tmp46 = bitcast %19** %tmp42 to i8**
133 store i8* %tmp44, i8** %tmp46
134 %0 = bitcast i8* %tmp44 to %46*
135 tail call void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_()
136 br label %bb48
137
138 bb48: ; preds = %bb43, %bb40
139 %tmp49 = phi %46* [ %0, %bb43 ], [ undef, %bb40 ]
140 %tmp50 = getelementptr inbounds %46, %46* %tmp49, i32 0, i32 1, i32 0, i32 1, i32 4, i32 0
141 store i32 ptrtoint (i1 (%0*)* @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv to i32), i32* %tmp50
142 br i1 undef, label %bb52, label %bb53
143
144 bb52: ; preds = %bb48
145 unreachable
146
147 bb53: ; preds = %bb48
148 br i1 undef, label %bb55, label %bb54
149
150 bb54: ; preds = %bb53
151 unreachable
152
153 bb55: ; preds = %bb53
154 br i1 undef, label %bb59, label %bb58
155
156 bb58: ; preds = %bb55
157 unreachable
158
159 bb59: ; preds = %bb55
160 br i1 undef, label %bb62, label %bb61
161
162 bb61: ; preds = %bb59
163 unreachable
164
165 bb62: ; preds = %bb59
166 br i1 undef, label %bb64, label %bb65
167
168 bb64: ; preds = %bb62
169 unreachable
170
171 bb65: ; preds = %bb62
172 %tmp66 = icmp eq %46* null, null
173 br i1 %tmp66, label %bb72, label %bb67
174
175 bb67: ; preds = %bb65
176 %tmp68 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0, i32 0
177 br i1 undef, label %bb70, label %bb74
178
179 bb70: ; preds = %bb67
180 unreachable
181
182 bb72: ; preds = %bb65
183 %tmp732 = bitcast %18* %tmp1 to %19**
184 br label %bb74
185
186 bb74: ; preds = %bb67, %bb72
187 %tmp75 = phi %18* [ %tmp1, %bb72 ], [ null, %bb67 ]
188 %tmp76 = phi %19** [ %tmp732, %bb72 ], [ %tmp68, %bb67 ]
189 %tmp77 = tail call i8* @_Znwj()
190 store %18* %tmp75, %18** undef
191 %tmp79 = bitcast %19** %tmp76 to i8**
192 store i8* %tmp77, i8** %tmp79
193 %1 = bitcast i8* %tmp77 to %46*
194 tail call void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_()
195 %tmp81 = getelementptr inbounds %46, %46* %1, i32 0, i32 1, i32 0, i32 1, i32 2, i32 0
196 store i32 ptrtoint (i1 (%0*)* @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv to i32), i32* %tmp81
197 store %18* %tmp8, %18** undef
198 %2 = bitcast %0* %arg to i8*
199 %sunkaddr = getelementptr i8, i8* %2, i32 140
200 %3 = bitcast i8* %sunkaddr to %18**
201 %tmp85 = load %18*, %18** %3
202 %tmp864 = bitcast %18* %tmp85 to %19**
203 %tmp87 = load %19*, %19** %tmp864
204 %tmp88 = icmp eq %19* %tmp87, null
205 br i1 %tmp88, label %bb90, label %bb89
206
207 bb89: ; preds = %bb74
208 unreachable
209
210 bb90: ; preds = %bb74
211 br i1 undef, label %bb94, label %bb92
212
213 bb92: ; preds = %bb90
214 br i1 undef, label %bb96, label %bb97
215
216 bb94: ; preds = %bb90
217 unreachable
218
219 bb96: ; preds = %bb92
220 unreachable
221
222 bb97: ; preds = %bb92
223 br i1 undef, label %bb101, label %bb102
224
225 bb101: ; preds = %bb97
226 unreachable
227
228 bb102: ; preds = %bb97
229 br i1 undef, label %bb104, label %bb103
230
231 bb103: ; preds = %bb102
232 unreachable
233
234 bb104: ; preds = %bb102
235 br i1 undef, label %bb109, label %bb108
236
237 bb108: ; preds = %bb104
238 unreachable
239
240 bb109: ; preds = %bb104
241 br i1 undef, label %bb111, label %bb112
242
243 bb111: ; preds = %bb109
244 unreachable
245
246 bb112: ; preds = %bb109
247 br i1 undef, label %bb118, label %bb117
248
249 bb117: ; preds = %bb112
250 unreachable
251
252 bb118: ; preds = %bb112
253 br i1 undef, label %bb120, label %bb121
254
255 bb120: ; preds = %bb118
256 unreachable
257
258 bb121: ; preds = %bb118
259 br i1 undef, label %bb124, label %bb125
260
261 bb124: ; preds = %bb121
262 unreachable
263
264 bb125: ; preds = %bb121
265 %4 = bitcast %18* %tmp1 to %46**
266 %tmp126 = load %46*, %46** %4
267 %tmp127 = icmp eq %46* %tmp126, null
268 br i1 %tmp127, label %bb135, label %bb128
269
270 bb128: ; preds = %bb125
271 br label %bb129
272
273 bb129: ; preds = %bb131, %bb128
274 %tmp130 = icmp ugt i32 undef, 95406324
275 br i1 %tmp130, label %bb131, label %bb133
276
277 bb131: ; preds = %bb129
278 br label %bb129
279
280 bb133: ; preds = %bb129
281 unreachable
282
283 bb135: ; preds = %bb125
284 br i1 undef, label %bb137, label %bb138
285
286 bb137: ; preds = %bb135
287 unreachable
288
289 bb138: ; preds = %bb135
290 unreachable
291 }
292
293 declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv(%0*) #0
294
295 declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv(%0*) #0 align 2
296
297 declare i32 @__gxx_personality_v0(...) #0
298
299 declare noalias nonnull i8* @_Znwj() local_unnamed_addr #0
300
301 declare void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_() local_unnamed_addr #0
302
303 ; Function Attrs: nounwind
304 declare void @llvm.stackprotector(i8*, i8**) #1
305
306 attributes #0 = { "target-cpu"="i486" }
307 attributes #1 = { nounwind }
308
309 ...
310 ---
311 # A physreg should always only be hinted once per getRegAllocationHints() query.
312 # CHECK: hints: $ebx $edi
313 # CHECK-NOT: hints: $ebx $edi $ebx $edi
314 name: fun
315 alignment: 4
316 tracksRegLiveness: true
317 registers:
318 - { id: 0, class: gr32 }
319 - { id: 1, class: gr32 }
320 - { id: 2, class: gr32 }
321 - { id: 3, class: gr32 }
322 - { id: 4, class: gr32 }
323 - { id: 5, class: gr32 }
324 - { id: 6, class: gr32 }
325 - { id: 7, class: gr32 }
326 - { id: 8, class: gr32 }
327 - { id: 9, class: gr32 }
328 - { id: 10, class: gr32 }
329 - { id: 11, class: gr32 }
330 - { id: 12, class: gr32 }
331 - { id: 13, class: gr32_abcd }
332 - { id: 14, class: gr8 }
333 - { id: 15, class: gr32_abcd }
334 - { id: 16, class: gr8 }
335 - { id: 17, class: gr32 }
336 - { id: 18, class: gr32_abcd }
337 - { id: 19, class: gr8 }
338 - { id: 20, class: gr32_abcd }
339 - { id: 21, class: gr8 }
340 - { id: 22, class: gr32_abcd }
341 - { id: 23, class: gr8 }
342 - { id: 24, class: gr32_abcd }
343 - { id: 25, class: gr8 }
344 - { id: 26, class: gr32_abcd }
345 - { id: 27, class: gr8 }
346 - { id: 28, class: gr32_abcd }
347 - { id: 29, class: gr8 }
348 - { id: 30, class: gr32_abcd }
349 - { id: 31, class: gr8 }
350 - { id: 32, class: gr32_abcd }
351 - { id: 33, class: gr8 }
352 - { id: 34, class: gr32 }
353 - { id: 35, class: gr32_abcd }
354 - { id: 36, class: gr8 }
355 - { id: 37, class: gr32 }
356 - { id: 38, class: gr32 }
357 - { id: 39, class: gr32_abcd }
358 - { id: 40, class: gr8 }
359 - { id: 41, class: gr32_abcd }
360 - { id: 42, class: gr8 }
361 - { id: 43, class: gr32_abcd }
362 - { id: 44, class: gr8 }
363 - { id: 45, class: gr32_abcd }
364 - { id: 46, class: gr8 }
365 - { id: 47, class: gr32_abcd }
366 - { id: 48, class: gr8 }
367 - { id: 49, class: gr8 }
368 - { id: 50, class: gr32_abcd }
369 - { id: 51, class: gr8 }
370 - { id: 52, class: gr32 }
371 - { id: 53, class: gr32 }
372 - { id: 54, class: gr32 }
373 - { id: 55, class: gr32 }
374 - { id: 56, class: gr32_abcd }
375 - { id: 57, class: gr8 }
376 - { id: 58, class: gr32_abcd }
377 - { id: 59, class: gr8 }
378 - { id: 60, class: gr32_abcd }
379 - { id: 61, class: gr8 }
380 - { id: 62, class: gr32_abcd }
381 - { id: 63, class: gr8 }
382 - { id: 64, class: gr32_abcd }
383 - { id: 65, class: gr8 }
384 - { id: 66, class: gr32_abcd }
385 - { id: 67, class: gr8 }
386 - { id: 68, class: gr32_abcd }
387 - { id: 69, class: gr8 }
388 - { id: 70, class: gr32_abcd }
389 - { id: 71, class: gr8 }
390 - { id: 72, class: gr32_abcd }
391 - { id: 73, class: gr8 }
392 - { id: 74, class: gr32 }
393 - { id: 75, class: gr32 }
394 - { id: 76, class: gr32_abcd }
395 - { id: 77, class: gr8 }
396 - { id: 78, class: gr32_abcd }
397 - { id: 79, class: gr32 }
398 - { id: 80, class: gr32 }
399 - { id: 81, class: gr32_abcd }
400 - { id: 82, class: gr32 }
401 frameInfo:
402 maxAlignment: 4
403 hasCalls: true
404 fixedStack:
405 - { id: 0, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
406 body: |
407 bb.0.bb:
408 successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
409
410 %13:gr32_abcd = MOV32r0 implicit-def dead $eflags
411 TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
412 JNE_1 %bb.2, implicit killed $eflags
413 JMP_1 %bb.1
414
415 bb.1.bb5:
416 successors:
417
418
419 bb.2.bb6:
420 successors: %bb.4(0x7fffffff), %bb.3(0x00000001)
421
422 %15:gr32_abcd = MOV32r0 implicit-def dead $eflags
423 TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
424 JNE_1 %bb.4, implicit killed $eflags
425 JMP_1 %bb.3
426
427 bb.3.bb9:
428 successors:
429
430
431 bb.4.bb10:
432 successors: %bb.6(0x7fffffff), %bb.5(0x00000001)
433
434 %12:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.0)
435 %1:gr32 = LEA32r %12, 1, $noreg, 144, $noreg
436 MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1 :: (store 4 into `%18** undef`)
437 %18:gr32_abcd = MOV32r0 implicit-def dead $eflags
438 TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
439 JNE_1 %bb.6, implicit killed $eflags
440 JMP_1 %bb.5
441
442 bb.5.bb13:
443 successors:
444
445
446 bb.6.bb14:
447 successors: %bb.7(0x00000001), %bb.8(0x7fffffff)
448
449 %20:gr32_abcd = MOV32r0 implicit-def dead $eflags
450 TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
451 JNE_1 %bb.8, implicit killed $eflags
452 JMP_1 %bb.7
453
454 bb.7.bb17:
455 successors:
456
457
458 bb.8.bb18:
459 successors: %bb.10(0x7fffffff), %bb.9(0x00000001)
460
461 %22:gr32_abcd = MOV32r0 implicit-def dead $eflags
462 TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
463 JNE_1 %bb.10, implicit killed $eflags
464 JMP_1 %bb.9
465
466 bb.9.bb19:
467 successors:
468
469
470 bb.10.bb20:
471 successors: %bb.12(0x7fffffff), %bb.11(0x00000001)
472
473 %24:gr32_abcd = MOV32r0 implicit-def dead $eflags
474 TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
475 JNE_1 %bb.12, implicit killed $eflags
476 JMP_1 %bb.11
477
478 bb.11.bb24:
479 successors:
480
481
482 bb.12.bb25:
483 successors: %bb.13(0x00000001), %bb.14(0x7fffffff)
484
485 %26:gr32_abcd = MOV32r0 implicit-def dead $eflags
486 TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
487 JNE_1 %bb.14, implicit killed $eflags
488 JMP_1 %bb.13
489
490 bb.13.bb29:
491 successors:
492
493
494 bb.14.bb30:
495 %0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
496 %28:gr32_abcd = MOV32r0 implicit-def dead $eflags
497 TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
498 JNE_1 %bb.20, implicit killed $eflags
499 JMP_1 %bb.15
500
501 bb.15.bb31:
502 successors: %bb.16(0x00000001), %bb.17(0x7fffffff)
503
504 %78:gr32_abcd = MOV32r0 implicit-def dead $eflags
505 TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
506 JNE_1 %bb.17, implicit killed $eflags
507 JMP_1 %bb.16
508
509 bb.16.bb34:
510 successors:
511
512
513 bb.17.bb35:
514 successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
515
516 TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
517 JE_1 %bb.19, implicit killed $eflags
518
519 bb.18:
520 %79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
521 JMP_1 %bb.21
522
523 bb.19.bb36:
524 successors:
525
526
527 bb.20.bb38:
528 %78:gr32_abcd = COPY %0
529 %79:gr32 = COPY %0
530
531 bb.21.bb40:
532 successors: %bb.22, %bb.23
533
534 %35:gr32_abcd = MOV32r0 implicit-def dead $eflags
535 TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
536 %80:gr32 = IMPLICIT_DEF
537 JNE_1 %bb.23, implicit killed $eflags
538 JMP_1 %bb.22
539
540 bb.22.bb43:
541 ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
542 CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
543 ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
544 %80:gr32 = COPY killed $eax
545 MOV32mr undef %38:gr32, 1, $noreg, 0, $noreg, %78 :: (store 4 into `%18** undef`)
546 MOV32mr %79, 1, $noreg, 0, $noreg, %80 :: (store 4 into %ir.tmp46)
547 ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
548 CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
549 ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
550
551 bb.23.bb48:
552 successors: %bb.24(0x00000001), %bb.25(0x7fffffff)
553
554 MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv :: (store 4 into %ir.tmp50)
555 %39:gr32_abcd = MOV32r0 implicit-def dead $eflags
556 TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
557 JNE_1 %bb.25, implicit killed $eflags
558 JMP_1 %bb.24
559
560 bb.24.bb52:
561 successors:
562
563
564 bb.25.bb53:
565 successors: %bb.27(0x7fffffff), %bb.26(0x00000001)
566
567 %41:gr32_abcd = MOV32r0 implicit-def dead $eflags
568 TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
569 JNE_1 %bb.27, implicit killed $eflags
570 JMP_1 %bb.26
571
572 bb.26.bb54:
573 successors:
574
575
576 bb.27.bb55:
577 successors: %bb.29(0x7fffffff), %bb.28(0x00000001)
578
579 %43:gr32_abcd = MOV32r0 implicit-def dead $eflags
580 TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
581 JNE_1 %bb.29, implicit killed $eflags
582 JMP_1 %bb.28
583
584 bb.28.bb58:
585 successors:
586
587
588 bb.29.bb59:
589 successors: %bb.31(0x7fffffff), %bb.30(0x00000001)
590
591 %45:gr32_abcd = MOV32r0 implicit-def dead $eflags
592 TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
593 JNE_1 %bb.31, implicit killed $eflags
594 JMP_1 %bb.30
595
596 bb.30.bb61:
597 successors:
598
599
600 bb.31.bb62:
601 successors: %bb.32(0x00000001), %bb.33(0x7fffffff)
602
603 %47:gr32_abcd = MOV32r0 implicit-def dead $eflags
604 TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
605 JNE_1 %bb.33, implicit killed $eflags
606 JMP_1 %bb.32
607
608 bb.32.bb64:
609 successors:
610
611
612 bb.33.bb65:
613 successors: %bb.37(0x30000000), %bb.34(0x50000000)
614
615 %49:gr8 = MOV8ri 1
616 TEST8rr %49, %49, implicit-def $eflags
617 JNE_1 %bb.37, implicit killed $eflags
618 JMP_1 %bb.34
619
620 bb.34.bb67:
621 successors: %bb.36(0x00000001), %bb.35(0x7fffffff)
622
623 %81:gr32_abcd = MOV32r0 implicit-def dead $eflags
624 TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
625 JE_1 %bb.36, implicit killed $eflags
626
627 bb.35:
628 %82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
629 JMP_1 %bb.38
630
631 bb.36.bb70:
632 successors:
633
634
635 bb.37.bb72:
636 %81:gr32_abcd = COPY %0
637 %82:gr32 = COPY %0
638
639 bb.38.bb74:
640 successors: %bb.40(0x7fffffff), %bb.39(0x00000001)
641
642 ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
643 CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
644 ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
645 %52:gr32 = COPY killed $eax
646 MOV32mr undef %53:gr32, 1, $noreg, 0, $noreg, %81 :: (store 4 into `%18** undef`)
647 MOV32mr %82, 1, $noreg, 0, $noreg, %52 :: (store 4 into %ir.tmp79)
648 ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
649 CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
650 ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
651 MOV32mi %52, 1, $noreg, 36, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv :: (store 4 into %ir.tmp81)
652 MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1 :: (store 4 into `%18** undef`)
653 %55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg :: (load 4 from %ir.3)
654 CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tmp864)
655 JE_1 %bb.40, implicit killed $eflags
656 JMP_1 %bb.39
657
658 bb.39.bb89:
659 successors:
660
661
662 bb.40.bb90:
663 successors: %bb.42(0x00000001), %bb.41(0x7fffffff)
664
665 %56:gr32_abcd = MOV32r0 implicit-def dead $eflags
666 TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
667 JNE_1 %bb.42, implicit killed $eflags
668 JMP_1 %bb.41
669
670 bb.41.bb92:
671 successors: %bb.43(0x00000001), %bb.44(0x7fffffff)
672
673 %58:gr32_abcd = MOV32r0 implicit-def dead $eflags
674 TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
675 JNE_1 %bb.43, implicit killed $eflags
676 JMP_1 %bb.44
677
678 bb.42.bb94:
679 successors:
680
681
682 bb.43.bb96:
683 successors:
684
685
686 bb.44.bb97:
687 successors: %bb.45(0x00000001), %bb.46(0x7fffffff)
688
689 %60:gr32_abcd = MOV32r0 implicit-def dead $eflags
690 TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
691 JNE_1 %bb.46, implicit killed $eflags
692 JMP_1 %bb.45
693
694 bb.45.bb101:
695 successors:
696
697
698 bb.46.bb102:
699 successors: %bb.48(0x7fffffff), %bb.47(0x00000001)
700
701 %62:gr32_abcd = MOV32r0 implicit-def dead $eflags
702 TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
703 JNE_1 %bb.48, implicit killed $eflags
704 JMP_1 %bb.47
705
706 bb.47.bb103:
707 successors:
708
709
710 bb.48.bb104:
711 successors: %bb.50(0x7fffffff), %bb.49(0x00000001)
712
713 %64:gr32_abcd = MOV32r0 implicit-def dead $eflags
714 TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
715 JNE_1 %bb.50, implicit killed $eflags
716 JMP_1 %bb.49
717
718 bb.49.bb108:
719 successors:
720
721
722 bb.50.bb109:
723 successors: %bb.51(0x00000001), %bb.52(0x7fffffff)
724
725 %66:gr32_abcd = MOV32r0 implicit-def dead $eflags
726 TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
727 JNE_1 %bb.52, implicit killed $eflags
728 JMP_1 %bb.51
729
730 bb.51.bb111:
731 successors:
732
733
734 bb.52.bb112:
735 successors: %bb.54(0x7fffffff), %bb.53(0x00000001)
736
737 %68:gr32_abcd = MOV32r0 implicit-def dead $eflags
738 TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
739 JNE_1 %bb.54, implicit killed $eflags
740 JMP_1 %bb.53
741
742 bb.53.bb117:
743 successors:
744
745
746 bb.54.bb118:
747 successors: %bb.55(0x00000001), %bb.56(0x7fffffff)
748
749 %70:gr32_abcd = MOV32r0 implicit-def dead $eflags
750 TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
751 JNE_1 %bb.56, implicit killed $eflags
752 JMP_1 %bb.55
753
754 bb.55.bb120:
755 successors:
756
757
758 bb.56.bb121:
759 successors: %bb.57(0x00000001), %bb.58(0x7fffffff)
760
761 %72:gr32_abcd = MOV32r0 implicit-def dead $eflags
762 TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
763 JNE_1 %bb.58, implicit killed $eflags
764 JMP_1 %bb.57
765
766 bb.57.bb124:
767 successors:
768
769
770 bb.58.bb125:
771 successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
772
773 CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.4)
774 JE_1 %bb.62, implicit killed $eflags
775 JMP_1 %bb.59
776
777 bb.59.bb128:
778
779 bb.60.bb129:
780 successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
781
782 CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
783 JB_1 %bb.61, implicit killed $eflags
784 JMP_1 %bb.60
785
786 bb.61.bb133:
787 successors:
788
789
790 bb.62.bb135:
791 successors: %bb.63, %bb.64
792
793 %76:gr32_abcd = MOV32r0 implicit-def dead $eflags
794 TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
795 JNE_1 %bb.64, implicit killed $eflags
796 JMP_1 %bb.63
797
798 bb.63.bb137:
799 successors:
800
801
802 bb.64.bb138:
803
804 ...