llvm.org GIT mirror llvm / 102d0f3
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC The SelectionDAG bad a special case for ISD::SELECT_CC, where it would allow targets to specify: setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); to indicate that they wanted to expand ISD::SELECT_CC for all types. This wasn't applied correctly everywhere, and it makes writing new DAG patterns with ISD::SELECT_CC difficult. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
7 changed file(s) with 25 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
45664566
45674567 // fold selects based on a setcc into other things, such as min/max/abs
45684568 if (N0.getOpcode() == ISD::SETCC) {
4569 // FIXME:
4570 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
4571 // having to say they don't support SELECT_CC on every type the DAG knows
4572 // about, since there is no way to mark an opcode illegal at all value types
4573 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
4574 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
4569 if ((!LegalOperations &&
4570 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4571 TLI.isOperationLegal(ISD::SELECT_CC, VT))
45754572 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
45764573 N0.getOperand(0), N0.getOperand(1),
45774574 N1, N2, N0.getOperand(2));
70277024 }
70287025
70297026 // The next optimizations are desirable only if SELECT_CC can be lowered.
7030 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
7031 // having to say they don't support SELECT_CC on every type the DAG knows
7032 // about, since there is no way to mark an opcode illegal at all value types
7033 // (See also visitSELECT)
7034 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
7027 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
70357028 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
70367029 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
70377030 !VT.isVector() &&
70847077 }
70857078
70867079 // The next optimizations are desirable only if SELECT_CC can be lowered.
7087 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
7088 // having to say they don't support SELECT_CC on every type the DAG knows
7089 // about, since there is no way to mark an opcode illegal at all value types
7090 // (See also visitSELECT)
7091 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) {
7080 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
70927081 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
70937082
70947083 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
13381338
13391339 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
13401340 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1341 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
13421341
13431342 } else {
13441343
13451344 // Hexagon has no select or setcc: expand to SELECT_CC.
13461345 setOperationAction(ISD::SELECT, MVT::f32, Expand);
13471346 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1348
1349 // This is a workaround documented in DAGCombiner.cpp:2892 We don't
1350 // support SELECT_CC on every type.
1351 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1352
13531347 }
13541348
13551349 if (EmitJumpTables) {
286286 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
287287 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
288288 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
289 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
289 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
290 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
290291 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
291292 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
292293 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
129129 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
130130
131131 // Operations not directly supported by NVPTX.
132 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
132 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
133 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
134 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
135 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
136 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
133139 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
134140 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
135141 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
439439 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
440440 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
441441 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
444 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
445 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
443449 if (Subtarget->is64Bit())
444450 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
445451 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
857863 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
858864 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
859865 setOperationAction(ISD::VSELECT, VT, Expand);
866 setOperationAction(ISD::SELECT_CC, VT, Expand);
860867 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
861868 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
862869 setTruncStoreAction(VT,
9696 setOperationAction(ISD::ADDE, MVT::i32, Expand);
9797 setOperationAction(ISD::SUBC, MVT::i32, Expand);
9898 setOperationAction(ISD::SUBE, MVT::i32, Expand);
99
100 // Stop the combiner recombining select and set_cc
101 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
10299
103100 // 64bit
104101 setOperationAction(ISD::ADD, MVT::i64, Custom);
1515 ; SOURCE-SCHED: lw
1616 ; SOURCE-SCHED: lui
1717 ; SOURCE-SCHED: sw
18 ; SOURCE-SCHED: addiu
19 ; SOURCE-SCHED: addiu
18 ; SOURCE-SCHED: lw
19 ; SOURCE-SCHED: lwc1
20 ; SOURCE-SCHED: mtc1
2021 ; SOURCE-SCHED: c.olt.s
21 ; SOURCE-SCHED: movt
22 ; SOURCE-SCHED: mtc1
2322 ; SOURCE-SCHED: jr
24
2523 store float 0.000000e+00, float* @gf0, align 4
2624 store float 1.000000e+00, float* @gf1, align 4
2725 %cmp = fcmp olt float %a, %b