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Merging r355825: ------------------------------------------------------------------------ r355825 | petarj | 2019-03-11 07:13:31 -0700 (Mon, 11 Mar 2019) | 10 lines [MIPS][microMIPS] Add a pattern to match TruncIntFP A pattern needed to match TruncIntFP was missing. This was causing multiple tests from llvm test suite to fail during compilation for micromips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58722 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@358936 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 months ago
3 changed file(s) with 426 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
10391039 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
10401040 FGR32Opnd, II_TRUNC>;
10411041 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1042 AFGR64Opnd, II_TRUNC>;
1042 FGR64Opnd, II_TRUNC>;
10431043 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
10441044 II_SQRT_S, fsqrt>;
10451045 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
17491749 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
17501750 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
17511751 (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1752 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
1753 (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6;
17521754
17531755 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
17541756 (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
424424 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
425425 (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
426426 FGR_32;
427 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
428 (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6,
429 FGR_64;
430 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
431 (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6;
427432
428433 // Selects
429434 defm : MovzPats0,
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\
2 ; RUN: FileCheck %s -check-prefixes=M32
3 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\
4 ; RUN: FileCheck %s -check-prefixes=M32
5 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\
6 ; RUN: FileCheck %s -check-prefixes=M32R2-FP64
7 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\
8 ; RUN: FileCheck %s -check-prefixes=M32R2-SF
9 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\
10 ; RUN: FileCheck %s -check-prefixes=M32R3R5
11 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\
12 ; RUN: FileCheck %s -check-prefixes=M32R3R5
13 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\
14 ; RUN: FileCheck %s -check-prefixes=M32R6
15 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\
16 ; RUN: FileCheck %s -check-prefixes=M64
17 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\
18 ; RUN: FileCheck %s -check-prefixes=M64
19 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\
20 ; RUN: FileCheck %s -check-prefixes=M64
21 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\
22 ; RUN: FileCheck %s -check-prefixes=M64R6
23 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\
24 ; RUN: FileCheck %s -check-prefixes=MMR2-FP32
25 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\
26 ; RUN: FileCheck %s -check-prefixes=MMR2-FP64
27 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\
28 ; RUN: FileCheck %s -check-prefixes=MMR2-SF
29 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\
30 ; RUN: FileCheck %s -check-prefixes=MMR6
31 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\
32 ; RUN: FileCheck %s -check-prefixes=MMR6-SF
33
34 ; Test that fptosi can be matched for MIPS targets for various FPU
35 ; configurations
36
37 define i32 @test1(float %t) {
38 ; M32-LABEL: test1:
39 ; M32: # %bb.0: # %entry
40 ; M32-NEXT: trunc.w.s $f0, $f12 #
41 ; M32-NEXT: #
42 ; M32-NEXT: # >
43 ; M32-NEXT: jr $ra #
44 ; M32-NEXT: # >
45 ; M32-NEXT: mfc1 $2, $f0 #
46 ; M32-NEXT: #
47 ; M32-NEXT: # >
48 ;
49 ; M32R2-FP64-LABEL: test1:
50 ; M32R2-FP64: # %bb.0: # %entry
51 ; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 #
52 ; M32R2-FP64-NEXT: #
53 ; M32R2-FP64-NEXT: # >
54 ; M32R2-FP64-NEXT: jr $ra #
55 ; M32R2-FP64-NEXT: # >
56 ; M32R2-FP64-NEXT: mfc1 $2, $f0 #
57 ; M32R2-FP64-NEXT: #
58 ; M32R2-FP64-NEXT: # >
59 ;
60 ; M32R2-SF-LABEL: test1:
61 ; M32R2-SF: # %bb.0: # %entry
62 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 #
63 ; M32R2-SF-NEXT: #
64 ; M32R2-SF-NEXT: #
65 ; M32R2-SF-NEXT: # >
66 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
67 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
68 ; M32R2-SF-NEXT: #
69 ; M32R2-SF-NEXT: #
70 ; M32R2-SF-NEXT: #
71 ; M32R2-SF-NEXT: # >
72 ; M32R2-SF-NEXT: .cfi_offset 31, -4
73 ; M32R2-SF-NEXT: jal __fixsfsi #
74 ; M32R2-SF-NEXT: # >
75 ; M32R2-SF-NEXT: nop #
76 ; M32R2-SF-NEXT: #
77 ; M32R2-SF-NEXT: #
78 ; M32R2-SF-NEXT: # >
79 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
80 ; M32R2-SF-NEXT: #
81 ; M32R2-SF-NEXT: #
82 ; M32R2-SF-NEXT: #
83 ; M32R2-SF-NEXT: # >
84 ; M32R2-SF-NEXT: jr $ra #
85 ; M32R2-SF-NEXT: # >
86 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 #
87 ; M32R2-SF-NEXT: #
88 ; M32R2-SF-NEXT: #
89 ; M32R2-SF-NEXT: # >
90 ;
91 ; M32R3R5-LABEL: test1:
92 ; M32R3R5: # %bb.0: # %entry
93 ; M32R3R5-NEXT: trunc.w.s $f0, $f12 #
94 ; M32R3R5-NEXT: #
95 ; M32R3R5-NEXT: # >
96 ; M32R3R5-NEXT: jr $ra #
97 ; M32R3R5-NEXT: # >
98 ; M32R3R5-NEXT: mfc1 $2, $f0 #
99 ; M32R3R5-NEXT: #
100 ; M32R3R5-NEXT: # >
101 ;
102 ; M32R6-LABEL: test1:
103 ; M32R6: # %bb.0: # %entry
104 ; M32R6-NEXT: trunc.w.s $f0, $f12 #
105 ; M32R6-NEXT: #
106 ; M32R6-NEXT: # >
107 ; M32R6-NEXT: jr $ra #
108 ; M32R6-NEXT: #
109 ; M32R6-NEXT: # >
110 ; M32R6-NEXT: mfc1 $2, $f0 #
111 ; M32R6-NEXT: #
112 ; M32R6-NEXT: # >
113 ;
114 ; M64-LABEL: test1:
115 ; M64: # %bb.0: # %entry
116 ; M64-NEXT: trunc.w.s $f0, $f12 #
117 ; M64-NEXT: #
118 ; M64-NEXT: # >
119 ; M64-NEXT: jr $ra #
120 ; M64-NEXT: # >
121 ; M64-NEXT: mfc1 $2, $f0 #
122 ; M64-NEXT: #
123 ; M64-NEXT: # >
124 ;
125 ; M64R6-LABEL: test1:
126 ; M64R6: # %bb.0: # %entry
127 ; M64R6-NEXT: trunc.w.s $f0, $f12 #
128 ; M64R6-NEXT: #
129 ; M64R6-NEXT: # >
130 ; M64R6-NEXT: jr $ra #
131 ; M64R6-NEXT: #
132 ; M64R6-NEXT: # >
133 ; M64R6-NEXT: mfc1 $2, $f0 #
134 ; M64R6-NEXT: #
135 ; M64R6-NEXT: # >
136 ;
137 ; MMR2-FP32-LABEL: test1:
138 ; MMR2-FP32: # %bb.0: # %entry
139 ; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 #
140 ; MMR2-FP32-NEXT: #
141 ; MMR2-FP32-NEXT: # >
142 ; MMR2-FP32-NEXT: jr $ra #
143 ; MMR2-FP32-NEXT: # >
144 ; MMR2-FP32-NEXT: mfc1 $2, $f0 #
145 ; MMR2-FP32-NEXT: #
146 ; MMR2-FP32-NEXT: # >
147 ;
148 ; MMR2-FP64-LABEL: test1:
149 ; MMR2-FP64: # %bb.0: # %entry
150 ; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 #
151 ; MMR2-FP64-NEXT: #
152 ; MMR2-FP64-NEXT: # >
153 ; MMR2-FP64-NEXT: jr $ra #
154 ; MMR2-FP64-NEXT: # >
155 ; MMR2-FP64-NEXT: mfc1 $2, $f0 #
156 ; MMR2-FP64-NEXT: #
157 ; MMR2-FP64-NEXT: # >
158 ;
159 ; MMR2-SF-LABEL: test1:
160 ; MMR2-SF: # %bb.0: # %entry
161 ; MMR2-SF-NEXT: addiusp -24 #
162 ; MMR2-SF-NEXT: # >
163 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
164 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
165 ; MMR2-SF-NEXT: #
166 ; MMR2-SF-NEXT: #
167 ; MMR2-SF-NEXT: #
168 ; MMR2-SF-NEXT: # >
169 ; MMR2-SF-NEXT: .cfi_offset 31, -4
170 ; MMR2-SF-NEXT: jal __fixsfsi #
171 ; MMR2-SF-NEXT: # >
172 ; MMR2-SF-NEXT: nop #
173 ; MMR2-SF-NEXT: #
174 ; MMR2-SF-NEXT: #
175 ; MMR2-SF-NEXT: # >
176 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
177 ; MMR2-SF-NEXT: #
178 ; MMR2-SF-NEXT: #
179 ; MMR2-SF-NEXT: #
180 ; MMR2-SF-NEXT: # >
181 ; MMR2-SF-NEXT: addiusp 24 #
182 ; MMR2-SF-NEXT: # >
183 ; MMR2-SF-NEXT: jrc $ra #
184 ; MMR2-SF-NEXT: # >
185 ;
186 ; MMR6-LABEL: test1:
187 ; MMR6: # %bb.0: # %entry
188 ; MMR6-NEXT: trunc.w.s $f0, $f12 #
189 ; MMR6-NEXT: #
190 ; MMR6-NEXT: # >
191 ; MMR6-NEXT: mfc1 $2, $f0 #
192 ; MMR6-NEXT: #
193 ; MMR6-NEXT: # >
194 ; MMR6-NEXT: jrc $ra #
195 ; MMR6-NEXT: # >
196 ;
197 ; MMR6-SF-LABEL: test1:
198 ; MMR6-SF: # %bb.0: # %entry
199 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 #
200 ; MMR6-SF-NEXT: #
201 ; MMR6-SF-NEXT: #
202 ; MMR6-SF-NEXT: # >
203 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
204 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
205 ; MMR6-SF-NEXT: #
206 ; MMR6-SF-NEXT: #
207 ; MMR6-SF-NEXT: #
208 ; MMR6-SF-NEXT: # >
209 ; MMR6-SF-NEXT: .cfi_offset 31, -4
210 ; MMR6-SF-NEXT: jalr __fixsfsi #
211 ; MMR6-SF-NEXT: # >
212 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
213 ; MMR6-SF-NEXT: #
214 ; MMR6-SF-NEXT: #
215 ; MMR6-SF-NEXT: #
216 ; MMR6-SF-NEXT: # >
217 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 #
218 ; MMR6-SF-NEXT: #
219 ; MMR6-SF-NEXT: #
220 ; MMR6-SF-NEXT: # >
221 ; MMR6-SF-NEXT: jrc $ra #
222 ; MMR6-SF-NEXT: # >
223 entry:
224 %conv = fptosi float %t to i32
225 ret i32 %conv
226 }
227
228 define i32 @test2(double %t) {
229 ; M32-LABEL: test2:
230 ; M32: # %bb.0: # %entry
231 ; M32-NEXT: trunc.w.d $f0, $f12 #
232 ; M32-NEXT: #
233 ; M32-NEXT: # >
234 ; M32-NEXT: jr $ra #
235 ; M32-NEXT: # >
236 ; M32-NEXT: mfc1 $2, $f0 #
237 ; M32-NEXT: #
238 ; M32-NEXT: # >
239 ;
240 ; M32R2-FP64-LABEL: test2:
241 ; M32R2-FP64: # %bb.0: # %entry
242 ; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 #
243 ; M32R2-FP64-NEXT: #
244 ; M32R2-FP64-NEXT: # >
245 ; M32R2-FP64-NEXT: jr $ra #
246 ; M32R2-FP64-NEXT: # >
247 ; M32R2-FP64-NEXT: mfc1 $2, $f0 #
248 ; M32R2-FP64-NEXT: #
249 ; M32R2-FP64-NEXT: # >
250 ;
251 ; M32R2-SF-LABEL: test2:
252 ; M32R2-SF: # %bb.0: # %entry
253 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 #
254 ; M32R2-SF-NEXT: #
255 ; M32R2-SF-NEXT: #
256 ; M32R2-SF-NEXT: # >
257 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
258 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
259 ; M32R2-SF-NEXT: #
260 ; M32R2-SF-NEXT: #
261 ; M32R2-SF-NEXT: #
262 ; M32R2-SF-NEXT: # >
263 ; M32R2-SF-NEXT: .cfi_offset 31, -4
264 ; M32R2-SF-NEXT: jal __fixdfsi #
265 ; M32R2-SF-NEXT: # >
266 ; M32R2-SF-NEXT: nop #
267 ; M32R2-SF-NEXT: #
268 ; M32R2-SF-NEXT: #
269 ; M32R2-SF-NEXT: # >
270 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
271 ; M32R2-SF-NEXT: #
272 ; M32R2-SF-NEXT: #
273 ; M32R2-SF-NEXT: #
274 ; M32R2-SF-NEXT: # >
275 ; M32R2-SF-NEXT: jr $ra #
276 ; M32R2-SF-NEXT: # >
277 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 #
278 ; M32R2-SF-NEXT: #
279 ; M32R2-SF-NEXT: #
280 ; M32R2-SF-NEXT: # >
281 ;
282 ; M32R3R5-LABEL: test2:
283 ; M32R3R5: # %bb.0: # %entry
284 ; M32R3R5-NEXT: trunc.w.d $f0, $f12 #
285 ; M32R3R5-NEXT: #
286 ; M32R3R5-NEXT: # >
287 ; M32R3R5-NEXT: jr $ra #
288 ; M32R3R5-NEXT: # >
289 ; M32R3R5-NEXT: mfc1 $2, $f0 #
290 ; M32R3R5-NEXT: #
291 ; M32R3R5-NEXT: # >
292 ;
293 ; M32R6-LABEL: test2:
294 ; M32R6: # %bb.0: # %entry
295 ; M32R6-NEXT: trunc.w.d $f0, $f12 #
296 ; M32R6-NEXT: #
297 ; M32R6-NEXT: # >
298 ; M32R6-NEXT: jr $ra #
299 ; M32R6-NEXT: #
300 ; M32R6-NEXT: # >
301 ; M32R6-NEXT: mfc1 $2, $f0 #
302 ; M32R6-NEXT: #
303 ; M32R6-NEXT: # >
304 ;
305 ; M64-LABEL: test2:
306 ; M64: # %bb.0: # %entry
307 ; M64-NEXT: trunc.w.d $f0, $f12 #
308 ; M64-NEXT: #
309 ; M64-NEXT: # >
310 ; M64-NEXT: jr $ra #
311 ; M64-NEXT: # >
312 ; M64-NEXT: mfc1 $2, $f0 #
313 ; M64-NEXT: #
314 ; M64-NEXT: # >
315 ;
316 ; M64R6-LABEL: test2:
317 ; M64R6: # %bb.0: # %entry
318 ; M64R6-NEXT: trunc.w.d $f0, $f12 #
319 ; M64R6-NEXT: #
320 ; M64R6-NEXT: # >
321 ; M64R6-NEXT: jr $ra #
322 ; M64R6-NEXT: #
323 ; M64R6-NEXT: # >
324 ; M64R6-NEXT: mfc1 $2, $f0 #
325 ; M64R6-NEXT: #
326 ; M64R6-NEXT: # >
327 ;
328 ; MMR2-FP32-LABEL: test2:
329 ; MMR2-FP32: # %bb.0: # %entry
330 ; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 #
331 ; MMR2-FP32-NEXT: #
332 ; MMR2-FP32-NEXT: # >
333 ; MMR2-FP32-NEXT: jr $ra #
334 ; MMR2-FP32-NEXT: # >
335 ; MMR2-FP32-NEXT: mfc1 $2, $f0 #
336 ; MMR2-FP32-NEXT: #
337 ; MMR2-FP32-NEXT: # >
338 ;
339 ; MMR2-FP64-LABEL: test2:
340 ; MMR2-FP64: # %bb.0: # %entry
341 ; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 #
342 ; MMR2-FP64-NEXT: #
343 ; MMR2-FP64-NEXT: # >
344 ; MMR2-FP64-NEXT: jr $ra #
345 ; MMR2-FP64-NEXT: # >
346 ; MMR2-FP64-NEXT: mfc1 $2, $f0 #
347 ; MMR2-FP64-NEXT: #
348 ; MMR2-FP64-NEXT: # >
349 ;
350 ; MMR2-SF-LABEL: test2:
351 ; MMR2-SF: # %bb.0: # %entry
352 ; MMR2-SF-NEXT: addiusp -24 #
353 ; MMR2-SF-NEXT: # >
354 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
355 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
356 ; MMR2-SF-NEXT: #
357 ; MMR2-SF-NEXT: #
358 ; MMR2-SF-NEXT: #
359 ; MMR2-SF-NEXT: # >
360 ; MMR2-SF-NEXT: .cfi_offset 31, -4
361 ; MMR2-SF-NEXT: jal __fixdfsi #
362 ; MMR2-SF-NEXT: # >
363 ; MMR2-SF-NEXT: nop #
364 ; MMR2-SF-NEXT: #
365 ; MMR2-SF-NEXT: #
366 ; MMR2-SF-NEXT: # >
367 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
368 ; MMR2-SF-NEXT: #
369 ; MMR2-SF-NEXT: #
370 ; MMR2-SF-NEXT: #
371 ; MMR2-SF-NEXT: # >
372 ; MMR2-SF-NEXT: addiusp 24 #
373 ; MMR2-SF-NEXT: # >
374 ; MMR2-SF-NEXT: jrc $ra #
375 ; MMR2-SF-NEXT: # >
376 ;
377 ; MMR6-LABEL: test2:
378 ; MMR6: # %bb.0: # %entry
379 ; MMR6-NEXT: trunc.w.d $f0, $f12 #
380 ; MMR6-NEXT: #
381 ; MMR6-NEXT: # >
382 ; MMR6-NEXT: mfc1 $2, $f0 #
383 ; MMR6-NEXT: #
384 ; MMR6-NEXT: # >
385 ; MMR6-NEXT: jrc $ra #
386 ; MMR6-NEXT: # >
387 ;
388 ; MMR6-SF-LABEL: test2:
389 ; MMR6-SF: # %bb.0: # %entry
390 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 #
391 ; MMR6-SF-NEXT: #
392 ; MMR6-SF-NEXT: #
393 ; MMR6-SF-NEXT: # >
394 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
395 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
396 ; MMR6-SF-NEXT: #
397 ; MMR6-SF-NEXT: #
398 ; MMR6-SF-NEXT: #
399 ; MMR6-SF-NEXT: # >
400 ; MMR6-SF-NEXT: .cfi_offset 31, -4
401 ; MMR6-SF-NEXT: jalr __fixdfsi #
402 ; MMR6-SF-NEXT: # >
403 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
404 ; MMR6-SF-NEXT: #
405 ; MMR6-SF-NEXT: #
406 ; MMR6-SF-NEXT: #
407 ; MMR6-SF-NEXT: # >
408 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 #
409 ; MMR6-SF-NEXT: #
410 ; MMR6-SF-NEXT: #
411 ; MMR6-SF-NEXT: # >
412 ; MMR6-SF-NEXT: jrc $ra #
413 ; MMR6-SF-NEXT: # >
414 entry:
415 %conv = fptosi double %t to i32
416 ret i32 %conv
417 }