llvm.org GIT mirror llvm / 0fe443d
ARM: implement support for the UDF mnemonic The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208751 91177308-0d34-0410-b5e6-96231b3b80d8 Saleem Abdulrasool 6 years ago
11 changed file(s) with 135 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
19661966 let Inst{3-0} = opt;
19671967 }
19681968
1969 // A8.8.247 UDF - Undefined (Encoding A1)
1970 def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
1971 "udf", "\t$imm16", []> {
1972 bits<16> imm16;
1973 let Inst{31-28} = 0b1110; // AL
1974 let Inst{27-25} = 0b011;
1975 let Inst{24-20} = 0b11111;
1976 let Inst{19-8} = imm16{15-4};
1977 let Inst{7-4} = 0b1111;
1978 let Inst{3-0} = imm16{3-0};
1979 }
1980
19691981 /*
19701982 * A5.4 Permanently UNDEFINED instructions.
19711983 *
11911191 "tst", "\t$Rn, $Rm",
11921192 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
11931193 Sched<[WriteALU]>;
1194
1195 // A8.8.247 UDF - Undefined (Encoding T1)
1196 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", []>,
1197 Encoding16 {
1198 bits<8> imm8;
1199 let Inst{15-12} = 0b1101;
1200 let Inst{11-8} = 0b1110;
1201 let Inst{7-0} = imm8;
1202 }
11941203
11951204 // Zero-extend byte
11961205 def tUXTB : // A8.6.262
24042404 let Inst{25} = 1;
24052405 let Inst{24-20} = 0b11100;
24062406 let Inst{15} = 0;
2407 }
2408
2409 // A8.8.247 UDF - Undefined (Encoding T2)
2410 def t2UDF
2411 : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", []> {
2412 bits<16> imm16;
2413 let Inst{31-29} = 0b111;
2414 let Inst{28-27} = 0b10;
2415 let Inst{26-20} = 0b1111111;
2416 let Inst{19-16} = imm16{15-12};
2417 let Inst{15} = 0b1;
2418 let Inst{14-12} = 0b010;
2419 let Inst{11-0} = imm16{11-0};
24072420 }
24082421
24092422 // A8.6.18 BFI - Bitfield insert (Encoding T1)
50935093
50945094 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
50955095 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5096 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
5097 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5096 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5097 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5098 Mnemonic.startswith("vsel") ||
50985099 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
50995100 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
51005101 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
0 @ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s
1
2 .syntax unified
3 .text
4 .arm
5
6 undefined:
7 udfpl
8
9 @ CHECK: error: instruction 'udf' is not predicable, but condition code specified
10 @ CHECK: udfpl
11 @ CHECK: ^
12
13 udf #65536
14
15 @ CHECK: error: invalid operand for instruction
16 @ CHECK: udf #65536
17 @ CHECK: ^
18
0 @ RUN: llvm-mc -triple arm-eabi -show-encoding %s | FileCheck %s
1
2 .syntax unified
3 .text
4 .arm
5
6 undefined:
7 udf #0
8
9 @ CHECK: udf #0 @ encoding: [0xf0,0x00,0xf0,0xe7]
10
0 @ RUN: not llvm-mc -triple thumbv7-eabi -mattr +thumb2 %s 2>&1 | FileCheck %s
1
2 .syntax unified
3 .text
4 .thumb
5
6 undefined:
7 udfpl
8
9 @ CHECK: error: instruction 'udf' is not predicable, but condition code specified
10 @ CHECK: udfpl
11 @ CHECK: ^
12
13 udf #256
14
15 @ CHECK: error: instruction requires: arm-mode
16 @ CHECK: udf #256
17 @ CHECK: ^
18
19 udf.w #65536
20
21 @ CHECK: error: invalid operand for instruction
22 @ CHECK: udf.w #65536
23 @ CHECK: ^
24
0 @ RUN: llvm-mc -triple thumbv7-eabi -mattr +thumb2 -show-encoding %s | FileCheck %s
1
2 .syntax unified
3 .text
4 .thumb
5
6 undefined:
7 udf #0
8 udf.w #0
9
10 @ CHECK: udf #0 @ encoding: [0x00,0xde]
11 @ CHECK: udf.w #0 @ encoding: [0xf0,0xf7,0x00,0xa0]
12
0 @ RUN: not llvm-mc -triple thumbv6m-eabi %s 2>&1 | FileCheck %s
1
2 .syntax unified
3 .text
4 .thumb
5
6 undefined:
7 udfpl
8
9 @ CHECK: error: conditional execution not supported in Thumb1
10 @ CHECK: udfpl
11 @ CHECK: ^
12
13 udf #256
14
15 @ CHECK: error: instruction requires: arm-mode
16 @ CHECK: udf #256
17 @ CHECK: ^
18
0 @ RUN: llvm-mc -triple thumbv6m-eabi -show-encoding %s | FileCheck %s
1
2 .syntax unified
3 .text
4 .thumb
5
6 undefined:
7 udf #0
8
9 @ CHECK: udf #0 @ encoding: [0x00,0xde]
10
1919 [0xaf 0xf7 0x44 0x8b]
2020 # CHECK: warning: invalid instruction encoding
2121 # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
22
23 # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
24 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
25 # -------------------------------------------------------------------------------------------------
26 # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
27 # -------------------------------------------------------------------------------------------------
28 #
29 # if cond = '1110' then UNDEFINED
30 [0x6f 0xde]
31 # CHECK: invalid instruction encoding
32 # CHECK-NEXT: [0x6f 0xde]
3322
3423 #------------------------------------------------------------------------------
3524 # Undefined encoding for it
246235 [0xe4 0xe9 0x02 0x46]
247236 # CHECK: warning: potentially undefined instruction encoding
248237 # CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
249
250 #------------------------------------------------------------------------------
251 # Undefined encodings for NEON/VFP instructions with invalid predicate bits
252 #------------------------------------------------------------------------------
253
254 # VABS
255 [0x40 0xde 0x00 0x0a]
256 # CHECK: invalid instruction encoding
257 # CHECK-NEXT: [0x40 0xde 0x00 0x0a]
258
259
260 # VMLA
261 [0xf0 0xde 0xe0 0x0b]
262 # CHECK: invalid instruction encoding
263 # CHECK-NEXT: [0xf0 0xde 0xe0 0x0b]
264
265 # VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
266
267 # VMOV
268 [0x00 0xde 0x10 0x0b]
269 # CHECK: invalid instruction encoding
270 # CHECK-NEXT: [0x00 0xde 0x10 0x0b]
271
272 # VDUP
273 [0xff 0xde 0xf0 0xfb]
274 # CHECK: invalid instruction encoding
275 # CHECK-NEXT: [0xff 0xde 0xf0 0xfb]
276
277238
278239 #------------------------------------------------------------------------------
279240 # Undefined encodings for NEON vld instructions