llvm.org GIT mirror llvm / 0fbe023
[X86] Correctly use SSE registers if no-x87 is selected. Fix use of SSE1 registers for f32 ops in no-x87 mode. Notably, allow use of SSE instructions for f32 operations in 64-bit mode (but not 32-bit which is disallowed by callign convention). Also avoid translating memset/memcopy/memmove into SSE registers without X87 for 32-bit mode. This fixes PR38738. Reviewers: nickdesaulniers, craig.topper Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D52555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343689 91177308-0d34-0410-b5e6-96231b3b80d8 Nirav Dave 1 year, 9 months ago
3 changed file(s) with 302 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
542542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
543543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
544544
545 // Expand FP immediates into loads from the stack, except for the special
546 // cases we handle.
547 addLegalFPImmediate(APFloat(+0.0)); // xorpd
548 addLegalFPImmediate(APFloat(+0.0f)); // xorps
549 } else if (UseX87 && X86ScalarSSEf32) {
545 } else if (!useSoftFloat() && X86ScalarSSEf32 && (UseX87 || Is64Bit)) {
550546 // Use SSE for f32, x87 for f64.
551547 // Set up the FP register classes.
552548 addRegisterClass(MVT::f32, &X86::FR32RegClass);
553 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
549 if (UseX87)
550 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554551
555552 // Use ANDPS to simulate FABS.
556553 setOperationAction(ISD::FABS , MVT::f32, Custom);
558555 // Use XORP to simulate FNEG.
559556 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560557
561 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
558 if (UseX87)
559 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562560
563561 // Use ANDPS and ORPS to simulate FCOPYSIGN.
564 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
562 if (UseX87)
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
565564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566565
567566 // We don't support sin/cos/fmod
569568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
570569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571570
572 // Special cases we handle for FP constants.
573 addLegalFPImmediate(APFloat(+0.0f)); // xorps
574 addLegalFPImmediate(APFloat(+0.0)); // FLD0
575 addLegalFPImmediate(APFloat(+1.0)); // FLD1
576 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
577 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578
579 // Always expand sin/cos functions even though x87 has an instruction.
580 setOperationAction(ISD::FSIN , MVT::f64, Expand);
581 setOperationAction(ISD::FCOS , MVT::f64, Expand);
582 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
571 if (UseX87) {
572 // Always expand sin/cos functions even though x87 has an instruction.
573 setOperationAction(ISD::FSIN, MVT::f64, Expand);
574 setOperationAction(ISD::FCOS, MVT::f64, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
576 }
583577 } else if (UseX87) {
584578 // f32 and f64 in x87.
585579 // Set up the FP register classes.
595589 setOperationAction(ISD::FCOS , VT, Expand);
596590 setOperationAction(ISD::FSINCOS, VT, Expand);
597591 }
598 addLegalFPImmediate(APFloat(+0.0)); // FLD0
599 addLegalFPImmediate(APFloat(+1.0)); // FLD1
600 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
601 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
602 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
592 }
593
594 // Expand FP32 immediates into loads from the stack, save special cases.
595 if (isTypeLegal(MVT::f32)) {
596 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
597 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
598 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
599 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
600 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
601 } else // SSE immediates.
602 addLegalFPImmediate(APFloat(+0.0f)); // xorps
603 }
604 // Expand FP64 immediates into loads from the stack, save special cases.
605 if (isTypeLegal(MVT::f64)) {
606 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) {
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 } else // SSE immediates.
612 addLegalFPImmediate(APFloat(+0.0)); // xorpd
606613 }
607614
608615 // We don't support FMA.
19351942 if (Subtarget.hasSSE2())
19361943 return MVT::v16i8;
19371944 // TODO: Can SSE1 handle a byte vector?
1938 if (Subtarget.hasSSE1())
1945 // If we have SSE1 registers we should be able to use them.
1946 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()))
19391947 return MVT::v4f32;
19401948 } else if ((!IsMemset || ZeroMemset) && !MemcpyStrSrc && Size >= 8 &&
19411949 !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+sse,-sse2 %s | FileCheck --check-prefixes=X64SSE %s
2 ; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+sse,-sse2 %s | FileCheck --check-prefixes=X86SSE %s
3 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+sse2,-sse3 %s | FileCheck --check-prefixes=X64SSE2 %s
4 ; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+sse2,-sse3 %s | FileCheck --check-prefixes=X86SSE2 %s
5 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -mattr=-x87,+avx,-avx2 %s | FileCheck --check-prefixes=X64AVX %s
6 ; RUN: llc -mtriple=i686-unknown-linux-gnu -o - -mattr=-x87,+avx,-avx2 %s | FileCheck --check-prefixes=X86AVX %s
7
8
9 %struct.params = type { double, double }
10
11 define i32 @pr38738() {
12 ; X64SSE-LABEL: pr38738:
13 ; X64SSE: # %bb.0: # %entry
14 ; X64SSE-NEXT: xorps %xmm0, %xmm0
15 ; X64SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
16 ; X64SSE-NEXT: movl $0, -{{[0-9]+}}(%rsp)
17 ; X64SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
18 ; X64SSE-NEXT: retq
19 ;
20 ; X86SSE-LABEL: pr38738:
21 ; X86SSE: # %bb.0: # %entry
22 ; X86SSE-NEXT: subl $28, %esp
23 ; X86SSE-NEXT: .cfi_def_cfa_offset 32
24 ; X86SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
25 ; X86SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
26 ; X86SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
27 ; X86SSE-NEXT: movl $0, (%esp)
28 ; X86SSE-NEXT: movl $0, {{[0-9]+}}(%esp)
29 ; X86SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
30 ; X86SSE-NEXT: addl $28, %esp
31 ; X86SSE-NEXT: .cfi_def_cfa_offset 4
32 ; X86SSE-NEXT: retl
33 ;
34 ; X64SSE2-LABEL: pr38738:
35 ; X64SSE2: # %bb.0: # %entry
36 ; X64SSE2-NEXT: xorps %xmm0, %xmm0
37 ; X64SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
38 ; X64SSE2-NEXT: movl $0, -{{[0-9]+}}(%rsp)
39 ; X64SSE2-NEXT: movl -{{[0-9]+}}(%rsp), %eax
40 ; X64SSE2-NEXT: retq
41 ;
42 ; X86SSE2-LABEL: pr38738:
43 ; X86SSE2: # %bb.0: # %entry
44 ; X86SSE2-NEXT: subl $44, %esp
45 ; X86SSE2-NEXT: .cfi_def_cfa_offset 48
46 ; X86SSE2-NEXT: xorps %xmm0, %xmm0
47 ; X86SSE2-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
48 ; X86SSE2-NEXT: movl $0, {{[0-9]+}}(%esp)
49 ; X86SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
50 ; X86SSE2-NEXT: addl $44, %esp
51 ; X86SSE2-NEXT: .cfi_def_cfa_offset 4
52 ; X86SSE2-NEXT: retl
53 ;
54 ; X64AVX-LABEL: pr38738:
55 ; X64AVX: # %bb.0: # %entry
56 ; X64AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
57 ; X64AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
58 ; X64AVX-NEXT: movl $0, -{{[0-9]+}}(%rsp)
59 ; X64AVX-NEXT: movl -{{[0-9]+}}(%rsp), %eax
60 ; X64AVX-NEXT: retq
61 ;
62 ; X86AVX-LABEL: pr38738:
63 ; X86AVX: # %bb.0: # %entry
64 ; X86AVX-NEXT: subl $44, %esp
65 ; X86AVX-NEXT: .cfi_def_cfa_offset 48
66 ; X86AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
67 ; X86AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
68 ; X86AVX-NEXT: movl $0, {{[0-9]+}}(%esp)
69 ; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
70 ; X86AVX-NEXT: addl $44, %esp
71 ; X86AVX-NEXT: .cfi_def_cfa_offset 4
72 ; X86AVX-NEXT: retl
73 entry:
74 %retval = alloca i32, align 4
75 %dlg_sys_param = alloca %struct.params, align 8
76 %total_active_bw = alloca float, align 4
77 %0 = bitcast %struct.params* %dlg_sys_param to i8*
78 call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 16, i1 false)
79 store float 0.000000e+00, float* %total_active_bw, align 4
80 %1 = load i32, i32* %retval, align 4
81 ret i32 %1
82 }
83
84 define void @tryset(i8* nocapture %x) {
85 ; X64SSE-LABEL: tryset:
86 ; X64SSE: # %bb.0:
87 ; X64SSE-NEXT: movq $0, 56(%rdi)
88 ; X64SSE-NEXT: movq $0, 48(%rdi)
89 ; X64SSE-NEXT: movq $0, 40(%rdi)
90 ; X64SSE-NEXT: movq $0, 32(%rdi)
91 ; X64SSE-NEXT: movq $0, 24(%rdi)
92 ; X64SSE-NEXT: movq $0, 16(%rdi)
93 ; X64SSE-NEXT: movq $0, 8(%rdi)
94 ; X64SSE-NEXT: movq $0, (%rdi)
95 ; X64SSE-NEXT: retq
96 ;
97 ; X86SSE-LABEL: tryset:
98 ; X86SSE: # %bb.0:
99 ; X86SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
100 ; X86SSE-NEXT: movl $0, 60(%eax)
101 ; X86SSE-NEXT: movl $0, 56(%eax)
102 ; X86SSE-NEXT: movl $0, 52(%eax)
103 ; X86SSE-NEXT: movl $0, 48(%eax)
104 ; X86SSE-NEXT: movl $0, 44(%eax)
105 ; X86SSE-NEXT: movl $0, 40(%eax)
106 ; X86SSE-NEXT: movl $0, 36(%eax)
107 ; X86SSE-NEXT: movl $0, 32(%eax)
108 ; X86SSE-NEXT: movl $0, 28(%eax)
109 ; X86SSE-NEXT: movl $0, 24(%eax)
110 ; X86SSE-NEXT: movl $0, 20(%eax)
111 ; X86SSE-NEXT: movl $0, 16(%eax)
112 ; X86SSE-NEXT: movl $0, 12(%eax)
113 ; X86SSE-NEXT: movl $0, 8(%eax)
114 ; X86SSE-NEXT: movl $0, 4(%eax)
115 ; X86SSE-NEXT: movl $0, (%eax)
116 ; X86SSE-NEXT: retl
117 ;
118 ; X64SSE2-LABEL: tryset:
119 ; X64SSE2: # %bb.0:
120 ; X64SSE2-NEXT: movq $0, 56(%rdi)
121 ; X64SSE2-NEXT: movq $0, 48(%rdi)
122 ; X64SSE2-NEXT: movq $0, 40(%rdi)
123 ; X64SSE2-NEXT: movq $0, 32(%rdi)
124 ; X64SSE2-NEXT: movq $0, 24(%rdi)
125 ; X64SSE2-NEXT: movq $0, 16(%rdi)
126 ; X64SSE2-NEXT: movq $0, 8(%rdi)
127 ; X64SSE2-NEXT: movq $0, (%rdi)
128 ; X64SSE2-NEXT: retq
129 ;
130 ; X86SSE2-LABEL: tryset:
131 ; X86SSE2: # %bb.0:
132 ; X86SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
133 ; X86SSE2-NEXT: movl $0, 4(%eax)
134 ; X86SSE2-NEXT: movl $0, (%eax)
135 ; X86SSE2-NEXT: movl $0, 12(%eax)
136 ; X86SSE2-NEXT: movl $0, 8(%eax)
137 ; X86SSE2-NEXT: movl $0, 20(%eax)
138 ; X86SSE2-NEXT: movl $0, 16(%eax)
139 ; X86SSE2-NEXT: movl $0, 28(%eax)
140 ; X86SSE2-NEXT: movl $0, 24(%eax)
141 ; X86SSE2-NEXT: movl $0, 36(%eax)
142 ; X86SSE2-NEXT: movl $0, 32(%eax)
143 ; X86SSE2-NEXT: movl $0, 44(%eax)
144 ; X86SSE2-NEXT: movl $0, 40(%eax)
145 ; X86SSE2-NEXT: movl $0, 52(%eax)
146 ; X86SSE2-NEXT: movl $0, 48(%eax)
147 ; X86SSE2-NEXT: movl $0, 60(%eax)
148 ; X86SSE2-NEXT: movl $0, 56(%eax)
149 ; X86SSE2-NEXT: retl
150 ;
151 ; X64AVX-LABEL: tryset:
152 ; X64AVX: # %bb.0:
153 ; X64AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
154 ; X64AVX-NEXT: vmovups %ymm0, 32(%rdi)
155 ; X64AVX-NEXT: vmovups %ymm0, (%rdi)
156 ; X64AVX-NEXT: vzeroupper
157 ; X64AVX-NEXT: retq
158 ;
159 ; X86AVX-LABEL: tryset:
160 ; X86AVX: # %bb.0:
161 ; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
162 ; X86AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
163 ; X86AVX-NEXT: vmovups %ymm0, 32(%eax)
164 ; X86AVX-NEXT: vmovups %ymm0, (%eax)
165 ; X86AVX-NEXT: vzeroupper
166 ; X86AVX-NEXT: retl
167 tail call void @llvm.memset.p0i8.i64(i8* align 1 %x, i8 0, i64 64, i1 false)
168 ret void
169 }
170
171 define void @trycpy(i8* nocapture %x, i8* nocapture readonly %y) {
172 ; X64SSE-LABEL: trycpy:
173 ; X64SSE: # %bb.0:
174 ; X64SSE-NEXT: movq 24(%rsi), %rax
175 ; X64SSE-NEXT: movq %rax, 24(%rdi)
176 ; X64SSE-NEXT: movq 16(%rsi), %rax
177 ; X64SSE-NEXT: movq %rax, 16(%rdi)
178 ; X64SSE-NEXT: movq (%rsi), %rax
179 ; X64SSE-NEXT: movq 8(%rsi), %rcx
180 ; X64SSE-NEXT: movq %rcx, 8(%rdi)
181 ; X64SSE-NEXT: movq %rax, (%rdi)
182 ; X64SSE-NEXT: retq
183 ;
184 ; X86SSE-LABEL: trycpy:
185 ; X86SSE: # %bb.0:
186 ; X86SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
187 ; X86SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
188 ; X86SSE-NEXT: movl 28(%ecx), %edx
189 ; X86SSE-NEXT: movl %edx, 28(%eax)
190 ; X86SSE-NEXT: movl 24(%ecx), %edx
191 ; X86SSE-NEXT: movl %edx, 24(%eax)
192 ; X86SSE-NEXT: movl 20(%ecx), %edx
193 ; X86SSE-NEXT: movl %edx, 20(%eax)
194 ; X86SSE-NEXT: movl 16(%ecx), %edx
195 ; X86SSE-NEXT: movl %edx, 16(%eax)
196 ; X86SSE-NEXT: movl 12(%ecx), %edx
197 ; X86SSE-NEXT: movl %edx, 12(%eax)
198 ; X86SSE-NEXT: movl 8(%ecx), %edx
199 ; X86SSE-NEXT: movl %edx, 8(%eax)
200 ; X86SSE-NEXT: movl (%ecx), %edx
201 ; X86SSE-NEXT: movl 4(%ecx), %ecx
202 ; X86SSE-NEXT: movl %ecx, 4(%eax)
203 ; X86SSE-NEXT: movl %edx, (%eax)
204 ; X86SSE-NEXT: retl
205 ;
206 ; X64SSE2-LABEL: trycpy:
207 ; X64SSE2: # %bb.0:
208 ; X64SSE2-NEXT: movq 24(%rsi), %rax
209 ; X64SSE2-NEXT: movq %rax, 24(%rdi)
210 ; X64SSE2-NEXT: movq 16(%rsi), %rax
211 ; X64SSE2-NEXT: movq %rax, 16(%rdi)
212 ; X64SSE2-NEXT: movq (%rsi), %rax
213 ; X64SSE2-NEXT: movq 8(%rsi), %rcx
214 ; X64SSE2-NEXT: movq %rcx, 8(%rdi)
215 ; X64SSE2-NEXT: movq %rax, (%rdi)
216 ; X64SSE2-NEXT: retq
217 ;
218 ; X86SSE2-LABEL: trycpy:
219 ; X86SSE2: # %bb.0:
220 ; X86SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
221 ; X86SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
222 ; X86SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
223 ; X86SSE2-NEXT: movsd %xmm0, 24(%eax)
224 ; X86SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
225 ; X86SSE2-NEXT: movsd %xmm0, 16(%eax)
226 ; X86SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
227 ; X86SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
228 ; X86SSE2-NEXT: movsd %xmm1, 8(%eax)
229 ; X86SSE2-NEXT: movsd %xmm0, (%eax)
230 ; X86SSE2-NEXT: retl
231 ;
232 ; X64AVX-LABEL: trycpy:
233 ; X64AVX: # %bb.0:
234 ; X64AVX-NEXT: vmovups (%rsi), %ymm0
235 ; X64AVX-NEXT: vmovups %ymm0, (%rdi)
236 ; X64AVX-NEXT: vzeroupper
237 ; X64AVX-NEXT: retq
238 ;
239 ; X86AVX-LABEL: trycpy:
240 ; X86AVX: # %bb.0:
241 ; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
242 ; X86AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
243 ; X86AVX-NEXT: vmovups (%ecx), %ymm0
244 ; X86AVX-NEXT: vmovups %ymm0, (%eax)
245 ; X86AVX-NEXT: vzeroupper
246 ; X86AVX-NEXT: retl
247 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %x, i8* align 1 %y, i64 32, i1 false)
248 ret void
249 }
250
251 declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) argmemonly nounwind
252 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #2
253
None ; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefix=X87
1 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse | FileCheck %s -check-prefix=X87
2 ; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s -check-prefix=NOX87
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse | FileCheck %s -check-prefix=NOX87
4 ; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse | FileCheck %s -check-prefix=NOX87
5 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse2 | FileCheck %s -check-prefix=NOX87
0 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefixes=X8732,X87
1 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse | FileCheck %s -check-prefixes=X8732,X87
2 ; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s -check-prefixes=NOX8732,NOX87
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse | FileCheck %s -check-prefixes=NOX8732,NOX87
4 ; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse | FileCheck %s -check-prefixes=NOX8732,NOX87
5 ; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,-sse2 | FileCheck %s -check-prefixes=X8732_SSE,NOX87
66
77 define void @test(i32 %i, i64 %l, float* %pf, double* %pd, fp128* %pld) nounwind readnone {
88 ; X87-LABEL: test:
1111 ; NOX87-NOT: {{ }}f{{.*}}
1212
1313 ; X87: fild
14 ; NOX87: __floatunsisf
14 ; NOX8732: __floatunsisf
1515 %tmp = uitofp i32 %i to float
1616
17 ; X87: fild
18 ; NOX87: __floatdisf
17 ; X8732: fild
18 ; NOX8732: __floatdisf
1919 %tmp1 = sitofp i64 %l to float
2020
21 ; X87: fadd
22 ; NOX87: __addsf3
21 ; X8732: fadd
22 ; NOX8732: __addsf3
2323 %tmp2 = fadd float %tmp, %tmp1
2424
25 ; X87: fstp
25 ; X8732: fstp
2626 store float %tmp2, float* %pf
2727
2828 ; X87: fild